专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US07543106B2 Apparatus and method for controlling refresh of semiconductor memory device according to positional information of memory chips 有权
标题翻译：根据存储芯片的位置信息控制半导体存储器件的刷新的装置和方法
公开(公告)号：US07543106B2
公开(公告)日：2009-06-02
申请号：US11504421
申请日：2006-08-15
申请人： Joo-Sun Choi
发明人： Joo-Sun Choi
IPC分类号： G06F12/16 , G11C7/00
CPC分类号： G06F13/1636 , G11C11/406 , G11C11/40611 , G11C11/40615 , G11C2211/4061
摘要： A memory controller controlling a plurality of semiconductor memory devices includes a refresh control circuit controlling refresh operations of the semiconductor memory devices according to positional information of memory chips of the memory devices. The refresh control circuit classifies the semiconductor memory devices into first and second groups and sets an auto refresh interval of the semiconductor memory devices belong to the first group and an auto refresh interval of the semiconductor memory devices belong to the second group different from each other.
摘要翻译：控制多个半导体存储器件的存储器控制器包括根据存储器件的存储器芯片的位置信息控制半导体存储器件的刷新操作的刷新控制电路。刷新控制电路将半导体存储器件分为第一组和第二组，并且设置属于第一组的半导体存储器件的自动刷新间隔，并且属于第二组的半导体存储器件的自动刷新间隔彼此不同。

32. 发明授权

US07366052B2 Memory device, memory system and method of inputting/outputting data into/from the same 有权
标题翻译：存储器件，存储器系统以及从其输入/输出数据的方法
公开(公告)号：US07366052B2
公开(公告)日：2008-04-29
申请号：US11582290
申请日：2006-10-17
申请人： Joo-Sun Choi
发明人： Joo-Sun Choi
IPC分类号： G01C8/00
CPC分类号： G11C7/1039 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C2207/107
摘要： A memory device includes a memory cell array, a row decoding section, a K-bit prefetch section and an output buffer section. The row decoding section decodes a row address in response to a first clock, to activate one of the word lines corresponding to the decoded row address. The K-bit prefetch section decodes a column address in response to a second clock and prefetches K data from K memory cells connected to the activated word line and corresponds to the decoded column address, in response to a second clock, where a frequency of the second clock is 1/M of that of the first clock. The output buffer section outputs the K prefetched data as a data stream in response to a third clock. Therefore, a burden from the physical limit of the access speed may be alleviated when the data I/O speed is increased.
摘要翻译：存储器件包括存储单元阵列，行解码部分，K位预取部分和输出缓冲器部分。行解码部分响应于第一时钟解码行地址，以激活对应于解码的行地址的字线之一。 K位预取部分响应于第二时钟对列地址进行解码，并且响应于第二时钟从与连接到激活字线的K个存储器单元中的K个存储器单元相对应地对应于解码的列地址，第二个时钟是第一个时钟的1 / M。输出缓冲器部分响应于第三个时钟输出K个预取数据作为数据流。因此，当数据I / O速度增加时，可以减轻访问速度的物理限制的负担。

33. 发明申请

US20080052482A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING CLOCK LATENCY ACCORDING TO REORDERING OF BURST DATA 失效
标题翻译：半导体存储器件和控制根据脉冲数据的时钟延迟的方法
公开(公告)号：US20080052482A1
公开(公告)日：2008-02-28
申请号：US11775780
申请日：2007-07-10
申请人： Joo-Sun CHOI , Won-Chang JUNG , Hi-Choon LEE , Sung-Min YIM , Chul-Woo PARK , Won-Il BAE
发明人： Joo-Sun CHOI , Won-Chang JUNG , Hi-Choon LEE , Sung-Min YIM , Chul-Woo PARK , Won-Il BAE
IPC分类号： G06F12/00
CPC分类号： G11C7/1045 , G11C7/1072
摘要： In an embodiment, a semiconductor memory device includes a clock latency that can be controlled responsive to whether or not an output order of burst data is reordered. The semiconductor memory device may comprise a control unit and a latency control unit. The control unit may generate a latency control signal having a logic level that varies depending on whether or not an output order of burst data is reordered. The latency control unit may control a latency value in response to the latency control signal. The semiconductor memory device and the method of controlling the latency value responsive to a reordering of the burst data allow for an optimally fast memory access time.
摘要翻译：在一个实施例中，半导体存储器件包括响应于突发数据的输出顺序是否被重新排序而被控制的时钟等待时间。半导体存储器件可以包括控制单元和等待时间控制单元。控制单元可以生成具有根据突发数据的输出顺序是否被重新排列而变化的逻辑电平的等待时间控制信号。延迟控制单元可以响应于等待时间控制信号来控制等待时间值。半导体存储器件和响应于突发数据的重排序来控制延迟值的方法允许最佳的快速存储器存取时间。

34. 发明申请

US20070162689A1 Memory controller, memory module and memory system having the same, and method of controlling the memory system 审中-公开
标题翻译：具有相同的存储器控制器，存储器模块和存储器系统以及控制存储器系统的方法
公开(公告)号：US20070162689A1
公开(公告)日：2007-07-12
申请号：US11649477
申请日：2007-01-04
申请人： Joo-Sun Choi
发明人： Joo-Sun Choi
IPC分类号： G06F13/28
CPC分类号： G06F13/1615
摘要： A memory system includes a memory controller and a plurality of first memory components. The memory controller has a plurality of I/O channels, each of the I/O channels including a command/address bus and a data bus. The plurality of the first memory components are respectively coupled to the memory controller through the plurality of I/O channels. The memory controller respectively transmits commands/addresses and data to the plurality of first memory components through the plurality of I/O channels in order to independently control the plurality of first memory components.
摘要翻译：存储器系统包括存储器控制器和多个第一存储器组件。存储器控制器具有多个I / O通道，每个I / O通道包括命令/地址总线和数据总线。多个第一存储器组件通过多个I / O通道分别耦合到存储器控制器。存储器控制器通过多个I / O通道分别向多个第一存储器组件发送命令/地址和数据，以便独立地控制多个第一存储器组件。

35. 发明申请

US20070133247A1 Memory system having point-to-point (PTP) and point-to-two-point (PTTP) links between devices 有权
标题翻译：在设备之间具有点到点（PTP）和点到两点（PTTP）链路的存储器系统
公开(公告)号：US20070133247A1
公开(公告)日：2007-06-14
申请号：US11603648
申请日：2006-11-22
申请人： Jae-Jun Lee , Joo-Sun Choi , Kyu-Hyoun Kim , Kwang-Soo Park
发明人： Jae-Jun Lee , Joo-Sun Choi , Kyu-Hyoun Kim , Kwang-Soo Park
IPC分类号： G11C5/06
CPC分类号： G11C5/063
摘要： A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary memories. A first connection element, such as a connector or solder, connects the memory module to a mother board. A second connection element, such as a connector or solder, connects at least one other of the first and second primary and first and second secondary memories to the mother board. At least one of the memories on the first memory module is coupled to at least one of the other memories. The memory system also includes a memory controller which is connected to the primary memories by a point-to-two-point link.
摘要翻译：存储器系统具有第一和第二主存储器以及分别耦合到第一和第二主存储器的第一和第二辅助存储器，耦合器包括至少一个点到点连接。存储器模块包括第一和第二主要和第一和第二辅助存储器中的至少两个。诸如连接器或焊料的第一连接元件将存储器模块连接到母板。诸如连接器或焊料的第二连接元件将第一和第二初级和第二和第二辅助存储器中的至少一个连接到母板。第一存储器模块上的至少一个存储器耦合到至少一个其他存储器。存储器系统还包括存储器控制器，其通过点对二点链接连接到主存储器。

36. 发明授权

US06286077B1 Synchronous semiconductor memory device with a plurality of memory modules which has an additional function for masking a data strobe signal outputted from each memory module 失效
标题翻译：具有多个存储器模块的同步半导体存储器件，其具有用于屏蔽从每个存储器模块输出的数据选通信号的附加功能
公开(公告)号：US06286077B1
公开(公告)日：2001-09-04
申请号：US09218617
申请日：1998-12-22
申请人： Joo Sun Choi , Seok Cheol Yoon
发明人： Joo Sun Choi , Seok Cheol Yoon
IPC分类号： G06F1200
CPC分类号： G11C7/1066 , G11C7/1006
摘要： A chip set memory controller having a data strobe mask function is disclosed. The controller includes first through N-th memory modules operated in synchronous with a clock signal outputted from the chip set memory controller, whereby the data outputted from each memory module are masked by a data mask signal outputted from the chip set memory controller, and the operation of the data outputted from each memory module is controlled by a data strobe signal outputted from each memory module, for thereby implementing a reverse compatibility of a DQM function by additionally installing a pin in a DDR SDRAM and masking a data strobe signal.
摘要翻译：公开了具有数据选通掩模功能的芯片组存储器控制器。控制器包括与从芯片组存储器控制器输出的时钟信号同步操作的第一至第N存储器模块，由此从每个存储器模块输出的数据由芯片组存储器控制器输出的数据屏蔽信号屏蔽，从每个存储器模块输出的数据的操作由每个存储器模块输出的数据选通信号控制，从而通过在DDR SDRAM中额外安装引脚并屏蔽数据选通信号来实现DQM功能的反向兼容性。

37. 发明授权

US06240033B1 Antifuse circuitry for post-package DRAM repair 有权
标题翻译：用于后封装DRAM修复的防漏电路
公开(公告)号：US06240033B1
公开(公告)日：2001-05-29
申请号：US09479665
申请日：2000-01-10
申请人： Woodward Yang , Joo Sun Choi , Jae Kyung Wee , Young Ho Seol , Jin Keun Oh , Phil Jung Kim , Ho Youe Cho
发明人： Woodward Yang , Joo Sun Choi , Jae Kyung Wee , Young Ho Seol , Jin Keun Oh , Phil Jung Kim , Ho Youe Cho
IPC分类号： G11C700
CPC分类号： G11C29/781 , G11C17/18
摘要： The anti-fuse circuit includes three sub-blocks: a multiplexer having inputs of control signals and addresses and yielding the activation of a programming signal and program addresses; a programming voltage generator consisting of an oscillator and a charge pump; and an anti-fuse unit circuits for the program/read of anti-fuse states. For an anti-fuse program at the special test mode, a program address generation circuit having inputs of control signals and addresses activates the programming voltage generator and makes a special or program address for selection of anti-fuse. In the normal mode, the program address generation circuit and an internal power generator remain at an inactive state. In anti-fuse unit circuit, the program address and the programming voltage signal from the programming voltage generator serve to switch the terminal of the anti-fuse up to a programming voltage level when the anti-fuse is selected for programming of anti-fuse elements.
摘要翻译：反熔丝电路包括三个子块：具有控制信号和地址的输入并产生编程信号和程序地址的激活的多路复用器; 由振荡器和电荷泵组成的编程电压发生器; 以及用于编程/读取反熔丝状态的反熔丝单元电路。对于在特殊测试模式下的反熔丝程序，具有控制信号和地址的输入的程序地址产生电路激活编程电压发生器，并产生用于选择反熔丝的特殊或程序地址。在正常模式中，程序地址产生电路和内部发电机保持在非工作状态。在反熔丝单元电路中，编程电压发生器的程序地址和编程电压信号用于在反熔丝被选择用于编程抗熔丝元件时将反熔丝的端子切换到编程电压电平。

38. 发明授权

US09036439B2 Semiconductor memory device having improved refresh characteristics 有权
标题翻译：具有改善的刷新特性的半导体存储器件
公开(公告)号：US09036439B2
公开(公告)日：2015-05-19
申请号：US13548484
申请日：2012-07-13
申请人： Jung-sik Kim , Cheol Kim , Sang-ho Shin , Jung-bae Lee , Chan-yong Lee , Sung-min Yim , Tae-seong Jang , Joo-sun Choi
发明人： Jung-sik Kim , Cheol Kim , Sang-ho Shin , Jung-bae Lee , Chan-yong Lee , Sung-min Yim , Tae-seong Jang , Joo-sun Choi
IPC分类号： G11C29/08 , G11C7/00 , G11C29/50 , G11C11/406 , G11C5/04 , G11C11/40
CPC分类号： G11C29/50016 , G11C5/04 , G11C11/40 , G11C11/406 , G11C11/40615 , G11C11/40622 , G11C2211/4061 , G11C2211/4065
摘要： A semiconductor memory device having improved refresh characteristics includes a memory array including a plurality of memory cells; a test unit configured to test refresh characteristics of the memory array and generate a first fail address signal; a storage unit configured to store the first fail address signal; and a refresh unit configured to perform a refresh operation on the memory array, wherein the refresh unit is configured to receive the first fail address signal from the storage unit, perform the refresh operation on a first memory cell that does not correspond to the first fail address signal according to a first period, and perform the refresh operation on a second memory cell that corresponds to the first fail address signal according to a second period that is shorter than the first period.
摘要翻译：具有改进的刷新特性的半导体存储器件包括包括多个存储器单元的存储器阵列; 测试单元，被配置为测试所述存储器阵列的刷新特性并产生第一故障地址信号; 存储单元，被配置为存储所述第一失败地址信号; 以及刷新单元，被配置为对所述存储器阵列执行刷新操作，其中所述刷新单元被配置为从所述存储单元接收所述第一故障地址信号，对与所述第一故障不对应的第一存储器单元执行刷新操作根据第一期间的地址信号，根据比第一期间短的第二期间对与第一失败地址信号对应的第二存储单元进行刷新动作。

39. 发明授权

US08817549B2 Integrated circuit memory device 有权
标题翻译：集成电路存储器件
公开(公告)号：US08817549B2
公开(公告)日：2014-08-26
申请号：US13478774
申请日：2012-05-23
申请人： Choong-Sun Shin , Joo-Sun Choi
发明人： Choong-Sun Shin , Joo-Sun Choi
IPC分类号： G11C7/10
CPC分类号： G11C5/04 , G11C5/025 , G11C7/10 , G11C8/12 , G11C11/408 , G11C11/4093 , G11C11/4097
摘要： A semiconductor memory device includes a plurality of memory regions formed on one chip, each of the memory regions having a plurality of volatile memory cells that are formed with a density or capacity of 2^K bits, where K is an integer greater than or equal to 0, and a plurality of input/output (I/O) terminals for inputting and outputting data of the volatile memory cells, and at least one peripheral region that controls a write operation for writing data into the memory regions and a read operation for reading data from the memory regions based on a command and an address input from outside. Thus, a total or entire density of the memory regions corresponds to a non-standard (or ‘interim’) density so that the semiconductor memory device may have an interim density.
摘要翻译：半导体存储器件包括形成在一个芯片上的多个存储器区域，每个存储器区域具有多个易失性存储器单元，其形成为2K比特的密度或容量，其中K是大于或等于的整数以及用于输入和输出易失性存储器单元的数据的多个输入/输出（I / O）端子，以及控制用于将数据写入存储区域的写入操作的至少一个外围区域，以及用于基于从外部输入的命令和地址从存储器区域读取数据。因此，存储区域的总体或整个密度对应于非标准（或“临时”）密度，使得半导体存储器件可具有临时密度。

40. 发明授权

US08588017B2 Memory circuits, systems, and modules for performing DRAM refresh operations and methods of operating the same 有权
标题翻译：用于执行DRAM刷新操作的存储器电路，系统和模块及其操作方法
公开(公告)号：US08588017B2
公开(公告)日：2013-11-19
申请号：US13236972
申请日：2011-09-20
申请人： Chul-woo Park , Young-hyun Jun , Joo-sun Choi , Hong-sun Hwang
发明人： Chul-woo Park , Young-hyun Jun , Joo-sun Choi , Hong-sun Hwang
IPC分类号： G11C29/00
CPC分类号： G11C29/808 , G06F2213/0038 , G11C11/40618 , G11C11/40622 , G11C11/40626 , G11C2211/4062
摘要： A memory module can include a plurality of dynamic memory devices that each can include a dynamic memory cell array with respective regions therein, where the plurality of dynamic memory devices can be configured to operate the respective regions responsive to a command. A DRAM management unit can be on the module and coupled to the plurality of dynamic memory devices, and can include a memory device operational parameter storage circuit that is configured to store memory device operational parameters for the respective regions to affect operation of the respective regions responsive to the command.
摘要翻译：存储器模块可以包括多个动态存储器设备，每个动态存储器设备可以包括其中具有其中各自区域的动态存储器单元阵列，其中多个动态存储器设备可被配置为响应于命令操作相应的区域。 DRAM管理单元可以在模块上并且耦合到多个动态存储器设备，并且可以包括存储器设备操作参数存储电路，其被配置为存储用于各个区域的存储器设备操作参数以影响相应区域的操作命令。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式