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31. 发明申请

US20100064109A1 Managing storage units in multi-core and multi-threaded systems 有权
标题翻译：管理多核和多线程系统中的存储单元
公开(公告)号：US20100064109A1
公开(公告)日：2010-03-11
申请号：US12232188
申请日：2008-09-11
申请人： David Michael Bull , Emre Ozer
发明人： David Michael Bull , Emre Ozer
IPC分类号： G06F12/02
CPC分类号： G06F12/126 , G06F9/3806 , G06F9/3851
摘要： A data processing apparatus is provided comprising processing circuitry for executing multiple program threads. At least one storage unit is shared between the multiple program threads and comprises multiple entries, each entry for storing a storage item either associated with a high priority program thread or a lower priority program thread. A history storage for retaining a history field for each of a plurality of blocks of the storage unit is also provided. On detection of a high priority storage item being evicted from the storage unit as a result of allocation to that entry of a lower priority storage item, the history field for the block containing that entry is populated with an indication of the evicted high priority storage item. When later a high priority storage item is allocated to a selected entry of the storage unit, a comparison operation between the allocated high priority storage item and the indication in the history field for the block containing the selected entry is carried out, and on detection of a match condition a lock indication associated with that entry is set to inhibit further eviction of that high priority storage item.
摘要翻译：提供了一种数据处理装置，包括用于执行多个程序线程的处理电路。至少一个存储单元在多个程序线程之间共享并且包括多个条目，每个条目用于存储与高优先级程序线程或较低优先级程序线程相关联的存储项目。还提供了用于保存存储单元的多个块中的每一个的历史字段的历史存储器。在检测到作为对较低优先级存储项目的该条目的分配的结果被从存储单元驱逐的高优先级存储项目时，包含该条目的块的历史字段填充有被驱逐的高优先级存储项目的指示。当稍后将高优先级存储项目分配给存储单元的所选条目时，执行所分配的高优先级存储项目与包含所选择的条目的块的历史字段中的指示之间的比较操作，并且在检测到匹配条件与该条目相关联的锁定指示被设置为禁止进一步驱逐该高优先级存储项目。

32. 发明申请

US20090161442A1 Data Processing System 有权
标题翻译：数据处理系统
公开(公告)号：US20090161442A1
公开(公告)日：2009-06-25
申请号：US12085901
申请日：2005-12-02
申请人： David New , Paul Darren Hoxey , David Michael Bull , Shidhartha Das
发明人： David New , Paul Darren Hoxey , David Michael Bull , Shidhartha Das
IPC分类号： G11C7/00
CPC分类号： G11C7/08 , G11C7/24 , G11C11/4125 , G11C29/12 , G11C29/12005 , G11C29/26
摘要： A data processing system comprising a memory array having a plurality of memory cells (240-246) and read circuitry (310,320) for reading a logic value stored in one of the plurality of memory cells. The read circuitry (310,320) is operable perform two substantially simultaneous reads of the stored logic value. A voltage controller is provided and is operable to selectively vary a level of a supply voltage to the memory array. Detection circuitry is provided (330) for detecting, in dependence upon the two substantially simultaneous reads, when the supply voltage level causes the read result to be unreliable.
摘要翻译：一种数据处理系统，包括具有多个存储单元（240-246）和用于读取存储在所述多个存储单元之一中的逻辑值的读取电路（310,320）的存储器阵列。读取电路（310,320）可操作地执行存储的逻辑值的两个基本上同时的读取。提供电压控制器并且可操作以选择性地改变对存储器阵列的电源电压的电平。提供检测电路（330），用于根据两个基本上同时的读取来检测供电电压电平是否导致读取结果不可靠。

33. 发明申请

US20090106616A1 Integrated circuit using speculative execution 有权
标题翻译：集成电路采用推测执行
公开(公告)号：US20090106616A1
公开(公告)日：2009-04-23
申请号：US12285796
申请日：2008-10-14
申请人： Emre Ozer , David Michael Bull , Shidhartha Das
发明人： Emre Ozer , David Michael Bull , Shidhartha Das
IPC分类号： G06F11/07
CPC分类号： G06F9/3842 , G06F9/3861 , G06F9/3869
摘要： An integrated circuit 2 is provided with a plurality of pipeline stages 10. These pipeline stages 10 have speculative processing control circuitry 12 which permits speculative processing in downstream pipeline stages and triggers a first error recovery operation (partial pipeline flushing) if such speculative processing is determined to be based upon an error. The pipeline stage 10 further includes speculative error detecting circuitry 14 which generates a prediction nc regarding whether or not the processing circuitry 18 will produce an error. This prediction is used to trigger a second error recovery operation (partial pipeline stall). This second error recovery operation has a lower performance penalty than the first error recovery operation.
摘要翻译：集成电路2设置有多个流水线级10.这些流水线级10具有推测性处理控制电路12，其允许下游流水线级的推测性处理，并且如果确定了这种推测性处理，则触发第一错误恢复操作（部分流水线冲洗）基于错误。流水线级10还包括推测性错误检测电路14，其产生关于处理电路18是否将产生错误的预测nc。该预测用于触发第二次错误恢复操作（部分流水线停止）。该第二错误恢复操作具有比第一错误恢复操作更低的性能损失。

34. 发明申请

US20080086624A1 Latch to block short path violation 有权
标题翻译：锁定阻止短路违规
公开(公告)号：US20080086624A1
公开(公告)日：2008-04-10
申请号：US11638703
申请日：2006-12-14
申请人： David Michael Bull , Shidhartha Das
发明人： David Michael Bull , Shidhartha Das
IPC分类号： G06F15/76
CPC分类号： G11C19/00
摘要： An integrated circuit 2 includes processing pipeline stages formed of an input register 8, processing circuit 10′, 10″ and an output register 12. The output register 12 employs speculative sampling and uses a subsequent speculation period during which any change in its input is detected and used to indicate a speculation error. In order to reduce the chances of a race condition giving rise to a false positive detection of a speculation error due to a too rapid signal propagation through the processing circuitry 10′, 10″, a transparent latch 14 is disposed at the approximate midpoint, measured in terms of propagation delay, within the processing circuitry 10′, 10″. This transparent latch 14 is non-transmissive during the speculation period of the output register 12 so as to prevent any new signal propagating from the input register 8 during the speculation period from reaching the output register 12.
摘要翻译：集成电路2包括由输入寄存器8，处理电路10'，10“和输出寄存器12形成的处理流水线级。输出寄存器12采用推测采样，并使用随后的推测周期，在此期间检测其输入中的任何变化并用于指示猜测误差。为了减少由于通过处理电路10'，10“的信号传播太快导致的猜测误差的假阳性检测的竞争条件的机会，透明锁存器14设置在大致中点处，在传播延迟方面测量，处理电路10'，10“内。该透明锁存器14在输出寄存器12的推测周期期间是非透射的，以便在推测期间防止任何新的信号从输入寄存器8传播到达输出寄存器12。

35. 发明授权

US06826670B2 Accessing memory units in a data processing apparatus 有权
标题翻译：访问数据处理设备中的存储器单元
公开(公告)号：US06826670B2
公开(公告)日：2004-11-30
申请号：US10158105
申请日：2002-05-31
申请人： Peter Guy Middleton , David Michael Bull , Gary Campbell
发明人： Peter Guy Middleton , David Michael Bull , Gary Campbell
IPC分类号： G06F1200
CPC分类号： G06F12/0888 , G06F12/0215 , Y02D10/13
摘要： The present invention relates to a technique for accessing memory units in a data processing apparatus. The data processing apparatus comprises of plurality of memory units for storing data values, a processor core for issuing an access request specifying an access to be made to the memory units in relation to a data value, and a memory controller for performing the access specified by the access request. Attribute generation logic is provided for determining from the access request one or more predetermined attributes verifying which of the memory units should be used when performing the access. However, the memory controller does not wait until such determination has been performed by the attribute generation logic before beginning the access. Instead, prediction logic is arranged to predict the one or more predetermined attributes, and clock generation logic is responsive to the predictive predetermined attributes from the prediction logic to select which one of the memory units is to be clocked during performance of the access, and to issue a clock signal to that memory unit. Checking logic is then provided to determine whether the predetermined attributes generated by the attribute generation logic agree with the predicted predetermined attributes, and if not, to reinitiate the access, in which event the clock generation logic is arranged to reselect one of the memory units using the predetermined attributes as determined by the attribute generation logic. This approach enables high speed processing of access requests, whilst achieving significant power savings over prior art systems where multiple memory units are clocked speculatively in parallel.
摘要翻译：本发明涉及用于访问数据处理装置中的存储单元的技术。数据处理装置包括用于存储数据值的多个存储器单元，用于发出指定对数据值对存储器单元进行访问的访问请求的处理器核心，以及用于执行由数据值指定的访问的存储器控制器访问请求。提供属性生成逻辑用于从访问请求确定一个或多个预定属性，以便在执行访问时验证哪个存储单元应被使用。然而，存储器控制器不等待直到在开始访问之前由属性生成逻辑执行这样的确定。相反，预测逻辑被布置为预测一个或多个预定属性，并且时钟生成逻辑响应来自预测逻辑的预测预定属性，以选择在执行访问期间要计时的哪个存储器单元，以及向该存储单元发出时钟信号。然后提供检查逻辑以确定由属性生成逻辑生成的预定属性是否与预测的预定属性一致，如果不是，则重新启动访问，在哪种情况下，时钟生成逻辑被设置为使用由属性生成逻辑确定的预定属性。这种方法可以实现对访问请求的高速处理，同时相对于其中多个存储器单元并行地推测地计时的现有技术系统实现显着的功率节省。

36. 发明授权

US06532553B1 Debugging data processing systems 有权
标题翻译：调试数据处理系统
公开(公告)号：US06532553B1
公开(公告)日：2003-03-11
申请号：US09407846
申请日：1999-09-29
申请人： David John Gwilt , Andrew Christopher Rose , Peter Guy Middleton , David Michael Bull
发明人： David John Gwilt , Andrew Christopher Rose , Peter Guy Middleton , David Michael Bull
IPC分类号： H02H305
CPC分类号： G06F11/3636 , G06F9/30003 , G06F9/3005
摘要： A data processing system is provided having a main processor 4 and a coprocessor 26. When in a debug mode, the main processor 4 and the coprocessor 26 are supplied with different instructions. The coprocessor 26 is supplied with a coprocessor debug data generation instruction (MCR) whilst the main processor 4 is supplied with a main processor data capture instruction (LDR). The coprocessor 26 responds to the MCR instruction by controlling debug data representing state of the data processing apparatus 2 to be placed upon a data bus 24 from where it is read by the main processor 4 under control of the LDR instruction.
摘要翻译：提供了具有主处理器4和协处理器26的数据处理系统。当处于调试模式时，向主处理器4和协处理器26提供不同的指令。协处理器26被提供有协处理器调试数据生成指令（MCR），而主处理器4被提供有主处理器数据捕获指令（LDR）。协处理器26通过控制表示数据处理装置2的状态的调试数据来响应MCR指令，数据处理装置2将被放置在数据总线24上，从LDR指令的控制下由主处理器4读取数据总线24。

37. 发明授权

US08738971B2 Limiting certain processing activities as error rate probability rises 有权
标题翻译：限制某些处理活动的错误率概率上升
公开(公告)号：US08738971B2
公开(公告)日：2014-05-27
申请号：US13313057
申请日：2011-12-07
申请人： Frederic Claude Marie Piry , Luca Scalabrino , David Michael Bull
发明人： Frederic Claude Marie Piry , Luca Scalabrino , David Michael Bull
IPC分类号： G06F11/00
CPC分类号： G06F11/0721 , G06F11/076 , G06F11/3024 , G06F11/3058
摘要： A data processing apparatus configured to operate in a voltage and frequency operating region that is located beyond a safe region where errors do not arise, but within operating region limits such that the errors are rare. The data processing apparatus comprises: error detection circuitry and error recovery circuitry; the error detection circuitry being configured to determine if a signal sampled in the processing apparatus changes within a time window occurring after the signal has been sampled and during a same clock cycle as the sampling and to signal an error if the signal does change. The data processing apparatus further comprises performance control circuitry configured to determine when the data processing apparatus is operating close to the operating region limits where an error rate is raised and in response to determining operation close to the operating region limits to modify a behavior of the data processing apparatus by at least one of: limiting speculative processing, and selecting timing insensitive processing paths and circuitry.
摘要翻译：一种数据处理装置，被配置为在电压和频率操作区域中操作，所述电压和频率操作区域位于不存在错误的安全区域之外，但是在操作区域限制内，使得错误是罕见的。数据处理装置包括：错误检测电路和错误恢复电路; 所述错误检测电路被配置为确定在所述处理装置中采样的信号是否在所述信号被采样之后并且在与所述采样相同的时钟周期期间发生的时间窗内改变，并且如果所述信号确实改变则发送信号。数据处理装置还包括性能控制电路，其被配置为确定数据处理装置何时操作接近错误率提高的操作区域限制，并且响应于确定接近操作区域限制的操作来修改数据的行为处理装置中的至少一个：限制推测处理，以及选择不敏感时序的处理路径和电路。

38. 发明授权

US08639987B2 Data processing apparatus and method using monitoring circuitry to control operating parameters 有权
标题翻译：数据处理装置和方法，使用监控电路来控制运行参数
公开(公告)号：US08639987B2
公开(公告)日：2014-01-28
申请号：US12929848
申请日：2011-02-18
申请人： Paul Nicholas Whatmough , David Michael Bull , Shidhartha Das
发明人： Paul Nicholas Whatmough , David Michael Bull , Shidhartha Das
IPC分类号： G06F11/00
CPC分类号： G06F1/324 , G06F1/3296 , G06F11/076 , Y02D10/126 , Y02D10/172
摘要： A data processing apparatus and method are provided that use monitoring circuitry to control operating parameters of the data processing apparatus. The data processing apparatus has functional circuitry for performing data processing, the functional circuitry including error correction circuitry configured to detect errors in operation of the functional circuitry and to repair those errors in operation. Tuneable monitoring circuitry monitors a characteristic indicative of changes in signal propagation delay within the functional circuitry and produces a control signal dependent on the monitored characteristic. In a continuous tuning mode operation, the tuneable monitoring circuitry modifies the dependency between the monitored characteristic and the control signal in dependence upon certain characteristics of the errors detected by the error correction circuitry. An operating parameter controller is then arranged, in the continuous mode of operation, to control one or more performance controlling operating parameters of the data processing apparatus in dependence upon the control signal. This enables efficient and robust control of those operating parameters in response to changes in environmental conditions.
摘要翻译：提供一种使用监视电路来控制数据处理装置的操作参数的数据处理装置和方法。所述数据处理装置具有用于执行数据处理的功能电路，所述功能电路包括错误校正电路，其被配置为检测功能电路的操作中的错误并修复这些操作中的错误。可调节监控电路监视指示功能电路内的信号传播延迟的变化的特性，并产生取决于被监测特性的控制信号。在连续调谐模式操作中，可调谐监视电路根据由纠错电路检测到的错误的某些特性来修改监视特性和控制信号之间的相关性。然后，在连续操作模式下，设置操作参数控制器，以根据控制信号控制数据处理装置的一个或多个性能控制操作参数。这可以响应于环境条件的变化而对这些操作参数进行有效和鲁棒的控制。

39. 发明授权

US08639975B2 Error management within a data processing system 有权
标题翻译：数据处理系统中的错误管理
公开(公告)号：US08639975B2
公开(公告)日：2014-01-28
申请号：US12926436
申请日：2010-11-17
申请人： Paul Nicholas Whatmough , David Michael Bull , Shidhartha Das , Daniel Kershaw
发明人： Paul Nicholas Whatmough , David Michael Bull , Shidhartha Das , Daniel Kershaw
IPC分类号： G06F11/00
CPC分类号： G06F11/0763 , H03M13/09
摘要： A data processing system 2 is used to perform processing operations to generate a result value. The processing circuitry which generates the result value has an error resistant portion 32 and an error prone portion 30. The probability of an error in operation of the error prone portion for a given set of operating parameters (clk, V) is greater than the probability of an error for that same set of operating parameters within the error resistant portion. Error detection circuitry 38 detects any errors arising in the error prone portion. Parameter control circuitry 40 responds to detected errors to adjust the set of operating parameters to maintain a non-zero error rate in the errors detected by the error detection circuitry. Errors within the one or more bits generated by the error prone portion are not corrected as the apparatus is tolerant to errors occurring within such bit values of the result value.
摘要翻译：数据处理系统2用于执行处理操作以产生结果值。产生结果值的处理电路具有抗错部分32和易错部分30.对于给定的一组操作参数（clk，V），错误倾向部分的操作错误的概率大于概率在该抗误差部分内的相同的一组操作参数的误差。错误检测电路38检测在易错部分中产生的任何错误。参数控制电路40对检测到的错误进行响应，以调整该组操作参数，以便在错误检测电路检测到的错误中保持非零错误率。由误差容易部分产生的一个或多个位内的错误不会被校正，因为该装置对结果值的这些比特值内发生的错误是容忍的。

40. 发明申请

US20130166952A1 DATA PROCESSING APPARATUS WITH AN EXECUTION PIPELINE AND ERROR RECOVERY UNIT AND METHOD OF OPERATING THE DATA PROCESSING APPARATUS 有权
标题翻译：具有执行管线和错误恢复单元的数据处理装置及操作数据处理装置的方法
公开(公告)号：US20130166952A1
公开(公告)日：2013-06-27
申请号：US13336432
申请日：2011-12-23
申请人： Guillaume Schon , Mélanie Emanuelle Lucie Teyssier , Frederic Claude Marie Piry , Luca Scalabrino , David Michael Bull
发明人： Guillaume Schon , Mélanie Emanuelle Lucie Teyssier , Frederic Claude Marie Piry , Luca Scalabrino , David Michael Bull
IPC分类号： G06F11/14
CPC分类号： G06F9/3865 , G06F9/3855 , G06F9/3861 , G06F11/0736 , G06F11/0757 , G06F11/1405 , G06F11/1497
摘要： A data processing apparatus executes instructions in a sequence of pipelined execution stages. An error detection unit twice samples a signal associated with execution of an instruction and generates an error signal if the samples differ. An exception storage unit maintains an age-ordered list of entries corresponding to instructions issued to the execution pipeline and can mark an entry to show if the error signal has been generated in association with that instruction. A timer unit is responsive to generation of the error signal to initiate timing of a predetermined time period. An error recovery unit initiates a soft pipeline flush procedure if an oldest pending entry in the list has said error marker stored in association therewith and initiates a hard pipeline flush procedure if said predetermined time period elapses, said hard flush procedure comprising resetting said pipeline to a predetermined state.
摘要翻译：数据处理装置以流水线执行阶段的顺序执行指令。错误检测单元对与执行指令相关联的信号进行两次采样，并且如果样本不同则产生误差信号。异常存储单元维护与发出到执行流水线的指令相对应的条目的年龄排序列表，并且可以标记条目以显示是否已经与该指令相关联地生成了错误信号。定时器单元响应于产生误差信号以启动预定时间段的定时。如果列表中的最旧的等待条目具有与其相关联地存储的所述错误标记，则错误恢复单元启动软管道冲洗过程，并且如果所述预定时间段过去则启动硬管道冲洗过程，所述硬冲洗程序包括将所述流水线重置为预定状态。

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