专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09519538B2 Error recovery following speculative execution with an instruction processing pipeline 有权
标题翻译：使用指令处理流水线进行推测执行后出错恢复
公开(公告)号：US09519538B2
公开(公告)日：2016-12-13
申请号：US13067510
申请日：2011-06-06
申请人： Emre Özer , Shidhartha Das , David Michael Bull
发明人： Emre Özer , Shidhartha Das , David Michael Bull
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F11/07 , G06F9/38
CPC分类号： G06F11/0793 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3867 , G06F11/0721
摘要： An instruction processing pipeline having error detection and error recovery circuitry associated with one or more of the pipeline stages. If an error is detected within a signal value within that pipeline stage, then it can be repaired. Part of the error recovery may be to flush upstream program instructions from the instruction pipeline. When multi-threading, only those instructions from a thread including an instruction which has been lost as a consequence of the error recovery need be flushed from the instruction pipeline. The instruction pipeline may additionally/alternatively be provided with more than one main storage element associated with each signal value with these main storage elements used in an alternating fashion such that if a signal value has been erroneously captured and needs to be repaired, there is still available a main storage element to properly capture the signal value corresponding to the following program instruction.
摘要翻译：具有与一个或多个流水线级相关联的错误检测和错误恢复电路的指令处理流水线。如果在该流水线阶段内的信号值内检测到错误，则可以进行修复。部分错误恢复可能是从指令流水线中刷新上游程序指令。当多线程时，只有来自包括作为错误恢复的结果已经丢失的指令的线程的那些指令需要从指令流水线中刷新。指令流水线可以另外/替代地设置有与每个信号值相关联的多于一个主存储元件，这些主存储元件以交替方式使用，使得如果信号值被错误地捕获并且需要被修复，则仍然存在可用主存储元件来适当地捕获与以下程序指令对应的信号值。

2. 发明授权

US08621272B2 Integrated circuit with error repair and fault tolerance 有权
公开(公告)号：US08621272B2
公开(公告)日：2013-12-31
申请号：US12735339
申请日：2008-12-29
申请人： Shidhartha Das , David Michael Bull , Emre Ozer
发明人： Shidhartha Das , David Michael Bull , Emre Ozer
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G01R31/31816 , G06F11/1076 , G06F11/1608
摘要： An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways.

3. 发明申请

US20120131313A1 Error recovery following speculative execution with an instruction processing pipeline 有权
标题翻译：使用指令处理流水线进行推测执行后出错恢复
公开(公告)号：US20120131313A1
公开(公告)日：2012-05-24
申请号：US13067510
申请日：2011-06-06
申请人： Emre Ozer , Shidhartha Das , David Michael Bull
发明人： Emre Ozer , Shidhartha Das , David Michael Bull
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F11/0793 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3867 , G06F11/0721
摘要： An instruction processing pipeline 6 is provided. This has error detection and error recovery circuitry 20 associated with one or more of the pipeline stages. If an error is detected within a signal value within that pipeline stage, then it can be repaired. Part of the error recovery may be to flush upstream program instructions from the instruction pipeline 6. When multi-threading, only those instructions from a thread including an instruction which has been lost as a consequence of the error recovery need to be flushed from the instruction pipeline 6. Instruction can also be selected for flushing in dependence upon characteristics such as privileged level, number of dependent instructions etc. The instruction pipeline may additionally/alternatively be provided with more than one main storage element 26, 28 associated with each signal value with these main storage elements 26, 28 being used in an alternating fashion such that if a signal value has been erroneously captured and needs to be repaired, there is still available a main storage element 26, 28 to properly capture the signal value corresponding to the following program instruction. In this way flushes can be avoided.
摘要翻译：提供了指令处理流水线6。这具有与一个或多个流水线级相关联的错误检测和错误恢复电路20。如果在该流水线阶段内的信号值内检测到错误，则可以进行修复。错误恢复的一部分可能是从指令流水线6冲洗上游程序指令。当多线程时，只有来自包括作为错误恢复的结果已经丢失的指令的线程的那些指令需要从指令中刷新流水线6.也可以根据诸如特权级别，依赖指令数量等特征来选择刷新指令。指令流水线可以另外地或替代地设置有多个主存储元件26,28，其与每个信号值相关联，这些主存储元件26,28以交替的方式使用，使得如果信号值被错误地捕获并且需要修复，则仍然可以使用主存储元件26,28来适当地捕获对应于以下的信号值程序指令。这样可以避免冲洗。

4. 发明授权

US08185812B2 Single event upset error detection within an integrated circuit 有权
标题翻译：集成电路内的单事件镦粗错误检测
公开(公告)号：US08185812B2
公开(公告)日：2012-05-22
申请号：US11636716
申请日：2006-12-11
申请人： Shidhartha Das , David Theodore Blaauw , David Michael Bull
发明人： Shidhartha Das , David Theodore Blaauw , David Michael Bull
IPC分类号： G06F11/00
CPC分类号： G06F11/1695 , G06F11/0721 , G06F11/0793 , G06F11/104 , G06F11/1608 , G06F11/167 , G06F11/183
摘要： An integrated circuit 2 includes logic circuitry 10 and sequential storage elements 8. Both the logic circuit 10 and sequential storage elements 8 can be subject to particle strikes giving rise to single event upset errors. These single event upset errors can be detected by detecting a transition in the stored value stored by the sequential storage elements 8 occurring outside of a valid transition period associated with that sequential storage element 8.
摘要翻译：集成电路2包括逻辑电路10和顺序存储元件8.逻辑电路10和顺序存储元件8都可能经受粒子撞击，从而引起单事件失真错误。可以通过检测在与该顺序存储元件8相关联的有效过渡时段之外发生的顺序存储元件8存储的存储值中的转变来检测这些单事件中断错误。

5. 发明授权

US07895469B2 Integrated circuit using speculative execution 有权
标题翻译：集成电路采用推测执行
公开(公告)号：US07895469B2
公开(公告)日：2011-02-22
申请号：US12285796
申请日：2008-10-14
申请人： Emre Özer , David Michael Bull , Shidhartha Das
发明人： Emre Özer , David Michael Bull , Shidhartha Das
IPC分类号： G06F11/00
CPC分类号： G06F9/3842 , G06F9/3861 , G06F9/3869
摘要： An integrated circuit 2 is provided with a plurality of pipeline stages 10. These pipeline stages 10 have speculative processing control circuitry 12 which permits speculative processing in downstream pipeline stages and triggers a first error recovery operation (partial pipeline flushing) if such speculative processing is determined to be based upon an error. The pipeline stage 10 further includes speculative error detecting circuitry 14 which generates a prediction nc regarding whether or not the processing circuitry 18 will produce an error. This prediction is used to trigger a second error recovery operation (partial pipeline stall). This second error recovery operation has a lower performance penalty than the first error recovery operation.
摘要翻译：集成电路2设置有多个流水线级10.这些流水线级10具有推测性处理控制电路12，其允许下游流水线级的推测性处理，并且如果确定了这种推测性处理，则触发第一错误恢复操作（部分流水线冲洗）基于错误。流水线级10还包括推测性错误检测电路14，其产生关于处理电路18是否将产生错误的预测nc。该预测用于触发第二次错误恢复操作（部分流水线停止）。该第二错误恢复操作具有比第一错误恢复操作更低的性能损失。

6. 发明申请

US20100064287A1 Scheduling control within a data processing system 有权
标题翻译：数据处理系统内的调度控制
公开(公告)号：US20100064287A1
公开(公告)日：2010-03-11
申请号：US12458699
申请日：2009-07-21
申请人： David Michael Bull , Emre Ozer , Shidhartha Das
发明人： David Michael Bull , Emre Ozer , Shidhartha Das
IPC分类号： G06F9/30 , G06F11/07 , G06F9/46
CPC分类号： G06F9/3836 , G06F9/3861 , G06F9/3869 , G06F9/3891 , G06F11/004 , G06F11/1405
摘要： A processor 2 is responsive to a stream of program instructions to issue program instructions under control of scheduling circuitry 6 to respective execution units 24 for execution. The execution units 24 can include error detecting circuitry 32 for detecting a change in an output signal which occurs after the output signal has latched and during an error detecting period following the latching of the output signal. The scheduling circuitry 6 is arranged so as to suppress issue of program instructions to an execution unit 24 having such error detecting circuitry 32 on consecutive processing cycles.
摘要翻译：处理器2响应于程序指令流，以在调度电路6的控制下发出程序指令，以执行相应的执行单元24。执行单元24可以包括用于检测在输出信号被锁存之后和在锁存输出信号之后的错误检测周期期间发生的输出信号的变化的错误检测电路32。调度电路6被布置为在连续的处理周期中抑制对具有这种错误检测电路32的执行单元24的程序指令的发出。

7. 发明授权

US08639987B2 Data processing apparatus and method using monitoring circuitry to control operating parameters 有权
标题翻译：数据处理装置和方法，使用监控电路来控制运行参数
公开(公告)号：US08639987B2
公开(公告)日：2014-01-28
申请号：US12929848
申请日：2011-02-18
申请人： Paul Nicholas Whatmough , David Michael Bull , Shidhartha Das
发明人： Paul Nicholas Whatmough , David Michael Bull , Shidhartha Das
IPC分类号： G06F11/00
CPC分类号： G06F1/324 , G06F1/3296 , G06F11/076 , Y02D10/126 , Y02D10/172
摘要： A data processing apparatus and method are provided that use monitoring circuitry to control operating parameters of the data processing apparatus. The data processing apparatus has functional circuitry for performing data processing, the functional circuitry including error correction circuitry configured to detect errors in operation of the functional circuitry and to repair those errors in operation. Tuneable monitoring circuitry monitors a characteristic indicative of changes in signal propagation delay within the functional circuitry and produces a control signal dependent on the monitored characteristic. In a continuous tuning mode operation, the tuneable monitoring circuitry modifies the dependency between the monitored characteristic and the control signal in dependence upon certain characteristics of the errors detected by the error correction circuitry. An operating parameter controller is then arranged, in the continuous mode of operation, to control one or more performance controlling operating parameters of the data processing apparatus in dependence upon the control signal. This enables efficient and robust control of those operating parameters in response to changes in environmental conditions.
摘要翻译：提供一种使用监视电路来控制数据处理装置的操作参数的数据处理装置和方法。所述数据处理装置具有用于执行数据处理的功能电路，所述功能电路包括错误校正电路，其被配置为检测功能电路的操作中的错误并修复这些操作中的错误。可调节监控电路监视指示功能电路内的信号传播延迟的变化的特性，并产生取决于被监测特性的控制信号。在连续调谐模式操作中，可调谐监视电路根据由纠错电路检测到的错误的某些特性来修改监视特性和控制信号之间的相关性。然后，在连续操作模式下，设置操作参数控制器，以根据控制信号控制数据处理装置的一个或多个性能控制操作参数。这可以响应于环境条件的变化而对这些操作参数进行有效和鲁棒的控制。

8. 发明授权

US08639975B2 Error management within a data processing system 有权
标题翻译：数据处理系统中的错误管理
公开(公告)号：US08639975B2
公开(公告)日：2014-01-28
申请号：US12926436
申请日：2010-11-17
申请人： Paul Nicholas Whatmough , David Michael Bull , Shidhartha Das , Daniel Kershaw
发明人： Paul Nicholas Whatmough , David Michael Bull , Shidhartha Das , Daniel Kershaw
IPC分类号： G06F11/00
CPC分类号： G06F11/0763 , H03M13/09
摘要： A data processing system 2 is used to perform processing operations to generate a result value. The processing circuitry which generates the result value has an error resistant portion 32 and an error prone portion 30. The probability of an error in operation of the error prone portion for a given set of operating parameters (clk, V) is greater than the probability of an error for that same set of operating parameters within the error resistant portion. Error detection circuitry 38 detects any errors arising in the error prone portion. Parameter control circuitry 40 responds to detected errors to adjust the set of operating parameters to maintain a non-zero error rate in the errors detected by the error detection circuitry. Errors within the one or more bits generated by the error prone portion are not corrected as the apparatus is tolerant to errors occurring within such bit values of the result value.
摘要翻译：数据处理系统2用于执行处理操作以产生结果值。产生结果值的处理电路具有抗错部分32和易错部分30.对于给定的一组操作参数（clk，V），错误倾向部分的操作错误的概率大于概率在该抗误差部分内的相同的一组操作参数的误差。错误检测电路38检测在易错部分中产生的任何错误。参数控制电路40对检测到的错误进行响应，以调整该组操作参数，以便在错误检测电路检测到的错误中保持非零错误率。由误差容易部分产生的一个或多个位内的错误不会被校正，因为该装置对结果值的这些比特值内发生的错误是容忍的。

9. 发明申请

US20130002298A1 Signal value storage circuitry with transition detector 有权
标题翻译：具有转换检测器的信号值存储电路
公开(公告)号：US20130002298A1
公开(公告)日：2013-01-03
申请号：US13067886
申请日：2011-07-01
申请人： David William Howard , David Michael Bull , Shidhartha Das
发明人： David William Howard , David Michael Bull , Shidhartha Das
IPC分类号： H03K19/00 , H03L7/00
CPC分类号： H03K3/0372 , H03K3/0375 , H03K5/1534
摘要： A D-type flip-flop 2 includes tristate inverter circuitry 4, 6 passing a processing signal through to storage circuitry 8 from where the processing signal passes via a transmission gate 10 to slave storage circuitry 12. A transition detector 16 is coupled to the input node nm of the storage circuitry 8 and serves to generate an error signal if a transition is detected upon that input node during an error detecting period. Other forms of this technique may provide clock gating circuitry.
摘要翻译： D型触发器2包括三态逆变器电路4,6将处理信号传递到存储电路8，处理信号从处理信号经由传输门10通过到从存储电路12.转换检测器16耦合到输入端存储电路8的节点nm，并且用于在错误检测周期期间在该输入节点上检测到转换时产生误差信号。该技术的其他形式可以提供时钟选通电路。

10. 发明授权

US08327118B2 Scheduling control within a data processing system 有权
标题翻译：数据处理系统内的调度控制
公开(公告)号：US08327118B2
公开(公告)日：2012-12-04
申请号：US12458699
申请日：2009-07-21
申请人： David Michael Bull , Emre Ozer , Shidhartha Das
发明人： David Michael Bull , Emre Ozer , Shidhartha Das
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3836 , G06F9/3861 , G06F9/3869 , G06F9/3891 , G06F11/004 , G06F11/1405
摘要： A processor 2 is responsive to a stream of program instructions to issue program instructions under control of scheduling circuitry 6 to respective execution units 24 for execution. The execution units 24 can include error detecting circuitry 32 for detecting a change in an output signal which occurs after the output signal has latched and during an error detecting period following the latching of the output signal. The scheduling circuitry 6 is arranged so as to suppress issue of program instructions to an execution unit 24 having such error detecting circuitry 32 on consecutive processing cycles.
摘要翻译：处理器2响应于程序指令流，以在调度电路6的控制下发出程序指令，以执行相应的执行单元24。执行单元24可以包括用于检测在输出信号被锁存之后和在锁存输出信号之后的错误检测周期期间发生的输出信号的变化的错误检测电路32。调度电路6被布置为在连续的处理周期中抑制对具有这种错误检测电路32的执行单元24的程序指令的发出。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式