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31. 发明申请

US20100046278A1 Implementing Local Evaluation of Domino Read SRAM With Enhanced SRAM Cell Stability and Enhanced Area Usage 失效
标题翻译：实现具有增强的SRAM单元稳定性和增强区域使用的Domino读取SRAM的本地评估
公开(公告)号：US20100046278A1
公开(公告)日：2010-02-25
申请号：US12195151
申请日：2008-08-20
申请人： Chad Allen Adams , Todd Alan Christensen , Peter Thomas Freiburger , Daniel Mark Nelson
发明人： Chad Allen Adams , Todd Alan Christensen , Peter Thomas Freiburger , Daniel Mark Nelson
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C11/413
摘要： A method and circuit for implementing domino static random access memory (SRAM) local evaluation with enhanced SRAM cell stability, and a design structure on which the subject circuit resides are provided. A SRAM local evaluation circuit enabling a read and write operations of an associated SRAM cell group includes true and complement bitlines, true and complement write data propagation inputs, a precharge signal, and a precharge write signal. A respective precharge device is connected between a voltage supply VDD and the true bitline and the complement bitline. A first passgate device is connected between the complement bitline and the true write data propagation input. A second passgate device is connected between the true bitline and the complement write data propagation input. The precharge write signal disables the passgate devices during a read operation. During write operations, the precharge write signal enables the passgate devices.
摘要翻译：一种用于实现具有增强的SRAM单元稳定性的多米诺骨牌静态随机存取存储器（SRAM）局部评估的方法和电路，以及提供主题电路所在的设计结构。实现相关SRAM单元组的读和写操作的SRAM本地评估电路包括真和补补位线，真和补写写数据传播输入，预充电信号和预充电写信号。相应的预充电装置连接在电压源VDD与真位线和补码位线之间。第一传递门装置连接在补码位线和真实写入数据传播输入端之间。第二个通路装置连接在真位线和补码写入数据传播输入之间。在读取操作期间，预充电写信号禁用通路器件。在写入操作期间，预充电写入信号使能通路装置。

32. 发明申请

US20100002495A1 Column Selectable Self-Biasing Virtual Voltages for SRAM Write Assist 有权
标题翻译：用于SRAM写入辅助的列选择自偏置虚拟电压
公开(公告)号：US20100002495A1
公开(公告)日：2010-01-07
申请号：US12167300
申请日：2008-07-03
申请人： Chad Allen Adams , George M. Braceras , Todd A. Christensen , Harold Pilo
发明人： Chad Allen Adams , George M. Braceras , Todd A. Christensen , Harold Pilo
IPC分类号： G11C11/00 , G11C8/00
CPC分类号： G11C11/417 , G11C11/41 , G11C11/419
摘要： A static random access memory decoder circuit includes a first cell supply line coupled to provide a first column of memory cells a first cell supply voltage and a second cell supply line coupled to provide a first column of memory cells a first cell supply voltage. The decoder circuit further includes a write assist circuit having a first threshold transistor coupled to the first cell supply line and a second threshold transistor coupled to the second cell supply line. In response to a write assist signal, the write assist circuit connects one of the first and second cell supply lines selected by control circuitry to an associated one of the first and second threshold transistors, such that a cell supply voltage of the selected one of the first and second cell supply lines is reduced toward the threshold voltage of the threshold transistor.
摘要翻译：静态随机存取存储器解码器电路包括第一单元电源线，其被耦合以提供第一列存储器单元第一单元电源电压和耦合以提供第一列存储器单元的第一单元电源电压的第二单元电源线。解码器电路还包括具有耦合到第一单元电源线的第一阈值晶体管和耦合到第二单元电源线的第二阈值晶体管的写辅助电路。响应于写入辅助信号，写入辅助电路将由控制电路选择的第一和第二单元电源线之一连接到第一和第二阈值晶体管中的相关联的一个，使得所选择的一个的单元电源电压第一和第二电池供应线路朝阈值晶体管的阈值电压减小。

33. 发明申请

US20090323445A1 High Performance Read Bypass Test for SRAM Circuits 失效
标题翻译： SRAM电路的高性能读取旁路测试
公开(公告)号：US20090323445A1
公开(公告)日：2009-12-31
申请号：US12146777
申请日：2008-06-26
申请人： Chad Allen Adams , Derick Gardner Behrends , Daniel Mark Nelson , Jeffrey Milton Scherer
发明人： Chad Allen Adams , Derick Gardner Behrends , Daniel Mark Nelson , Jeffrey Milton Scherer
IPC分类号： G11C29/00
CPC分类号： G11C29/12 , G11C11/41 , G11C29/1201
摘要： A design structure embodied in a machine readable medium used in a design process and an integrated circuit for high performance SRAM (Static Random Access Memory) read bypass for BIST (built-in self-test). The design structure and integrated structure includes a dynamic to static conversion unit for a read output of an SRAM array, and a test bypass unit integrated into the dynamic to static conversion unit, so as to allow the read output of the SRAM array to pass through in a non-test mode without impacting performance, and bypass the read output of the SRAM array and allow a test signal to pass though in a test mode.
摘要翻译：在设计过程中使用的机器可读介质中体现的设计结构和用于BIST（内置自检）的高性能SRAM（静态随机存取存储器）读取旁路的集成电路。该设计结构和集成结构包括用于SRAM阵列的读取输出的动态到静态转换单元和集成到动态到静态转换单元中的测试旁路单元，以便允许SRAM阵列的读取输出通过在不影响性能的非测试模式下，并绕过SRAM阵列的读取输出，并允许测试信号在测试模式下通过。

34. 发明申请

US20090287971A1 METHOD AND APPARATUS FOR TESTING A RANDOM ACCESS MEMORY DEVICE 失效
标题翻译：用于测试随机访问存储器件的方法和装置
公开(公告)号：US20090287971A1
公开(公告)日：2009-11-19
申请号：US12121512
申请日：2008-05-15
申请人： Chad Allen Adams , Elizabeth Lair Gerhard , Sharon Huertas Cesky , Jeffrey Milton Scherer
发明人： Chad Allen Adams , Elizabeth Lair Gerhard , Sharon Huertas Cesky , Jeffrey Milton Scherer
IPC分类号： G11C29/12 , G06F11/27
CPC分类号： G11C29/02 , G11C11/41 , G11C29/022 , G11C29/12 , G11C29/1201
摘要： A method and apparatus for testing a random access memory device is provided. One embodiment involves providing an interface between Logic Built in Self Test (LBIST) and Array Built in Self Test (ABIST) paths for memory testing, including providing a cross-coupled NAND device with an LBIST test path; configuring the cross-coupled NAND device for interfacing ABIST and LBIST paths by modeling a worst case scenario for timing from a domino read static random access memory (SRAM) array; and modifying data in the cross-coupled NAND device using an LBIST controlled data path at essentially the latest point in time when a read may propagate from the array to provide full AC test coverage of down stream logic.
摘要翻译：提供了一种用于测试随机存取存储器件的方法和装置。一个实施例涉及提供用于存储器测试的逻辑内置自测（LBIST）和内置自测（ABIST）阵列之间的接口，包括提供具有LBIST测试路径的交叉耦合NAND器件; 通过对来自多米诺骨牌读静态随机存取存储器（SRAM）阵列的定时的最坏情况进行建模来配置交叉耦合的NAND器件用于接口ABIST和LBIST路径; 以及在基本上最初的时间点上使用LBIST控制数据路径修改交叉耦合NAND器件中的数据，当读取可以从阵列传播以提供下行流逻辑的完整AC测试覆盖时。

35. 发明申请

US20090185435A1 Method and Circuit for Implementing Enhanced SRAM Write and Read Performance Ring Oscillator 失效
标题翻译：实现增强型SRAM写和读性能环形振荡器的方法和电路
公开(公告)号：US20090185435A1
公开(公告)日：2009-07-23
申请号：US12015806
申请日：2008-01-17
申请人： Chad Allen Adams , Todd Alan Christensen , Peter Thomas Freiburger , Travis Reynold Hebig
发明人： Chad Allen Adams , Todd Alan Christensen , Peter Thomas Freiburger , Travis Reynold Hebig
IPC分类号： G11C7/00
CPC分类号： G11C11/413
摘要： A method and circuit for implementing an enhanced static random access memory (SRAM) read and write performance ring oscillator, and a design structure on which the subject circuit resides are provided. A plurality of SRAM base blocks is connected together in a chain. Each of the plurality of SRAM base blocks includes a SRAM cell, such as an eight-transistor (8T) static random access memory (SRAM) cell, and a local evaluation block coupled to the SRAM cell. The SRAM cell includes independent left wordline input and right wordline input. The SRAM cell includes a read wordline connected high, and a true and complement write bitline pair connected low. In the local evaluation circuit, one input of a NAND gate receiving the read bitline input is connected high. A control signal is combined with an inverted feedback signal to start and stop the ring oscillator.
摘要翻译：一种用于实现增强型静态随机存取存储器（SRAM）读写性能环形振荡器的方法和电路，以及设置有被摄体电路所在的设计结构。多个SRAM基块在链中连接在一起。多个SRAM基块中的每一个包括诸如八晶体管（8T）静态随机存取存储器（SRAM）单元的SRAM单元，以及耦合到SRAM单元的局部评估块。 SRAM单元包括独立的左字线输入和右字线输入。 SRAM单元包括一个连接到高电平的读字字线和一个连接低电平的真写补码写位线对。在本地评估电路中，接收读取位线输入的NAND门的一个输入被连接得很高。控制信号与反相反馈信号相结合，以启动和停止环形振荡器。

36. 发明授权

US07505340B1 Method for implementing SRAM cell write performance evaluation 失效
标题翻译：实现SRAM单元写入性能评估的方法
公开(公告)号：US07505340B1
公开(公告)日：2009-03-17
申请号：US11845866
申请日：2007-08-28
申请人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
发明人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/1202
摘要： A method implements static random access memory (SRAM) cell write performance evaluation. A SRAM cell write performance evaluation circuit includes a SRAM core where each wordline is connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.
摘要翻译：一种方法实现了静态随机存取存储器（SRAM）单元写入性能评估。 SRAM单元写入性能评估电路包括SRAM核心，其中每个字线仅连接到一个位列。环形振荡器电路用于产生字线脉冲。状态机控制包括环形振荡器电路和SRAM内核的SRAM单元写入性能评估电路的操作。控制信号被施加到状态机以选择第一写入操作，其中电路同时将所有单元格写入具有宽字线的已知状态，以确保所有单元被写入。然后选择第二次写入操作，同时启动所有字线，将单元写入相反的状态。从这些写入操作中，识别要写入单元的所需字线脉冲宽度。

37. 发明申请

US20090063912A1 Method and Apparatus for Implementing SRAM Cell Write Performance Evaluation 失效
标题翻译：实现SRAM单元写入性能评估的方法和装置
公开(公告)号：US20090063912A1
公开(公告)日：2009-03-05
申请号：US11873173
申请日：2007-10-16
申请人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
发明人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
IPC分类号： G11C29/08
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/1202
摘要： A method and apparatus for implementing static random access memory (SRAM) cell write performance evaluation, and a design structure on which the subject circuit resides are provided. ASRAM core includes each wordline connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.
摘要翻译：一种用于实现静态随机存取存储器（SRAM）单元写入性能评估的方法和装置，以及设置有主题电路所在的设计结构。 ASRAM内核包括只连接到一个位列的每个字线。环形振荡器电路用于产生字线脉冲。状态机控制包括环形振荡器电路和SRAM内核的SRAM单元写入性能评估电路的操作。将控制信号施加到状态机以选择第一写入操作，其中电路同时将所有单元格写入具有宽字线的已知状态，以确保所有单元都被写入。然后选择第二次写入操作，同时启动所有字线，将单元写入相反的状态。从这些写入操作中，识别要写入单元的所需字线脉冲宽度。

38. 发明申请

US20090059697A1 METHOD AND APPARATUS FOR IMPLEMENTING SRAM CELL WRITE PERFORMANCE EVALUATION 失效
标题翻译：用于实现SRAM单元写性能评估的方法和装置
公开(公告)号：US20090059697A1
公开(公告)日：2009-03-05
申请号：US11845866
申请日：2007-08-28
申请人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
发明人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/1202
摘要： A SRAM cell write performance evaluation circuit includes a SRAM core where each wordline is connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.
摘要翻译： SRAM单元写入性能评估电路包括SRAM核心，其中每个字线仅连接到一个位列。环形振荡器电路用于产生字线脉冲。状态机控制包括环形振荡器电路和SRAM内核的SRAM单元写入性能评估电路的操作。控制信号被施加到状态机以选择第一写入操作，其中电路同时将所有单元格写入具有宽字线的已知状态，以确保所有单元被写入。然后选择第二次写入操作，同时启动所有字线，将单元写入相反的状态。从这些写入操作中，识别要写入单元的所需字线脉冲宽度。

39. 发明申请

US20090027946A1 METHOD AND APPARATUS FOR IMPLEMENTING ENHANCED SRAM READ PERFORMANCE SORT RING OSCILLATOR (PSRO) 有权
标题翻译：实现增强SRAM读取性能分析振荡器（PSRO）的方法和设备
公开(公告)号：US20090027946A1
公开(公告)日：2009-01-29
申请号：US11782808
申请日：2007-07-25
申请人： Chad Allen Adams , Todd Alan Christensen , Travis Reynold Hebig , Kirk David Peterson
发明人： Chad Allen Adams , Todd Alan Christensen , Travis Reynold Hebig , Kirk David Peterson
IPC分类号： G11C11/00
CPC分类号： G11C11/413 , G11C11/41 , G11C11/419 , G11C2029/0403
摘要： A method and apparatus including a static random access memory (SRAM) cell implement an enhanced SRAM read performance sort ring oscillator (PSRO). A pair of parallel reverse polarity connected inverters defines a static latch or cross-coupled memory cell. The SRAM cell includes independent left and right wordlines providing a respective gate input to a pair of access transistors used to access to the memory cell. The SRAM cell includes a voltage supply connection to one side of the static latch. For example, a complement side of the static latch is connected to the voltage supply. A plurality of the SRAM cells is assembled together to form a SRAM base block. A plurality of the SRAM base blocks is connected together to form the SRAM read PSRO.
摘要翻译：包括静态随机存取存储器（SRAM）单元的方法和装置实现增强型SRAM读取性能排序环形振荡器（PSRO）。一对并联反极性连接的反相器定义了静态锁存器或交叉耦合存储器单元。 SRAM单元包括独立的左和右字线，为用于访问存储单元的一对存取晶体管提供相应的栅极输入。 SRAM单元包括到静态锁存器的一侧的电压供应连接。例如，静态锁存器的补码侧连接到电源。多个SRAM单元组装在一起以形成SRAM基块。多个SRAM基块被连接在一起以形成SRAM读取PSRO。

40. 发明授权

US07283411B2 Flood mode implementation for continuous bitline local evaluation circuit 失效
标题翻译：连续位线局部评估电路的洪水模式实现
公开(公告)号：US07283411B2
公开(公告)日：2007-10-16
申请号：US11552791
申请日：2006-10-25
申请人： Chad Allen Adams , Derick Gardner Behrends , Ryan Charles Kivimagi
发明人： Chad Allen Adams , Derick Gardner Behrends , Ryan Charles Kivimagi
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/41
摘要： A method, an apparatus, and a computer program product are provided for flood mode implementation of SRAM cells that employ a continuous bitline local evaluation circuit. Flood mode testing is used to weed out marginal SRAM cells by stressing the SRAM cells. Flood mode is induced by beginning with a normal write operation. After new data values have been forced into the SRAM cells, then the write signal is chopped off. A delay block keeps the wordline signal at the high supply, and the SRAM cells go into flood mode. At this juncture marginal cells can be easily detected and later mapped to redundant cells.
摘要翻译：提供了一种方法，装置和计算机程序产品，用于采用连续位线局部评估电路的SRAM单元的泛洪模式实现。洪水模式测试用于通过强调SRAM单元来清除边缘SRAM单元。通过开始正常的写操作来引发洪泛模式。在新的数据值被强制进入SRAM单元之后，写入信号被切断。延迟块将字线信号保持在高电源，SRAM单元进入泛洪模式。在这个关键点，边缘细胞可以很容易地被检测，并且稍后映射到冗余细胞。

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