专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明申请

US20080278190A1 Testing fuse configurations in semiconductor devices 有权
标题翻译：测试半导体器件中的保险丝配置
公开(公告)号：US20080278190A1
公开(公告)日：2008-11-13
申请号：US12008318
申请日：2008-01-10
申请人： Adrian E. Ong , Paul Fuller , Nick van Heel , Mark Thomann
发明人： Adrian E. Ong , Paul Fuller , Nick van Heel , Mark Thomann
IPC分类号： H01L23/62 , G01R31/26
CPC分类号： G01R31/31722 , G01R31/2851 , G01R31/31723 , H01L2224/05554 , H01L2224/48137 , H01L2224/48145 , H01L2924/00012
摘要： Methods, systems, and apparatus for testing semiconductor devices. A semiconductor device includes one or more external terminals configured to receive fuse configuration data from an external source. The semiconductor device also includes a soft-blow circuit to generate a soft-blow signal based on the fuse configuration data, and a fuse circuit that includes a fuse and has first and second operational states corresponding to the fuse being intact and blown, respectively. The fuse circuit is configured to receive the soft-blow signal and to select its operational state to be the first or second operational state based on the received soft-blow signal.
摘要翻译：用于测试半导体器件的方法，系统和设备。半导体器件包括被配置为从外部源接收熔丝配置数据的一个或多个外部端子。半导体器件还包括基于熔丝配置数据产生软吹信号的软吹电路，以及包括保险丝的熔丝电路，并且具有对应于保险丝的第一和第二操作状态是完整的和被熔断的。熔丝电路被配置为基于所接收的软吹扫信号接收软吹信号并将其操作状态选择为第一或第二操作状态。

32. 发明授权

US07404117B2 Component testing and recovery 有权
标题翻译：组件测试和恢复
公开(公告)号：US07404117B2
公开(公告)日：2008-07-22
申请号：US11258484
申请日：2005-10-24
申请人： Adrian E. Ong , Richard G. Egan
发明人： Adrian E. Ong , Richard G. Egan
IPC分类号： G11C29/00 , G01R31/02 , G01R31/26
CPC分类号： G11C29/846 , G11C29/56 , G11C29/76 , G11C29/81 , G11C2229/743 , G11C2229/763
摘要： Disclosed are systems and methods of producing electronic devices. These electronic devices include excess circuits to be used as replacements for circuits that are found to be defective within the electronic device. The excess circuits are included in a different device component than the circuits that are found to be defective. The replacement process occurs after the excess circuits and defective circuits are included in an electronic device including the different device components. Identification of the defective circuits may occur before or after the defective circuits are incorporated in the electronic device. In some embodiments, systems and methods of the invention result in improved manufacturing yields as compared with the prior art.
摘要翻译：公开了制造电子设备的系统和方法。这些电子设备包括用作电子设备中发现有缺陷的电路的替代物的多余电路。多余电路被包含在与发现有缺陷的电路不同的器件部件中。替换处理发生在多余电路和故障电路包括在包括不同器件组件的电子设备中之后。有缺陷的电路的识别可能发生在电路装置内的故障电路之前或之后。在一些实施例中，与现有技术相比，本发明的系统和方法导致改进的制造产量。

33. 发明授权

US06983404B2 Method and apparatus for checking the resistance of programmable elements 失效
标题翻译：用于检查可编程元件电阻的方法和装置
公开(公告)号：US06983404B2
公开(公告)日：2006-01-03
申请号：US09777036
申请日：2001-02-05
申请人： Douglas J. Cutter , Adrian E. Ong , Fan Ho , Kurt D. Beigel , Brett M. Debenham , Dien Luong , Kim Pierce , Patrick J. Mullarkey
发明人： Douglas J. Cutter , Adrian E. Ong , Fan Ho , Kurt D. Beigel , Brett M. Debenham , Dien Luong , Kim Pierce , Patrick J. Mullarkey
IPC分类号： G11C29/00
CPC分类号： G11C17/18
摘要： Method and apparatus are disclosed for checking the resistance of antifuse elements in an integrated circuit. A voltage based on the resistance of an antifuse element is compared to a voltage based on a known resistance, and an output signal is generated whose binary value indicates whether the resistance of the antifuse element is higher or lower than the known value of resistance. The method and apparatus are useful in verifying the programming of antifuse elements.
摘要翻译：公开了用于检查集成电路中的反熔丝元件的电阻的方法和装置。将基于反熔丝元件的电阻的电压与基于已知电阻的电压进行比较，并且生成其二进制值表示反熔丝元件的电阻是否高于或低于已知电阻值的输出信号。该方法和装置在验证反熔丝元件的编程方面是有用的。

34. 发明授权

US6154410A Method and apparatus for reducing antifuse programming time 失效
标题翻译：减少反熔丝编程时间的方法和装置
公开(公告)号：US6154410A
公开(公告)日：2000-11-28
申请号：US795531
申请日：1997-02-05
申请人： Douglas J. Cutter , Kurt D. Beigel , Adrian E. Ong , Fan Ho , Patrick J. Mullarkey , Dien Luong , Brett Debenham , Kim Pierce
发明人： Douglas J. Cutter , Kurt D. Beigel , Adrian E. Ong , Fan Ho , Patrick J. Mullarkey , Dien Luong , Brett Debenham , Kim Pierce
IPC分类号： G11C17/18 , G11C7/00
CPC分类号： G11C17/18
摘要： Method and apparatus are disclosed for reducing antifuse programming time by connecting the programming voltage to the electrode of the antifuse element that has roughened polysilicon.
摘要翻译：公开了通过将编程电压连接到具有粗糙多晶硅的反熔丝元件的电极来减少反熔丝编程时间的方法和装置。

35. 发明授权

US5919269A Supervoltage detection circuit having a multi-level reference voltage 失效
标题翻译：具有多电平参考电压的超级电压检测电路
公开(公告)号：US5919269A
公开(公告)日：1999-07-06
申请号：US67254
申请日：1998-04-27
申请人： Adrian E. Ong
发明人： Adrian E. Ong
IPC分类号： G11C29/46 , G01R31/28
CPC分类号： G11C29/46
摘要： An integrated memory circuit is described which can be tested using both a burn-in test and an application specific test. The application specific test is initiated by providing a supervoltage on one of the integrated memory circuit external input pins. A reference voltage circuit is described for producing a variable or multi-level reference voltage used by a supervoltage detection circuit. If a burn-in test is being performed, the reference voltage is adjusted from a level used when the memory is not operating in a burn-in test mode. A multi-level reference voltage is provided to the supervoltage detection circuit, thereby, adjusting the supervoltage level needed to initiate an application specific test.
摘要翻译：描述了可以使用老化测试和应用特定测试来测试的集成存储器电路。通过在集成存储器电路外部输入引脚之一上提供超级电压来启动应用特定测试。描述了用于产生由超压检测电路使用的可变或多电平参考电压的参考电压电路。如果正在执行老化测试，则当存储器未在老化测试模式下运行时使用的电平调整参考电压。向超级电压检测电路提供多电平参考电压，从而调整启动应用特定测试所需的超级电平。

36. 发明授权

US5901105A Dynamic random access memory having decoding circuitry for partial memory blocks 失效
标题翻译：具有用于部分存储器块的解码电路的动态随机存取存储器
公开(公告)号：US5901105A
公开(公告)日：1999-05-04
申请号：US869035
申请日：1997-06-05
申请人： Adrian E Ong , Paul S. Zagar , Troy Manning , Brent Keeth , Ken Waller
发明人： Adrian E Ong , Paul S. Zagar , Troy Manning , Brent Keeth , Ken Waller
IPC分类号： G11C5/02 , G11C7/10 , G11C11/4096 , G11C29/00 , G11C29/36 , G11C8/00
CPC分类号： G11C29/785 , G11C11/4096 , G11C29/80 , G11C29/88 , G11C5/025 , G11C7/10 , G11C29/36
摘要： A semiconductor dynamic random-access memory (DRAM) device embodying numerous features that collectively and/or individually prove beneficial and advantageous with regard to such considerations as density, power consumption, speed, and redundancy is disclosed. The device is a 64 Mbit DRAM comprising eight substantially identical 8 Mbit partial array blocks (PABs), each pair of PABs comprising a 16 Mbit quadrant of the device. Between the top two quadrants and between the bottom two quadrants are column blocks containing I/O read/write circuitry, column redundancy fuses, and column decode circuitry. Column select lines originate from the column blocks and extend right and left across the width of each quadrant. Each PAB comprises eight substantially identical 1 Mbit sub-array blocks (SABs). Associated with each SAB are a plurality of local row decoder circuits functioning to receive partially decoded row addresses from a column predecoder circuit and generating local row addresses supplied to the SAB with which they are associated. Various pre- and/or post-packaging options are provided for enabling a large degree of versatility, redundancy, and economy of design. Programmable options of the disclosed device are programmable by means of both laser fuses and electrical fuses. In the RAS chain, circuitry is provided for simulating the RC time constant behavior of word lines and digit lines during memory accesses, such that memory access cycle time can be optimized. Test data compression circuitry optimizes the process of testing each cell in the array. On-chip topology circuitry simplifies the testing of the device.
摘要翻译：公开了一种体现许多特征的半导体动态随机存取存储器（DRAM）装置，它们集中和/或单独地证明了在诸如密度，功耗，速度和冗余度之类的考虑方面是有利和有利的。该器件是包括八个基本上相同的8兆位部分阵列块（PAB）的64Mbit DRAM，每对PAB包括该器件的16Mb象限。顶部两个象限之间和底部两个象限之间是包含I / O读/写电路，列冗余保险丝和列解码电路的列块。列选择线来自列块，并在每个象限的宽度上左右延伸。每个PAB包括八个基本上相同的1兆位子阵列块（SAB）。与每个SAB相关联的是多个本地行解码器电路，用于从列预解码器电路接收部分解码的行地址，并产生提供给与它们相关联的SAB的本地行地址。提供了各种前置和/或后封装选项，以实现大量多功能性，冗余性和设计经济性。所公开的设备的可编程选项可通过激光熔丝和电熔丝两者来编程。在RAS链中，提供电路用于在存储器访问期间模拟字线和数字线的RC时间常数行为，使得可以优化存储器访问周期时间。测试数据压缩电路优化了测试阵列中每个单元的过程。片上拓扑电路简化了器件的测试。

37. 发明授权

US5761145A Efficient method for obtaining usable parts from a partially good memory integrated circuit 失效
公开(公告)号：US5761145A
公开(公告)日：1998-06-02
申请号：US685783
申请日：1996-07-24
申请人： Paul S. Zagar , Brent Keeth , Adrian E. Ong
发明人： Paul S. Zagar , Brent Keeth , Adrian E. Ong
IPC分类号： G06F12/16 , G01R31/30 , G06F11/22 , G11C29/00 , G11C29/02 , G11C29/04 , G11C29/44 , G11C29/50 , G11C13/00
CPC分类号： G11C29/70 , G01R31/3004 , G06F11/22 , G11C29/02 , G11C29/44 , G11C29/50 , G11C29/83 , G11C29/832 , G11C29/88 , G11C11/401 , G11C2029/5006
摘要： An integrated circuit memory device has multiple subarray partitions which can be independently isolated from the remaining circuitry on the integrated circuit. Subarrays of the integrated circuit can be independently tested. Should a subarray of the integrated circuit be found inoperable it is electrically isolated from the remaining circuitry on the integrated circuit so that it cannot interfere with the normal operation of the remaining circuitry. Defects such as power to ground shorts in a subarray which would have previously been catastrophic can be electrically isolated allowing the remaining functional subarrays to be utilized. Integrated circuit repair by isolation of inoperative elements eliminates the current draw and other performance degradations that have previously been associated with integrated circuits with defects repaired through the incorporation of redundant elements alone.

38. 发明授权

US08908428B2 Voltage assisted STT-MRAM writing scheme 有权
标题翻译：电压辅助STT-MRAM写入方案
公开(公告)号：US08908428B2
公开(公告)日：2014-12-09
申请号：US13753350
申请日：2013-01-29
申请人： Adrian E. Ong , Vladimir Nikitin , Mohamad Towfik Krounbi
发明人： Adrian E. Ong , Vladimir Nikitin , Mohamad Towfik Krounbi
IPC分类号： G11C11/14 , G11C11/16 , H01L43/02 , H01L43/12
CPC分类号： G11C11/1673 , G11C11/161 , G11C11/1655 , G11C11/1659 , G11C11/1675 , H01L27/228 , H01L43/02 , H01L43/08 , H01L43/12
摘要： An embodiment includes a three terminal magnetic element for a semiconductor memory device. The magnetic element includes a reference layer; a free layer; a barrier layer disposed between the reference layer and the free layer; a first electrode; an insulating layer disposed between the electrode and the free layer; and a second electrode coupled to sidewalls of the free layer.
摘要翻译：实施例包括用于半导体存储器件的三端子磁性元件。磁性元件包括参考层; 自由层设置在参考层和自由层之间的阻挡层; 第一电极; 设置在电极和自由层之间的绝缘层; 以及耦合到所述自由层的侧壁的第二电极。

39. 发明授权

US08717052B2 Testing fuse configurations in semiconductor devices 失效
标题翻译：测试半导体器件中的保险丝配置
公开(公告)号：US08717052B2
公开(公告)日：2014-05-06
申请号：US13206434
申请日：2011-08-09
申请人： Adrian E. Ong , Paul Fuller , Nick van Heel , Mark Thomann
发明人： Adrian E. Ong , Paul Fuller , Nick van Heel , Mark Thomann
IPC分类号： G01R31/3187
CPC分类号： G01R31/31722 , G01R31/2851 , G01R31/31723 , H01L2224/05554 , H01L2224/48137 , H01L2224/48145 , H01L2924/00012
摘要： Methods, systems, and apparatus for testing semiconductor devices. A semiconductor device includes one or more external terminals configured to receive fuse configuration data from an external source. The semiconductor device also includes a soft-blow circuit to generate a soft-blow signal based on the fuse configuration data, and a fuse circuit that includes a fuse and has first and second operational states corresponding to the fuse being intact and blown, respectively. The fuse circuit is configured to receive the soft-blow signal and to select its operational state to be the first or second operational state based on the received soft-blow signal.
摘要翻译：用于测试半导体器件的方法，系统和设备。半导体器件包括被配置为从外部源接收熔丝配置数据的一个或多个外部端子。半导体器件还包括基于熔丝配置数据产生软吹信号的软吹电路，以及包括保险丝的熔丝电路，并且具有对应于保险丝的第一和第二操作状态是完整的和被熔断的。熔丝电路被配置为基于所接收的软吹扫信号接收软吹信号并将其操作状态选择为第一或第二操作状态。

40. 发明授权

US08446788B2 Programmable memory repair scheme 有权
公开(公告)号：US08446788B2
公开(公告)日：2013-05-21
申请号：US12922425
申请日：2009-04-09
申请人： Adrian E. Ong , Fan Ho
发明人： Adrian E. Ong , Fan Ho
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/76 , G11C11/401 , G11C11/4085 , G11C29/027 , G11C29/04 , G11C29/12 , G11C29/4401 , G11C29/48 , G11C29/78 , G11C29/789 , G11C29/802 , G11C2229/743
摘要： The present disclosure provides semiconductor devices and methods, systems, and apparatus for testing and operating the same. A semiconductor memory device includes data storage elements and a repair circuit. The data storage elements include primary data storage elements and one or more redundant data storage elements, the primary data storage elements having respective addresses for memory access operations. The repair circuit is programmable by another semiconductor device separate from the memory device to recognize a malfunctioning address of the primary data storage elements and the programmed repair circuit is configured to reroute memory access from a primary data storage element having the recognized malfunctioning address to a corresponding redundant data storage element.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式