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1. 发明授权

US09116210B2 Integrated circuit testing module including signal shaping interface 有权
标题翻译：集成电路测试模块包括信号整形接口
公开(公告)号：US09116210B2
公开(公告)日：2015-08-25
申请号：US13609019
申请日：2012-09-10
申请人： Adrian E. Ong
发明人： Adrian E. Ong
IPC分类号： G06F11/00 , G01R31/319 , G06F11/27 , G06F11/263 , G06F11/273 , G11C29/14 , G11C29/56
CPC分类号： G01R31/31928 , G06F11/263 , G06F11/27 , G06F11/2733 , G11C29/14 , G11C29/56 , G11C29/56012 , G11C2029/5602
摘要： Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher slew rate than the slew rate at which signals are received from the automated testing equipment.
摘要翻译：公开了测试集成电路的系统和方法。这些系统包括配置成在自动测试设备和要测试的集成电路之间运行的测试模块。测试接口被配置为以比从自动测试设备接收信号的转换速率更高的转换速率测试集成电路。

2. 发明授权

US09099181B2 Non-volatile static ram cell circuit and timing method 有权
标题翻译：非易失性静态压电池电路及定时方法
公开(公告)号：US09099181B2
公开(公告)日：2015-08-04
申请号：US13011726
申请日：2011-01-21
申请人： Adrian E. Ong
发明人： Adrian E. Ong
IPC分类号： G11C14/00
CPC分类号： G11C14/0081 , G11C14/0063 , G11C14/0072 , G11C14/009 , Y10T29/49117
摘要： A non-volatile static random access memory cell and includes a bistable regenerative circuit coupled to first and second transistors and to first and second non-volatile memory cells. Methods of use include directly transferring a complementary data bit between the non-volatile memory cell and the bistable regenerative circuit. Alternatively, complementary data from the bistable regenerative circuit may be regenerated by a sense amplifier and a second bistable regenerative circuit before being transferred to non-volatile memory cells in a column of memory cells. The bistable regenerative circuit may be reset to ground potential. Applications using the non-volatile SRAM cell with direct read out from the bistable regenerative circuit include a non-volatile flip-flop or non-volatile multiplexer.
摘要翻译：一种非易失性静态随机存取存储器单元，包括耦合到第一和第二晶体管以及第一和第二非易失性存储单元的双稳态再生电路。使用方法包括在非易失性存储单元和双稳态再生电路之间直接传送互补数据位。或者，来自双稳态再生电路的补充数据可以在被传送到存储器单元列中的非易失性存储器单元之前由读出放大器和第二双稳态再生电路再生。双稳态再生电路可能被复位到地电位。使用从双稳态再生电路直接读出的非易失性SRAM单元的应用包括非易失性触发器或非易失性复用器。

3. 发明申请

US20140157065A1 METHOD AND SYSTEM FOR PROVIDING A SMART MEMORY ARCHITECTURE 有权
标题翻译：提供智能存储器架构的方法和系统
公开(公告)号：US20140157065A1
公开(公告)日：2014-06-05
申请号：US13936134
申请日：2013-07-05
申请人： Adrian E. ONG
发明人： Adrian E. ONG
IPC分类号： G11C29/12
CPC分类号： G11C29/12 , G06F11/00 , G06F15/7821 , G06F21/00 , G11C11/16 , G11C13/0002 , G11C29/42 , G11C29/44
摘要： A smart memory system preferably includes a memory including one or more memory chips, and a processor including one or more memory processor chips. The system may include a smart memory controller capable of performing a bit error rate built-in self test. The smart memory control may include bit error rate controller logic configured to control the bit error rate built-in self test. A write error rate test pattern generator may generate a write error test pattern for the bit error rate built-in self test. A read error rate test pattern generator may generate a read error test pattern for the built-in self test. The smart memory controller may internally generate an error rate timing pattern, perform built-in self test, measure the resulting error rate, automatically adjust one or more test parameters based on the measured error rate, and repeat the built-in self test using the adjusted parameters.
摘要翻译：智能存储器系统优选地包括包括一个或多个存储器芯片的存储器和包括一个或多个存储器处理器芯片的处理器。该系统可以包括能够执行误码率内置自检的智能存储器控制器。智能存储器控制可以包括误码率控制器逻辑，其被配置为控制内置自检中的误码率。写错误率测试模式发生器可能会产生内部自检误码率的写错误测试模式。读错误率测试模式发生器可以产生用于内置自检的读错误测试模式。智能存储器控制器可以在内部产生错误率定时模式，执行内置自检，测量产生的错误率，根据测量的错误率自动调整一个或多个测试参数，并使用调整参数。

4. 发明申请

US20130322154A1 SENSE AMPLIFIER CIRCUITRY FOR RESISTIVE TYPE MEMORY 有权
标题翻译：用于电阻型存储器的感测放大器电路
公开(公告)号：US20130322154A1
公开(公告)日：2013-12-05
申请号：US13488432
申请日：2012-06-04
申请人： YongSik Youn , Adrian E. Ong , SOOHO CHA , Chan-kyung Kim
发明人： YongSik Youn , Adrian E. Ong , SOOHO CHA , Chan-kyung Kim
IPC分类号： G11C7/06 , G11C7/12 , G11C11/00
CPC分类号： G11C7/062 , G11C7/12 , G11C11/1653 , G11C11/1673 , G11C11/1675 , G11C13/0002 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C2013/0042 , G11C2207/063
摘要： Example embodiments include a resistive type memory current sense amplifier circuit including differential output terminals, first and second input terminals, pre-charge transistors, and current modulating transistors coupled directly to the pre-charge transistors. The pre-charge configuration provides high peak currents to charge the bit line and reference line during a “ready” or “pre-charge” stage of operation of the current sense amplifier circuit. The current modulating transistors are configured to operate in a saturation region mode during at least a “set” or “amplification” stage. The current modulating transistors continuously average a bit line current and a reference line current during the “set” or “amplification” stage, thereby improving noise immunity of the circuit. During a “go” or “latch” stage of operation, a logical value “0” or “1” is latched at the differential output terminals based on positive feedback of a latch circuit.
摘要翻译：示例实施例包括包括差分输出端子，直接耦合到预充电晶体管的第一和第二输入端子，预充电晶体管和电流调制晶体管的电阻型存储电流读出放大器电路。预充电配置提供高峰值电流，以在电流检测放大器电路的“准备”或“预充电”阶段期间为位线和参考线充电。电流调制晶体管被配置为在至少“设置”或“放大”阶段期间以饱和区域模式工作。电流调制晶体管在“设置”或“放大”级期间连续平均位线电流和参考线电流，从而提高电路的抗噪声能力。在“去”或“锁存”操作阶段期间，基于锁存电路的正反馈，在差分输出端子处锁存逻辑值“0”或“1”。

5. 发明申请

US20130212207A1 ARCHITECTURE AND METHOD FOR REMOTE MEMORY SYSTEM DIAGNOSTIC AND OPTIMIZATION 审中-公开
标题翻译：用于远程记忆系统诊断和优化的架构和方法
公开(公告)号：US20130212207A1
公开(公告)日：2013-08-15
申请号：US13719213
申请日：2012-12-18
申请人： Adrian E. Ong
发明人： Adrian E. Ong
IPC分类号： G06F15/167
CPC分类号： G06F15/167 , G06F3/0601 , G06F11/0751 , G06F11/0793 , G06F11/1008 , G06F11/1076 , G06F12/00 , G06F21/00 , G11C11/16 , G11C11/1677 , G11C11/1695 , G11C13/0002
摘要： A smart memory system preferably includes a memory including one or more memory chips and a smart memory controller. The smart memory controller includes a transmitter communicatively coupled to the cloud. The transmitter securely transmits a product identification (ID) associated with the memory to the cloud. A cloud-based data center receives and stores the product ID and related information associated with the memory. A smart memory tester receives a product specific test program from the cloud-based data center. The smart memory tester may remotely test the memory via the cloud in accordance with the product specific test program. The information stored in the cloud-based data center can be accessed anywhere in the world by authorized personnel. Repair solutions can be remotely determined based on the test results and the diagnostic information. The repair solutions are transmitted to the smart memory controller, which repairs the memory.
摘要翻译：智能存储器系统优选地包括包括一个或多个存储器芯片和智能存储器控制器的存储器。智能存储器控制器包括通信地耦合到云的发射器。发射机将与存储器相关联的产品标识（ID）安全地传输到云。基于云的数据中心接收并存储与存储器相关联的产品ID和相关信息。智能内存测试仪从云端数据中心接收产品特定的测试程序。智能内存测试器可以根据产品特定的测试程序通过云端远程测试内存。存储在云数据中心中的信息可以由授权人员在世界上任何地方访问。维修解决方案可以根据测试结果和诊断信息进行远程确定。修复解决方案被传输到智能存储器控制器，从而修复存储器。

6. 发明授权

US08456926B2 Memory write error correction circuit 有权
标题翻译：内存写错误纠正电路
公开(公告)号：US08456926B2
公开(公告)日：2013-06-04
申请号：US13013616
申请日：2011-01-25
申请人： Adrian E. Ong , Vladimir Nitikin
发明人： Adrian E. Ong , Vladimir Nitikin
IPC分类号： G11C7/00 , G11C8/00 , G11C11/00
CPC分类号： G11C7/1006 , G11C7/22 , G11C11/1659 , G11C11/1675 , G11C11/1677 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0064 , G11C2211/5647
摘要： Memory circuit includes; an array, row decoder, column decoder, addressing circuit to receive an address of the data bit, control logic receiving commands and transmitting control signals to memory system blocks, and sensing and write driver circuits coupled to a selected column. A hidden read compare circuit couples between the sensing circuit and write driver, which couples an error flag to the control logic circuit responsive to a comparison between a data bit in the input latch and a data-out read from the memory array. A write error address tag memory is responsive to the error flag and is coupled to the addressing circuit via a bidirectional bus. A data input output circuit having first and second bidirectional buses to transmit and receive said data bit is provided. Write error address tag memory stores the address if the error flag is set and provides the address during a re-write operation.
摘要翻译：存储电路包括阵列，行解码器，列解码器，用于接收数据位的地址的寻址电路，控制逻辑接收命令并向存储器系统块发送控制信号，以及感测和写入耦合到所选列的驱动器电路。隐藏的读取比较电路耦合在感测电路和写入驱动器之间，该驱动器响应于输入锁存器中的数据位与从存储器阵列读取的数据输出之间的比较将错误标志耦合到控制逻辑电路。写错误地址标签存储器响应于错误标志，并且经由双向总线耦合到寻址电路。提供了具有用于发送和接收所述数据位的第一和第二双向总线的数据输入输出电路。写错误地址标签存储器如果设置了错误标志，则存储地址，并在重写操作期间提供地址。

7. 发明授权

US08286046B2 Integrated circuit testing module including signal shaping interface 有权
标题翻译：集成电路测试模块包括信号整形接口
公开(公告)号：US08286046B2
公开(公告)日：2012-10-09
申请号：US13162112
申请日：2011-06-16
申请人： Adrian E. Ong
发明人： Adrian E. Ong
IPC分类号： G06F11/00
CPC分类号： G01R31/31928 , G06F11/263 , G06F11/27 , G06F11/2733 , G11C29/14 , G11C29/56 , G11C29/56012 , G11C2029/5602
摘要： Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher slew rate than the slew rate at which signals are received from the automated testing equipment. In order to do so, the testing interface includes components configured for generating addresses, commands, and test data to be conveyed to the integrated circuit. A variety of test data patterns can be produced and the test data can be address dependent. The systems are optionally configured to include a test plan memory component configured to store one or more test plans. A test plan may include a sequence of test patterns and/or conditional branches whereby the tests to be performed next are dependent on the results of the preceding tests. The test plan memory is, optionally, be detachable from the test module.
摘要翻译：公开了测试集成电路的系统和方法。这些系统包括配置成在自动测试设备和要测试的集成电路之间运行的测试模块。测试接口被配置为以比从自动测试设备接收信号的转换速率更高的转换速率测试集成电路。为了这样做，测试接口包括被配置用于生成要传送到集成电路的地址，命令和测试数据的组件。可以生成各种测试数据模式，并且测试数据可以取决于地址。系统可选地被配置为包括被配置为存储一个或多个测试计划的测试计划存储器组件。测试计划可以包括一系列测试模式和/或条件分支，由此下一步执行的测试取决于前面测试的结果。测试计划存储器可选地可从测试模块拆卸。

8. 发明申请

US20120206167A1 Multi-Supply Symmetric Driver Circuit and Timing Method 有权
标题翻译：多电源对称驱动电路和时序方法
公开(公告)号：US20120206167A1
公开(公告)日：2012-08-16
申请号：US13153031
申请日：2011-06-03
申请人： Adrian E. Ong , Dmytro Apalkov
发明人： Adrian E. Ong , Dmytro Apalkov
IPC分类号： H03K3/00
CPC分类号： G11C11/1675 , G11C8/08 , G11C8/14 , G11C11/1653 , G11C11/1659 , G11C11/1693 , G11C11/1697
摘要： Circuit includes, in part, random access memory cells, column decoders, row decoders, and write driver circuit. Driver circuit is responsive to data and control signals. Writing data includes multiple write phases, each phase driving predetermined current through selected cell by driver setting predetermined voltages to first and second lines. Voltages are in sets such that sequential voltages of each set correspond to respective phase. During writing of first data to selected cell, driver circuit causes first signal line to be at second voltage set and second signal line to be at first voltage set. Second voltage set is greater than first voltage set. During writing of second data to selected cell, driver cause first signal line to be at third voltage set and second signal line to be at fourth voltage set. Third voltage set is smaller than the fourth voltage set.
摘要翻译：电路部分包括随机存取存储单元，列解码器，行解码器和写驱动器电路。驱动电路响应于数据和控制信号。写入数据包括多个写入相位，每个相位通过驱动器将预定电流驱动到所选择的单元，将预定电压设置到第一和第二行。电压为一组，使得每组的顺序电压对应于相应的相位。在向所选单元写入第一数据期间，驱动电路使第一信号线处于第二电压设置，第二信号线处于第一电压设置。第二电压设置大于第一电压设置。在将第二数据写入所选择的单元时，驱动器使第一信号线处于第三电压设置，第二信号线处于第四电压设置。第三电压设定小于第四电压设定值。

9. 发明申请

US20120127804A1 Memory Write Error Correction Circuit 有权
标题翻译：内存写错误纠正电路
公开(公告)号：US20120127804A1
公开(公告)日：2012-05-24
申请号：US13013616
申请日：2011-01-25
申请人： Adrian E. Ong , Vladimir Nitikin
发明人： Adrian E. Ong , Vladimir Nitikin
IPC分类号： G11C7/00 , G11C8/06
CPC分类号： G11C7/1006 , G11C7/22 , G11C11/1659 , G11C11/1675 , G11C11/1677 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0064 , G11C2211/5647
摘要： Memory circuit includes; an array, row decoder, column decoder, addressing circuit to receive an address of the data bit, control logic receiving commands and transmitting control signals to memory system blocks, and sensing and write driver circuits coupled to a selected column. A hidden read compare circuit couples between the sensing circuit and write driver, which couples an error flag to the control logic circuit responsive to a comparison between a data bit in the input latch and a data-out read from the memory array. A write error address tag memory is responsive to the error flag and is coupled to the addressing circuit via a bidirectional bus. A data input output circuit having first and second bidirectional buses to transmit and receive said data bit is provided. Write error address tag memory stores the address if the error flag is set and provides the address during a re-write operation.
摘要翻译：存储电路包括阵列，行解码器，列解码器，用于接收数据位的地址的寻址电路，控制逻辑接收命令并向存储器系统块发送控制信号，以及感测和写入耦合到所选列的驱动器电路。隐藏的读取比较电路耦合在感测电路和写入驱动器之间，该驱动器响应于输入锁存器中的数据位与从存储器阵列读取的数据输出之间的比较将错误标志耦合到控制逻辑电路。写错误地址标签存储器响应于错误标志，并且经由双向总线耦合到寻址电路。提供了具有用于发送和接收所述数据位的第一和第二双向总线的数据输入输出电路。写错误地址标签存储器如果设置了错误标志，则存储地址，并在重写操作期间提供地址。

10. 发明授权

US07779311B2 Testing and recovery in a multilayer device 有权
标题翻译：在多层设备中进行测试和恢复
公开(公告)号：US07779311B2
公开(公告)日：2010-08-17
申请号：US11538799
申请日：2006-10-04
申请人： Adrian E. Ong
发明人： Adrian E. Ong
IPC分类号： G11C29/00 , G01R31/26 , H01L31/00 , H01L23/02
CPC分类号： G11C29/48 , G11C29/1201 , G11C29/72
摘要： Disclosed are systems and methods of producing electronic devices including an auxiliary circuit mounted on another, underlying, circuit at the wafer level. The auxiliary circuit is electrically connected to the underlying circuit via micro-scale interconnects. The systems are capable of testing the auxiliary circuit and/or interconnects using an interface within the underlying circuit. For example, the auxiliary circuit may be tested although it is mounted such that the interconnects are hidden, i.e., inaccessible for testing purposes after assembly using conventional testing systems and methods.The systems and methods further allow for including excess circuits and/or excess interconnects that can be reconfigured to replace parts of the auxiliary circuit and/or micro-scale interconnects found defective during testing.
摘要翻译：公开了制造电子器件的系统和方法，其包括安装在晶片级的另一个下层电路上的辅助电路。辅助电路通过微尺度互连电连接到底层电路。该系统能够使用底层电路内的接口来测试辅助电路和/或互连。例如，可以对辅助电路进行测试，尽管它被安装成使得互连是隐藏的，即在使用常规测试系统和方法组装之后不能进行测试。这些系统和方法还允许包括可以被重新配置的多余电路和/或多余的互连以替代在测试期间发现有缺陷的辅助电路和/或微尺度互连的部分。

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