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31. 发明专利

JP2010044834A Method of manufacturing magnetic recording medium 有权
标题翻译：制造磁记录介质的方法
公开(公告)号：JP2010044834A
公开(公告)日：2010-02-25
申请号：JP2008208961
申请日：2008-08-14
申请人： Fuji Electric Device Technology Co Ltd , 富士電機デバイステクノロジー株式会社
发明人： OSAWA YOSHIHITO
IPC分类号： G11B5/84
CPC分类号： G11B5/8408
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a high-density magnetic recording medium inexpensively in a short time with a small environmental load.
SOLUTION: The method of manufacturing the magnetic recording medium includes ejecting 0.1-10 picoliter per ejection from a nozzle to form a lubricating layer while a lubricant liquid which contains at least a perfluoropolyether lubricant is heated, in a process of forming the lubricating layer of a magnetic recording medium formed by laminating at least a nonmagnetic underlayer, a magnetic layer, a protective layer, and the lubricating layer in order on a nonmagnetic substrate.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种以小的环境负荷在短时间内廉价地制造高密度磁记录介质的方法。解决方案：制造磁记录介质的方法包括：在喷射形成润滑剂的过程中，从喷嘴喷射0.1-10皮升，形成润滑层，同时加入至少含有全氟聚醚润滑剂的润滑剂液体层叠至少非磁性底层，磁性层，保护层和润滑层而形成的磁记录介质。版权所有（C）2010，JPO＆INPIT

32. 发明专利

JP2010027142A Method for manufacturing substrate for information recording medium 有权
标题翻译：用于制造信息记录介质的基板的方法
公开(公告)号：JP2010027142A
公开(公告)日：2010-02-04
申请号：JP2008187138
申请日：2008-07-18
申请人： Fuji Electric Device Technology Co Ltd , 富士電機デバイステクノロジー株式会社
发明人： TSUDA KOICHI
IPC分类号： G11B5/84 , G11B5/73
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a substrate for an information recording medium which satisfies requirements of contradictory thermal characteristics of low effective thermal conductivity upon temperature increase and high effective thermal conductivity upon temperature decrease, and static and dynamic mechanical strength of high resistance to circular transverse rupture and high resistance to impact and drop.
SOLUTION: The method for manufacturing a substrate for an information recording medium includes: (a) a step of preparing a silicon single crystal support which has a disk shape having a central hole and which includes a main flat surface, a substrate inner circumference part adjacent to the central hole, and a substrate outer circumference part positioned at the opposite side of the main flat surface with respect to the substrate inner circumference part; and (b) a step of supplying an oxidizing gas to the substrate inner circumference part, heating the silicon single crystal support in a state where an inert or reducing gas is supplied to the main flat surface and the substrate outer circumference part, and selectively forming a SiO
2 film on the substrate inner circumference part.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供一种用于制造信息记录介质的基板的方法，其满足在温度升高时低有效热导率的相互矛盾的热特性以及降低时的高有效热导率以及静态和动态机械强度高，耐圆环横断裂，抗冲击和降落性能高。解决方案：用于信息记录介质的基板的制造方法包括：（a）制备具有中心孔的圆盘形状并包括主平面的硅单晶支撑体的步骤，与所述中心孔相邻的圆周部分和位于所述主平面的相对于所述基板内周部的相对侧的基板外周部; 和（b）向基板内周部供给氧化气体的步骤，在向主平坦面和基板外周部供给惰性气体或还原气体的状态下加热硅单晶支撑体，并选择性地形成在基板内周部上的SiO 2 SB 2膜。版权所有（C）2010，JPO＆INPIT

33. 发明专利

JP2010021218A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2010021218A
公开(公告)日：2010-01-28
申请号：JP2008178530
申请日：2008-07-09
申请人： Fuji Electric Device Technology Co Ltd , 富士電機デバイステクノロジー株式会社
发明人： MATSUNAGA SHINICHIRO
IPC分类号： H01L21/822 , H01L21/3205 , H01L21/76 , H01L23/52 , H01L27/04 , H01L29/06
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device with a novel floating guard ring structure, which reduces a leakage current than a conventional floating guard ring structure. SOLUTION: The floating guard ring structure comprising a separate Nwell 4, Pwell 5, p + regions 6 and 7, and interconnections (a) to (e) is arranged around circuit Nwell 3a where a control circuit etc., is formed to suppress inflow of the leakage current from output-stage Nwell 2 where an output stage element is formed. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供具有新颖的浮动保护环结构的半导体器件，其减小了比传统的浮动保护环结构的漏电流。解决方案：包括单独的Nwell 4，Pwell 5，p + SP区域6和7以及互连（a）至（e）的浮动保护环结构围绕电路Nwell 3a布置，其中控制电路等被形成为抑制来自输出级元件的输出级Nwell2的漏电流的流入。版权所有（C）2010，JPO＆INPIT

34. 发明专利

JP2010017865A Method for manufacturing mold for nanoimprinting 审中-公开
标题翻译：制造用于纳米压印的模具的方法
公开(公告)号：JP2010017865A
公开(公告)日：2010-01-28
申请号：JP2008177882
申请日：2008-07-08
申请人： Fuji Electric Device Technology Co Ltd , 富士電機デバイステクノロジー株式会社
发明人： IMAI BUNICHI
IPC分类号： B29C59/02 , B29C33/38 , G11B7/26
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a mold for nanoimprinting with which a high-quality mold can be obtained by forming a current seed layer without using a sputtering method for a resist pattern.
SOLUTION: The method includes the process (1) for preparing a substrate 10 having a conductive surface, the process (2) for forming a resist layer 20 having an uneven pattern on the substrate having the conductive surface to have the conductive pattern exposed from the recesses of the pattern of the resist layer, the process (3) for carrying out electroforming on the conductive surface exposed from the recesses of the pattern of the resist layer to form an electroformed film 40 thicker than the resist layer, and the process (4) for removing the substrate having the conductive surface and the resist layer.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决方案：提供一种制造用于纳米压印的模具的方法，通过在不使用用于抗蚀剂图案的溅射方法的情况下形成电流晶种层可以获得高质量的模具。解决方案：该方法包括用于制备具有导电表面的衬底10的工艺（1），用于在具有导电表面的衬底上形成具有凹凸图案的抗蚀剂层20的工艺（2）具有导电图案从抗蚀剂层的图案的凹部露出的工艺（3），用于在从抗蚀剂层的图案的凹部露出的导电表面上进行电铸以形成比抗蚀剂层厚的电铸膜40，用于去除具有导电表面的基板和抗蚀剂层的工艺（4）。版权所有（C）2010，JPO＆INPIT

35. 发明专利

JP2010003970A Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：JP2010003970A
公开(公告)日：2010-01-07
申请号：JP2008163408
申请日：2008-06-23
申请人： Fuji Electric Device Technology Co Ltd , 富士電機デバイステクノロジー株式会社
发明人： TAKEI MANABU
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66712 , H01L23/544 , H01L29/0634 , H01L29/66136 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device which prevents the occurrence of crystal defects of an embedded epitaxial film caused by an oxide film to lessen the leak current when a super junction semiconductor device having an SJ-column by a trench-embedded system is manufactured, and controls the removal of an over epitaxial layer on the SJ-column to reduce the broadness of the voltage withstand distribution. SOLUTION: An oxide film and a nitride film are formed in order on a high resistance n-type epitaxial layer surface on a low resistance n-type semiconductor substrate. The nitride film on a scribe region is left by patterning and an alignment marker is opened simultaneously. A trench pattern is opened on the oxide film to thereafter form a high aspect ratio trench. The oxide film outside the scribe region is removed; a p-type epitaxial layer in embedded in the trench; the over epitaxial layer is ground with the nitride film as a reference, and finished by etching to expose the n-type epitaxial layer surface. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供一种半导体器件的制造方法，其防止当具有SJ柱的超结半导体器件时，由氧化物膜引起的嵌入式外延膜的晶体缺陷的发生减小漏电流制造了沟槽嵌入式系统，并且控制了在SJ-列上的过度外延层的去除以减小耐电压分布的宽度。解决方案：在低电阻n型半导体衬底上的高电阻n型外延层表面上依次形成氧化物膜和氮化物膜。划线区域上的氮化物膜通过图案化留下，同时打开对准标记。在氧化膜上打开沟槽图案，之后形成高纵横比的沟槽。去除划线区域外的氧化膜; 嵌入沟槽中的p型外延层; 用氮化物膜作为参考，研磨过外延层，并通过蚀刻完成露出n型外延层表面。版权所有（C）2010，JPO＆INPIT

36. 发明专利

JP2009295773A Mos type semiconductor device 有权
标题翻译： MOS型半导体器件
公开(公告)号：JP2009295773A
公开(公告)日：2009-12-17
申请号：JP2008147714
申请日：2008-06-05
申请人： Fuji Electric Device Technology Co Ltd , 富士電機デバイステクノロジー株式会社
发明人： YAMAZAKI TOMOYUKI
IPC分类号： H01L29/78 , H01L29/739
CPC分类号： H01L29/7397 , H01L29/0696 , H01L29/1095 , H01L29/7395 , H01L29/7802 , H01L29/7813
摘要： PROBLEM TO BE SOLVED: To provide a MOS type semiconductor device improved in breakdown resistance and having high reliability by suppressing a gain increase of a parasitic transistor caused by photo pattern defect liable to occur due to micronization of a process design rule. SOLUTION: A partially missing part is formed on a surface of an n+ emitter region 9 on surfaces between gate electrodes 7 of a MOS gate structure to form a surface pattern for expanding a surface area of a p+ contact region 9 surrounded by a surface of the n+ emitter region 9. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种通过抑制由于工艺设计规则的微粉化而容易发生的光图案缺陷导致的寄生晶体管的增益增加而提供耐击穿性提高并具有高可靠性的MOS型半导体器件。解决方案：在MOS栅极结构的栅电极7之间的表面上，在n +发射区9的表面上形成部分缺失的部分，以形成用于扩展被p +接触区9包围的表面积的表面图案 n +发射区9的表面。版权所有（C）2010，JPO＆INPIT

37. 发明专利

JP2009294044A Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2009294044A
公开(公告)日：2009-12-17
申请号：JP2008147209
申请日：2008-06-04
申请人： Fuji Electric Device Technology Co Ltd , 富士電機デバイステクノロジー株式会社
发明人： SAITO KAZUNORI , NISHIKAWA MUTSUO
IPC分类号： G01L9/00 , H01L21/66 , H01L29/84
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing semiconductor devices capable of effectively selecting or removing a semiconductor device having a pinhole in a gold film to the semiconductor device including a semiconductor pressure sensor area wherein a lower-layer electrode film is prevented from being corroded by forming the gold film on the top surface of a layered metal film having an aluminum or aluminum alloy electrode film at its lower layer.
SOLUTION: In the method for manufacturing the semiconductor devices has a process of forming a corrosion-resistant dielectric film 4 on the surface of a semiconductor substrate 100a excluding its pad part, and subsequently forming the gold film 6 on the aluminum electrode film 3 which is disposed on the surface of the pad part, through a metal film 5 for improving the degree of adhesion and preventing any mutual diffusion, in order to form the layered metal film, a process is prepared for immersing the semiconductor substrate 100a in an etching solution of aluminum after the process of forming the layered metal film.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供一种半导体器件的制造方法，其能够有效地选择或去除具有金膜的针孔的半导体器件到半导体器件，该半导体器件包括半导体压力传感器区域，其中下层电极膜为通过在其下层具有铝或铝合金电极膜的层状金属膜的顶面上形成金膜而防止被腐蚀。解决方案：在半导体器件的制造方法中，具有在除了焊盘部分之外的半导体基板100a的表面上形成耐蚀电介质膜4的工序，随后在铝电极膜上形成金膜6 3，其通过金属膜5设置在焊盘部分的表面上，用于提高粘合度并防止任何相互扩散，为了形成层状金属膜，准备将半导体衬底100a浸入在形成层状金属膜的过程之后蚀刻铝的溶液。版权所有（C）2010，JPO＆INPIT

38. 发明专利

JP2009290986A Backflow prevention circuit for synchronous rectification dc-dc converter 有权
标题翻译：逆流预防电路同步整流DC-DC转换器
公开(公告)号：JP2009290986A
公开(公告)日：2009-12-10
申请号：JP2008140594
申请日：2008-05-29
申请人： Fuji Electric Device Technology Co Ltd , 富士電機デバイステクノロジー株式会社
发明人： YAMADA KOHEI
IPC分类号： H02M3/155
CPC分类号： H02M3/1588 , Y02B70/1466
摘要： PROBLEM TO BE SOLVED: To provide a backflow prevention circuit for a synchronous rectification DC-DC converter that is not affected by variations in input offset voltage of a comparator.
SOLUTION: The backflow prevention circuit 100 includes a comparator 200, a backflow detection circuit 300, a memory 400, a flip-flop 500, and a synchronous rectification element Mn (110). A value of an inductor current IL when the Mn (110) is turned off can be determined from a significant change in a switching terminal voltage Vsw immediately after the turning-off. In accordance with a state in which a reverse current flows in an inductor L (40) (IL 0) when the Mn (110) is turned off, an output signal 370 is added to the memory 400 from the backflow detection circuit 300. The memory 400 outputs a control signal Vctrl (450) for controlling an offset voltage to the comparator 200 according to the output signal so as to move an operation point in a direction that the comparator 200 reacts with a current on the further positive side/a current on the further negative side.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供不受比较器的输入偏移电压的变化影响的同步整流DC-DC转换器的防回流电路。解决方案：防回流电路100包括比较器200，回流检测电路300，存储器400，触发器500和同步整流元件Mn（110）。 Mn（110）关断时的电感电流IL的值可以根据紧接关闭后的开关端子电压Vsw的显着变化来确定。根据在电感器L（40）（IL <0）/其中正向电流流过电感器L（40）（IL> 0）中的正向电流的状态（IL> 0）时的反向电流流动的状态）输出信号370从回流检测电路300加到存储器400中。存储器400根据输出信号输出控制信号Vctr1（450），用于根据输出信号控制比较器200的偏移电压，以移动比较器200在另一负侧的另一正侧/电流上的电流反应的方向上的操作点。版权所有（C）2010，JPO＆INPIT

39. 发明专利

JP2009283106A Magnetic disk and method for manufacturing the same 有权
标题翻译：磁盘及其制造方法
公开(公告)号：JP2009283106A
公开(公告)日：2009-12-03
申请号：JP2008136787
申请日：2008-05-26
申请人： Fuji Electric Device Technology Co Ltd , 富士電機デバイステクノロジー株式会社
发明人： WATANABE TAKESHI
IPC分类号： G11B5/84 , G11B5/725
摘要： PROBLEM TO BE SOLVED: To provide a magnetic disk, wherein ruggedness of the surface of a lubricant layer is relaxed. SOLUTION: A method for manufacturing the magnetic disk includes: a step (A) for providing a magnetic disk substrate, having at least a non-magnetic substrate and a magnetic layer; a step (B) for applying a lubricant solution containing a perfluoropolyether, based compound on the surface on the magnetic layer side of the magnetic disk substrate to dispose the lubricant layer; and a step (C) for subjecting the magnetic disk substrate on which the lubricant layer is subjected to a high-temperature high-humidity treatment, in the conditions of ≥50°C temperature and ≥60% relative humidity so as to planarize the surface of the lubricant layer. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种磁盘，其中润滑剂层的表面的粗糙度被松弛。解决方案：一种用于制造磁盘的方法包括：用于提供至少具有非磁性衬底和磁性层的磁盘衬底的步骤（A）; 在所述磁盘基板的磁性层一侧的表面上涂布含有全氟聚醚类化合物的润滑剂溶液以设置润滑剂层的步骤（B）; 以及在≥50℃温度和≥60％相对湿度的条件下对其上进行高温高湿处理的磁盘基板进行处理的步骤（C），以使表面平坦化的润滑剂层。版权所有（C）2010，JPO＆INPIT

40. 发明专利

JP2009262351A Imprint method and its apparatus 有权
标题翻译：印刷方法及其设备
公开(公告)号：JP2009262351A
公开(公告)日：2009-11-12
申请号：JP2008111763
申请日：2008-04-22
申请人： Fuji Electric Device Technology Co Ltd , 富士電機デバイステクノロジー株式会社
发明人： UCHIDA SHINJI
IPC分类号： B29C59/02 , H01L21/027
CPC分类号： G11B5/855
摘要： PROBLEM TO BE SOLVED: To provide a method which enabales nano-imprint working to efficiently be carried out and its apparatus. SOLUTION: The method includes at least an alignment process for setting a substrate coated with a resist for a room temperature imprint and a mold with an uneven pattern formed on its offset surface in an incorporation tool, a press process for pushing the pattern surface of the mold to the resist surface of the substrate, and a separation process in which the mold is separated from the substrate to be separated into the substrate, the mold, and the incorporation tool. In the imprint method, each process is carried out in an independent unit in which one process is carried out, and a conveyance process in which, from the alignment process to the separation process, the mold and the substrate are made a pair by the incorporation tool and conveyed between units is set between the units. The imprint apparatus has at least an alignment unit in which the alignment process is carried out, a press unit in which the press process is carried out, and a separation unit in which the separation process is carried out and is provided with a conveyance means for carrying out the conveyance process. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种有效地实现纳米压印工作的方法及其装置。解决方案：该方法至少包括用于设置涂覆有用于室温压印的抗蚀剂的基材和在其结合工具中形成在其偏移表面上的具有不平坦图案的模具的对准过程，用于推动图案模具的表面到基板的抗蚀剂表面，以及分离工艺，其中模具与基板分离以分离成基板，模具和结合工具。在压印方法中，每个处理在其中执行一个处理的独立单元中进行，并且通过结合使得从对准处理到分离处理，模具和基板成对的输送处理在单元之间设置工具并在单元之间传送。压印装置至少具有进行对准处理的对准单元，进行加压处理的压制单元和进行分离处理的分离单元，并且设置有用于进行运输过程。版权所有（C）2010，JPO＆INPIT

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