专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US06515511B2 Semiconductor integrated circuit and semiconductor integrated circuit device 有权
标题翻译：半导体集成电路和半导体集成电路器件
公开(公告)号：US06515511B2
公开(公告)日：2003-02-04
申请号：US09785089
申请日：2001-02-16
申请人： Tadahiko Sugibayashi , Tohru Mogami
发明人： Tadahiko Sugibayashi , Tohru Mogami
IPC分类号： H03K19177
CPC分类号： H01L27/1203 , H01L21/8221 , H01L27/0688 , H01L27/11807 , H01L27/1214
摘要： A semiconductor integrated circuit device has a plurality of basic cells. The basic cells are placed in a matrix form, and are formed on a semiconductor substrate. Each of the basic cells includes a wire selection portion and a logic gate portion. The logic gate portion has a MOS transistor. The wire selection portion has a thin-film transistor serving as a transfer gate. The wire selection portion is placed over the logic gate portion via an interlayer insulating film.
摘要翻译：半导体集成电路器件具有多个基本单元。将基本电池放置成矩阵形式，并形成在半导体衬底上。每个基本单元包括导线选择部分和逻辑门部分。逻辑门部分具有MOS晶体管。导线选择部分具有用作转移栅极的薄膜晶体管。电线选择部分经由层间绝缘膜放置在逻辑门部分上。

22. 发明授权

US06512395B1 Configurable memory for programmable logic circuits 有权
公开(公告)号：US06512395B1
公开(公告)日：2003-01-28
申请号：US10024093
申请日：2001-12-18
申请人： Timothy M. Lacey , David L. Johnson
发明人： Timothy M. Lacey , David L. Johnson
IPC分类号： H03K19177
CPC分类号： H03K19/1776
摘要： An apparatus comprising a memory device and a programmable logic device. The memory device may be configured to (i) connect to a first bus and a second bus and (ii) operate in one or more modes in response to one or more control signals. The programmable logic device may be configured to generate the control signals.

23. 发明授权

US06504399B2 Method and apparatus for universal program controlled bus architecture 失效
公开(公告)号：US06504399B2
公开(公告)日：2003-01-07
申请号：US09960916
申请日：2001-09-24
申请人： Peter M. Pani , Benjamin S. Ting
发明人： Peter M. Pani , Benjamin S. Ting
IPC分类号： H03K19177
CPC分类号： H03K19/17704 , H03K19/17728 , H03K19/17736 , H03K19/17744 , H03K19/17796
摘要： The system and method of the present invention provides an innovative bus system of lines which can be programmed and to provide data, control and address information to the logic circuits interconnected by the bus system. This flexible structure and process enables a configurable system to be created to programmably connect one or more logic circuits, such as megacells. The programmability of the bus system enables the cascading of multiple megacells in an arbitrary fashion (i.e., wide, deep or both) and the sharing of common lines for system level communication.

24. 发明授权

US06486702B1 Embedded memory blocks for programmable logic 有权
标题翻译：用于可编程逻辑的嵌入式存储块
公开(公告)号：US06486702B1
公开(公告)日：2002-11-26
申请号：US09609102
申请日：2000-06-30
申请人： Tony Ngai , Sergey Shumarayev , Wei-Jen Huang , Rakesh Patel , Tin Lai
发明人： Tony Ngai , Sergey Shumarayev , Wei-Jen Huang , Rakesh Patel , Tin Lai
IPC分类号： H03K19177
CPC分类号： G11C5/025 , H03K19/17736 , H03K19/1776
摘要： A high-performance programmable logic architecture has embedded memory (608). arranged at the peripheries or edges of the integrated circuit. This enhances the performance of the programmable logic integrated circuit by shortening the lengths of the programmable interconnect (748). In a specific embodiment, the memory blocks (703) are organized in rows along the top and bottom edges of the integrated circuit. The logic elements (805) can be directly programmable routed and connected to driver blocks (809) of the logic block in adjacent rows and columns. This permits fast interconnection of signals without using the global programmable interconnect resources (815, 825). Using similar direct programmable interconnections (828, 830, 835), the logic blocks can directly programmable connect to the memory blocks without using the global programmable interconnect resources. The present invention also provides technique of flexibly combining or stitching multiple memories together to form memories of a desired size.
摘要翻译：高性能可编程逻辑架构具有嵌入式存储器（608）。布置在集成电路的周边或边缘。这通过缩短可编程互连（748）的长度来增强可编程逻辑集成电路的性能。在一个具体实施例中，存储块（703）沿着集成电路的顶部和底部边缘被排列成行。逻辑元件（805）可以直接编程路由并连接到相邻行和列中的逻辑块的驱动器块（809）。这允许信号的快速互连，而不使用全局可编程互连资源（815,825）。使用类似的直接可编程互连（828,88,835），逻辑块可以直接可编程地连接到存储器块而不使用全局可编程互连资源。本发明还提供了将多个存储器灵活组合或拼接在一起以形成所需尺寸的存储器的技术。

25. 发明授权

US06480026B2 Multi-functional I/O buffers in a field programmable gate array (FPGA) 有权
标题翻译：现场可编程门阵列（FPGA）中的多功能I / O缓冲器
公开(公告)号：US06480026B2
公开(公告)日：2002-11-12
申请号：US09864289
申请日：2001-05-25
申请人： William B. Andrews , Harold N. Scholz
发明人： William B. Andrews , Harold N. Scholz
IPC分类号： H03K19177
CPC分类号： G06F1/10 , H03K5/13 , H03K5/133 , H03K19/017581 , H03K19/17732 , H03K19/17736 , H03K19/1774 , H03K19/17744 , H03K19/17748 , H03K19/1776 , H03K19/17788 , H03K19/17792 , H03L7/081 , H03L7/0996
摘要： A multi-functional programmable I/O buffer in a Field Programmable Gate Array (FPGA) device. The I/O buffer is programmably configurable to meet any of a wide range of I/O standards, be it single ended or differential, 5V, 3.3V, 2.5V or 1.5V logic, without the need for implementing multiple I/O buffers to properly handle each different iteration of I/O requirements. An embedded, internal programmable resistor (e.g., a programmable 100 ohm resistor) is programmably selected for use in differential I/O applications, thus eliminating the conventional requirement for the use of an external resistor connected to each differential receiver I/O pin. The present invention also separates I/O pads into groups in each of a plurality of banks in a programmable device (e.g., PLD, FPGA, etc.), with each group being separately powered by the user. The disclosed multi-functional I/O buffer may be programmably configured by the user to be, e.g., a single ended receiver or transmitter, a reference receiver or transmitter, or a differential receiver or transmitter. The pad logic of the multi-functional I/O buffer may include a double data rate input and output mode, each of which includes two flip-flop devices operating on opposite sides of a data clock signal. One of the two flip-flop devices may be borrowed from another logic element, e.g., from a shift register logic element.
摘要翻译：现场可编程门阵列（FPGA）设备中的多功能可编程I / O缓冲器。 I / O缓冲器可编程配置，可满足任何I / O标准，无论是单端还是差分5V，3.3V，2.5V或1.5V逻辑，无需实现多个I / O缓冲器以适当地处理每个不同的I / O要求的迭代。嵌入式内部可编程电阻器（例如，可编程100欧姆电阻器）可编程选择用于差分I / O应用，从而消除了使用连接到每个差分接收器I / O引脚的外部电阻器的常规要求。本发明还将可编程器件（例如，PLD，FPGA等）中的I / O焊盘分成多个组中的每个组中的每个组，每个组由用户单独供电。所公开的多功能I / O缓冲器可由用户可编程地配置为例如单端接收器或发射器，参考接收器或发射器，或差分接收器或发射器。多功能I / O缓冲器的焊盘逻辑可以包括双数据速率输入和输出模式，每个数据速率输入和输出模式包括在数据时钟信号的相对侧上操作的两个触发器装置。两个触发器装置中的一个可以从另一个逻辑元件借用，例如来自移位寄存器逻辑元件。

26. 发明授权

US06469540B2 Reconfigurable device having programmable interconnect network suitable for implementing data paths 有权
标题翻译：具有适于实现数据路径的可编程互连网络的可重配置设备
公开(公告)号：US06469540B2
公开(公告)日：2002-10-22
申请号：US09880018
申请日：2001-06-14
申请人： Shogo Nakaya
发明人： Shogo Nakaya
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K19/17728 , H03K19/17792
摘要： A reconfigurable device includes a plurality of function cells and a programmable interconnect network which programmably connects the function cells. The programmable interconnect network includes horizontal programmable interconnect ways and vertical programmable interconnect ways. Each horizontal programmable interconnect way includes a short horizontal programmable interconnect channel and a long horizontal programmable interconnect channel, and each vertical programmable interconnect way includes a short vertical programmable interconnect channel and a long vertical programmable interconnect channel. In the horizontal programmable interconnect way, both the short horizontal programmable interconnect channel and the long horizontal programmable interconnect channel are constructed to have “shift structure”, thereby “sector segmentation” and problems related to the sector segmentation are avoided. The function cells are directly connected to the short horizontal programmable interconnect channel, but are not directly connected to the long horizontal programmable interconnect channel, therefore, signal transfer of input/output signals between the function cell and the long horizontal programmable interconnect channel is conducted necessarily through the short horizontal programmable interconnect channel and a programmable switch, thereby load capacitance on the long horizontal programmable interconnect channel is reduced and thereby high-speed signal transfer is realized.
摘要翻译：可重构设备包括多个功能单元和可编程地连接功能单元的可编程互连网络。可编程互连网络包括水平可编程互连方式和垂直可编程互连方式。每个水平可编程互连方式包括一个短的水平可编程互连通道和一个长的水平可编程互连通道，每个垂直可编程互连方式包括一个短的垂直可编程互连通道和一个长的垂直可编程互连通道。在水平可编程互联方式中，短水平可编程互连通道和长水平可编程互连通道被构造为具有“移位结构”，从而避免了“扇区分割”，并且避免了与扇区分割相关的问题。功能单元直接连接到短水平可编程互连通道，但不直接连接到长水平可编程互连通道，因此必须执行功能单元和长水平可编程互连通道之间的输入/输出信号的信号传输通过短水平可编程互连通道和可编程开关，从而减小了长水平可编程互连通道上的负载电容，从而实现了高速信号传输。

27. 发明授权

US06466052B1 Implementing wide multiplexers in an FPGA using a horizontal chain structure 有权
标题翻译：在FPGA中使用水平链结构实现广泛的多路复用器
公开(公告)号：US06466052B1
公开(公告)日：2002-10-15
申请号：US09858991
申请日：2001-05-15
申请人： Alireza S. Kaviani
发明人： Alireza S. Kaviani
IPC分类号： H03K19177
CPC分类号： H03K19/1778 , H03K19/1737 , H03K19/17728
摘要： Methods and structures for implementing wide multiplexers in programmable logic devices (PLDs) in a distributed fashion. According to one embodiment, a configurable logic structure includes a function generator, a carry multiplexer, and an OR gate. The function generator is configured to implement a multiplexing function (under control of a first select signal) and an AND function (ANDing the output of the multiplexer with a second select signal). The carry multiplexer is configured to perform an AND function between an output of the function generator and a third select signal. Thus, with three select signals available, an 8-to-1 multiplexer can be implemented by combining the outputs of four different logic structures that use different values of the select signals. This combination of outputs is performed by forming an OR chain, with the OR input of each stage being provided by the associated carry multiplexer.
摘要翻译：以分布式方式在可编程逻辑器件（PLD）中实现宽多路复用器的方法和结构。根据一个实施例，可配置逻辑结构包括功能发生器，进位复用器和或门。功能发生器被配置为实现多路复用功能（在第一选择信号的控制下）和AND功能（将多路复用器的输出与第二选择信号进行AND运算）。进位复用器被配置为在函数发生器的输出和第三选择信号之间执行AND功能。因此，通过三种可用的选择信号，可以通过组合使用不同选择信号值的四种不同逻辑结构的输出来实现8对1多路复用器。通过形成OR链来执行输出的组合，每个级的OR输入由相关的进位多路复用器提供。

28. 发明授权

US06420902B1 Field programmable logic arrays with transistors with vertical gates 有权
标题翻译：具有垂直栅极晶体管的现场可编程逻辑阵列
公开(公告)号：US06420902B1
公开(公告)日：2002-07-16
申请号：US09583584
申请日：2000-05-31
申请人： Leonard Forbes , Kie Y. Ahn
发明人： Leonard Forbes , Kie Y. Ahn
IPC分类号： H03K19177
CPC分类号： H01L27/11521 , H01L21/28273
摘要： Structures and methods for programmable logic arrays are provided with logic cells, or floating gate transistors, which can operate with lower applied control gate voltages than conventional programmable logic arrays. The programmable logic arrays of the present invention do not increase the costs or complexity of the fabrication process. According to the teachings of the present invention, the floating gate capacitance in the logic cells is much smaller than the control gate capacitance such that the majority of any voltage applied to the control gate will appear across the floating gate thin tunnel oxide. The programmable logic arrays include a plurality of input lines for receiving an input signal and a plurality of output lines. One or more arrays is provided which includes a first logic plane and a second logic plane connected between the input lines and the output lines. The first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to the received input signal. Each logic cell includes a source and a drain region in a horizontal substrate with a channel region therebetween. A first vertical gate is located above a portion of the channel region and separated from the channel region by a first oxide thickness. A second vertical gate is located above another portion of the channel region and separated therefrom by a second oxide thickness.
摘要翻译：可编程逻辑阵列的结构和方法提供有逻辑单元或浮栅晶体管，其可以以比常规可编程逻辑阵列更低的施加的控制栅极电压工作。本发明的可编程逻辑阵列不会增加制造过程的成本或复杂性。根据本发明的教导，逻辑单元中的浮置栅极电容远小于控制栅极电容，使得施加到控制栅极的任何电压的大部分将出现在浮置栅极薄隧道氧化物上。可编程逻辑阵列包括用于接收输入信号和多条输出线的多条输入线。提供了一个或多个阵列，其包括连接在输入线和输出线之间的第一逻辑平面和第二逻辑平面。第一逻辑平面和第二逻辑平面包括以行和列排列的多个逻辑单元，用于响应于所接收的输入信号在输出线上提供乘积项。每个逻辑单元包括在水平衬底中的源极和漏极区域，其间具有沟道区域。第一垂直栅极位于沟道区的一部分上方并与沟道区分离第一氧化物厚度。第二垂直栅极位于沟道区域的另一部分上方并与第二垂直栅极隔开第二氧化物厚度。

29. 发明授权

US06417694B1 Programmable logic device with hierarchical interconnection resources 有权
标题翻译：具有分层互连资源的可编程逻辑器件
公开(公告)号：US06417694B1
公开(公告)日：2002-07-09
申请号：US09956748
申请日：2001-09-19
申请人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
发明人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17728
摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.
摘要翻译：可编程逻辑器件具有多个可编程逻辑超区域，该多个可编程逻辑超区域以相邻的行和列的超区域的二维阵列布置在器件上。水平和垂直超超导区域互连导体分别与每行和列相关联。每个超区域包括多个可编程逻辑区域，并且每个区域包括多个可编程逻辑子区域。区域间互连导体与每个超区域相关联，主要用于将信号引入超区域并互连超区域中的区域。本地导体与每个区域相关联，主要用于使信号进入该区域。在超区域级别，设备可以是水平和垂直同构的，这有助于产生具有一个或几乎一个的低纵横比的设备。可以提供共享的驱动器电路（例如，用于（1）从子区域和水平和/或垂直导体接收信号，以及（2）将选择的接收信号施加到区域间导体，水平和垂直导体，以及可能的也是当地的导体）。水平和/或垂直导体可以轴向分割，并且可以提供缓冲电路用于将可编程地拼接在一起的轴向段以制造更长的导体。

30. 发明授权

US06392437B2 Programmable multi-standard I/O architecture for FPGAs 有权
标题翻译：用于FPGA的可编程多标准I / O架构
公开(公告)号：US06392437B2
公开(公告)日：2002-05-21
申请号：US09738508
申请日：2000-12-18
申请人： Khaled Ahmad El-Ayat
发明人： Khaled Ahmad El-Ayat
IPC分类号： H03K19177
CPC分类号： H03K19/17744 , H03K19/1778
摘要： The invention discloses an architecture for the input/output buffer section of an FPGA. It provides a convenient and efficient addressing scheme for addressing fuse matrices that are used to configure programmable input/output buffers in the FPGA. The programmable I/O buffers may be configured to implement a large number of different output and input bus standards
摘要翻译：本发明公开了一种用于FPGA的输入/输出缓冲器部分的架构。它提供了一种方便有效的寻址方案，用于寻址用于在FPGA中配置可编程输入/输出缓冲器的熔丝矩阵。可编程I / O缓冲器可以被配置为实现大量不同的输出和输入总线标准

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式