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1. 发明授权

US06515511B2 Semiconductor integrated circuit and semiconductor integrated circuit device 有权
标题翻译：半导体集成电路和半导体集成电路器件
公开(公告)号：US06515511B2
公开(公告)日：2003-02-04
申请号：US09785089
申请日：2001-02-16
申请人： Tadahiko Sugibayashi , Tohru Mogami
发明人： Tadahiko Sugibayashi , Tohru Mogami
IPC分类号： H03K19177
CPC分类号： H01L27/1203 , H01L21/8221 , H01L27/0688 , H01L27/11807 , H01L27/1214
摘要： A semiconductor integrated circuit device has a plurality of basic cells. The basic cells are placed in a matrix form, and are formed on a semiconductor substrate. Each of the basic cells includes a wire selection portion and a logic gate portion. The logic gate portion has a MOS transistor. The wire selection portion has a thin-film transistor serving as a transfer gate. The wire selection portion is placed over the logic gate portion via an interlayer insulating film.
摘要翻译：半导体集成电路器件具有多个基本单元。将基本电池放置成矩阵形式，并形成在半导体衬底上。每个基本单元包括导线选择部分和逻辑门部分。逻辑门部分具有MOS晶体管。导线选择部分具有用作转移栅极的薄膜晶体管。电线选择部分经由层间绝缘膜放置在逻辑门部分上。

2. 发明授权

US08503222B2 Non-volatile logic circuit 有权
标题翻译：非易失性逻辑电路
公开(公告)号：US08503222B2
公开(公告)日：2013-08-06
申请号：US13144480
申请日：2010-01-21
申请人： Tetsuhiro Suzuki , Shunsuke Fukami , Kiyokazu Nagahara , Nobuyuki Ishiwata , Tadahiko Sugibayashi , Noboru Sakimura , Ryusuke Nebashi
发明人： Tetsuhiro Suzuki , Shunsuke Fukami , Kiyokazu Nagahara , Nobuyuki Ishiwata , Tadahiko Sugibayashi , Noboru Sakimura , Ryusuke Nebashi
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C11/5607 , H01L43/08 , H03K19/1776 , H03K19/1778 , H03K19/18 , H03K19/20
摘要： A non-volatile logic circuit includes an input section, a control section and an output section. The input section has perpendicular magnetic anisotropy and has a ferromagnetic layer whose magnetization state is changeable. The control section includes a ferromagnetic layer. The output section is provided in a neighborhood of the input section and the control section and includes a magnetic tunnel junction element whose magnetization state is changeable. The magnetization state of the input section is changed based on the magnetization state. A magnetization state of the magnetic tunnel junction element of the output section which state is changed based on the magnetization state of the ferromagnetic material of the control section and the magnetization state of the ferromagnetic material of the input section.
摘要翻译：非易失性逻辑电路包括输入部分，控制部分和输出部分。输入部具有垂直的磁各向异性，并具有磁化状态可变的铁磁层。控制部分包括铁磁层。输出部分设置在输入部分和控制部分的附近，并且包括磁化状态可变的磁性隧道结元件。基于磁化状态改变输入部的磁化状态。输出部分的磁性隧道结元件的磁化状态基于控制部分的铁磁材料的磁化状态和输入部分的铁磁材料的磁化状态而改变。

3. 发明授权

US08477528B2 Magnetic memory cell and magnetic random access memory 有权
标题翻译：磁存储单元和磁性随机存取存储器
公开(公告)号：US08477528B2
公开(公告)日：2013-07-02
申请号：US12443349
申请日：2007-09-25
申请人： Takeshi Honda , Noboru Sakimura , Tadahiko Sugibayashi , Hideaki Numata , Norikazu Ohshima
发明人： Takeshi Honda , Noboru Sakimura , Tadahiko Sugibayashi , Hideaki Numata , Norikazu Ohshima
IPC分类号： G11C11/00
CPC分类号： H01L27/228 , B82Y10/00 , G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1675 , H01L43/08
摘要： A magnetic memory cell 1 is provided with a magnetic recording layer 10 which is a ferromagnetic layer and a pinned layer 30 connected with the magnetic recording layer 10 through a non-magnetic layer 20. The magnetic recording layer 10 has a magnetization inversion region 13, a first magnetization fixed region 11 and a second magnetization fixed region 12. The magnetization inversion region 13 has a magnetization whose orientation is invertible and overlaps the pinned layer 30. The first magnetization fixed region 11 is connected with a first boundary B1 in the magnetization inversion region 13 and a magnetization orientation is fixed on a first direction. The second magnetization fixed region 12 is connected with a second boundary B2 in magnetization inversion region 13 and a magnetization orientation is fixed on a second direction. The first direction and the second direction are opposite to each other.
摘要翻译：磁存储单元1设置有磁记录层10，磁记录层10是铁磁层，和通过非磁性层20与磁记录层10连接的钉扎层30.磁记录层10具有磁化反转区域13，第一磁化固定区域11和第二磁化固定区域12.磁化反转区域13具有其取向可反转并与被钉扎层30重叠的磁化。第一磁化固定区域11与磁化反转中的第一边界B1连接区域13和磁化取向在第一方向固定。第二磁化固定区域12与磁化反转区域13中的第二边界B2连接，并且磁化取向固定在第二方向上。第一方向和第二方向彼此相反。

4. 发明授权

US08254157B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US08254157B2
公开(公告)日：2012-08-28
申请号：US12593423
申请日：2008-01-17
申请人： Tadahiko Sugibayashi
发明人： Tadahiko Sugibayashi
IPC分类号： G11C11/00 , G11C7/12 , G11C7/00 , G11C7/22 , G11C11/21
CPC分类号： G11C13/0007 , G11C7/04 , G11C13/0069 , G11C2013/0078 , G11C2213/32 , G11C2213/34 , H01L27/101
摘要： A semiconductor integrated circuit includes: an oxide resistance change element, a constant current source circuit supplying a write current to the oxide resistance change element, and a voltage clamper clamping a voltage in a path in which a write current flows. The voltage clamper is arranged in parallel with the path between the constant current source circuit and the oxide resistance change element.
摘要翻译：半导体集成电路包括：氧化物电阻变化元件，向氧化物电阻变化元件提供写入电流的恒定电流源电路，以及夹持写入电流流动的路径中的电压的电压钳位器。电压钳位器与恒流源电路和氧化物电阻变化元件之间的路径平行布置。

5. 发明授权

US08243502B2 Nonvolatile latch circuit and logic circuit using the same 有权
标题翻译：非易失性锁存电路和逻辑电路使用相同
公开(公告)号：US08243502B2
公开(公告)日：2012-08-14
申请号：US12747951
申请日：2008-11-19
申请人： Noboru Sakimura , Tadahiko Sugibayashi , Ryusuke Nebashi
发明人： Noboru Sakimura , Tadahiko Sugibayashi , Ryusuke Nebashi
IPC分类号： G11C11/00
CPC分类号： G11C11/18 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , H01L27/226 , H01L43/08 , H03K3/45
摘要： A nonvolatile latch circuit includes: a latch circuit; a first magnetoresistance element and a second magnetoresistance element; and a current supply portion. The latch circuit temporarily holds data. Each of the first magnetoresistance element and the second magnetoresistance element includes a first magnetic layer and a second magnetic layer that are stacked with an insulating film sandwiched therebetween. The current supply portion complementarily changes magnetization states of the first magnetoresistance element and the second magnetoresistance element based on a state of the latch circuit. The first magnetic layer of the first magnetoresistance element and the first magnetic layer of the second magnetoresistance element are series-connected to each other in. The latch circuit has a function that brings data corresponding to the magnetization states to data held by the latch circuit.
摘要翻译：非易失性锁存电路包括：锁存电路; 第一磁阻元件和第二磁阻元件; 和电流供应部分。锁存电路暂时保存数据。第一磁阻元件和第二磁阻元件中的每一个包括层叠有绝缘膜的第一磁性层和第二磁性层。电流供应部分基于锁存电路的状态互补地改变第一磁阻元件和第二磁阻元件的磁化状态。第一磁阻元件的第一磁性层和第二磁阻元件的第一磁性层彼此串联连接。锁存电路具有将对应于磁化状态的数据带入由锁存电路保持的数据的功能。

6. 发明授权

US07916520B2 Memory cell and magnetic random access memory 有权
标题翻译：存储单元和磁性随机存取存储器
公开(公告)号：US07916520B2
公开(公告)日：2011-03-29
申请号：US11574121
申请日：2005-08-19
申请人： Tadahiko Sugibayashi , Takeshi Honda , Noboru Sakimura , Tetsuhiro Suzuki
发明人： Tadahiko Sugibayashi , Takeshi Honda , Noboru Sakimura , Tetsuhiro Suzuki
IPC分类号： G11C11/00
CPC分类号： H01L27/228 , G11C11/15 , H01L43/08 , Y10S977/935
摘要： A memory cell is used which includes a plurality of magneto-resistive elements and a plurality of laminated ferrimagnetic structure substances. The plurality of the magneto-resistive elements are placed corresponding to respective positions where a plurality of first wirings extended in a first direction intersects with a plurality of second wirings extended in a second direction which is substantially perpendicular to the first direction. The plurality of the laminated ferrimagnetic structure substances corresponds to the plurality of the magneto-resistive elements, respectively, is placed to have a distance of a predetermined range from the respective plurality of the magneto-resistive elements, and has a laminated ferrimagnetic structure. The magneto-resistive element includes a free layer having a laminated ferrimagnetic structure, a fixed layer, and a nonmagnetic layer interposed between the free layer and the fixed layer.
摘要翻译：使用包括多个磁阻元件和多个叠层铁磁结构物质的存储单元。多个磁阻元件对应于在第一方向上延伸的多个第一布线与基本上垂直于第一方向的第二方向延伸的多个第二布线相对应的相应位置放置。多个叠层铁氧体结构物质分别对应于多个磁阻元件，放置成距离相应的多个磁阻元件具有预定范围的距离，并具有叠层铁磁结构。磁阻元件包括层叠的铁磁结构，固定层和插入在自由层和固定层之间的非磁性层的自由层。

7. 发明授权

US07885131B2 Resistance change semiconductor memory device and method of reading data with a first and second switch circuit 有权
标题翻译：电阻变化半导体存储器件以及利用第一和第二开关电路读取数据的方法
公开(公告)号：US07885131B2
公开(公告)日：2011-02-08
申请号：US11815325
申请日：2006-02-01
申请人： Noboru Sakimura , Takeshi Honda , Tadahiko Sugibayashi
发明人： Noboru Sakimura , Takeshi Honda , Tadahiko Sugibayashi
IPC分类号： G11C7/02
CPC分类号： G11C11/16 , G11C7/02 , G11C7/062 , G11C7/14 , G11C11/4091 , G11C11/4099 , G11C13/0002 , G11C13/0004 , G11C13/004 , G11C2013/0054
摘要： A semiconductor memory device of the present invention comprises a memory array and a read circuit that reads data of a selected cell. The memory array includes a plurality of memory cells and a reference cell each having a memory element that stores data based on change in resistance value. The read circuit includes: a voltage comparison unit that compares a value corresponding to a sense current from the selected cell with a value corresponding to a reference current from the reference cell; a first switch; and a second switch. Both of the first and second switches are provided at a subsequent stage of a decoder and at a preceding stage of the voltage comparison unit. The second switch circuit controls input of the value corresponding to the sense current to the voltage comparison unit, while the first switch circuit controls input of the value corresponding to the reference current to the voltage comparison unit.
摘要翻译：本发明的半导体存储器件包括存储器阵列和读取所选择的单元的数据的读取电路。存储器阵列包括多个存储器单元和参考单元，每个存储器单元具有存储元件，该存储元件基于电阻值的变化存储数据。读取电路包括：电压比较单元，将来自所选择的单元的检测电流的值与来自参考单元的参考电流对应的值进行比较; 第一个开关和第二开关。第一和第二开关都被提供在解码器的后续阶段，并且在电压比较单元的前一级提供。第二开关电路将对应于感测电流的值的输入控制到电压比较单元，而第一开关电路将对应于参考电流的值的输入控制到电压比较单元。

8. 发明授权

US07885095B2 Magnetic random access memory and operation method of the same 有权
标题翻译：磁性随机存取存储器及其操作方法相同
公开(公告)号：US07885095B2
公开(公告)日：2011-02-08
申请号：US12303821
申请日：2007-06-01
申请人： Noboru Sakimura , Takeshi Honda , Tadahiko Sugibayashi
发明人： Noboru Sakimura , Takeshi Honda , Tadahiko Sugibayashi
IPC分类号： G11C11/00 , C11C11/14
CPC分类号： G11C11/1673 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1675 , H01L27/228
摘要： A magnetic random access memory of the present invention includes: a plurality of first wirings and a plurality of second wirings extending in a first direction; a plurality of third wirings and a plurality of fourth wirings extending in a second direction; and a plurality of memory cells provided at intersections of the plurality of first wirings and the plurality of third wirings, respectively. Each of the plurality of memory cells includes: a first transistor and a second transistor connected in series between one of the plurality of first wirings and one of the plurality of second wirings and controlled in response to a signal on one of the plurality of third wirings, a first magnetic resistance element having one end connected to a write wiring through which the first transistor and the second transistor are connected, and the other end grounded; and a second magnetic resistance element having one end connected to the write wiring, and the other end connected to the fourth wiring.
摘要翻译：本发明的磁性随机存取存储器包括：沿第一方向延伸的多个第一布线和多条第二布线; 多个第三布线和沿第二方向延伸的多个第四布线; 以及多个存储单元，分别设置在所述多个第一布线和所述多个第三布线的交点处。所述多个存储单元中的每一个包括：第一晶体管和第二晶体管，其串联连接在所述多个第一布线中的一个与所述多个第二布线中的一个之间，并响应于所述多个第三布线之一上的信号而被控制第一磁阻元件，其一端连接到第一晶体管和第二晶体管连接的写入布线，另一端接地; 以及第二磁阻元件，其一端连接到写入布线，另一端连接到第四布线。

9. 发明申请

US20100271866A1 NONVOLATILE LATCH CIRCUIT 有权
标题翻译：非线性锁定电路
公开(公告)号：US20100271866A1
公开(公告)日：2010-10-28
申请号：US12746589
申请日：2008-12-03
申请人： Noboru Sakimura , Tadahiko Sugibayashi , Ryusuke Nebashi
发明人： Noboru Sakimura , Tadahiko Sugibayashi , Ryusuke Nebashi
IPC分类号： G11C11/00 , G11C7/10
CPC分类号： H03K3/45 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C11/18 , G11C14/0081 , H01L27/11 , H03K3/356008 , Y10S977/933 , Y10S977/935
摘要： A nonvolatile latch circuit includes: first and second inverters cross-coupled to hold 1-bit data; first and second magnetoresistive elements each having first to third terminals; and a current supply circuitry configured to supply a magnetization reversal current for changing the magnetization states of the first and second maqnetoresistive elements in response to the 1-bit data. The power terminal of the first inverter is connected to the first terminal of the first magnetoresistive element and the power terminal of the second inverter is connected to the first terminal of the second magnetoresistive element. The current supply circuitry is configured to supply the magnetization reversal current to the second terminals of the first and second magnetoresistive elements. The third terminal of the first magnetoresistive element is electrically connected to the third terminal of the second magnetoresistive element.
摘要翻译：非易失性锁存电路包括：交叉耦合以保持1位数据的第一和第二反相器; 第一和第二磁阻元件各自具有第一至第三端子; 以及电流源电路，被配置为响应于1位数据提供用于改变第一和第二电阻元件的磁化状态的磁化反转电流。第一反相器的电源端子连接到第一磁阻元件的第一端子，第二反相器的电源端子连接到第二磁阻元件的第一端子。电流供应电路被配置为向第一和第二磁阻元件的第二端提供磁化反转电流。第一磁阻元件的第三端子电连接到第二磁阻元件的第三端子。

10. 发明申请

US20100265760A1 NONVOLATILE LATCH CIRCUIT AND LOGIC CIRCUIT USING THE SAME 有权
标题翻译：非线性锁定电路和逻辑电路
公开(公告)号：US20100265760A1
公开(公告)日：2010-10-21
申请号：US12747951
申请日：2008-11-19
申请人： Noboru Sakimura , Tadahiko Sugibayashi , Ryusuke Nebashi
发明人： Noboru Sakimura , Tadahiko Sugibayashi , Ryusuke Nebashi
IPC分类号： G11C11/00 , G11C7/10
CPC分类号： G11C11/18 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , H01L27/226 , H01L43/08 , H03K3/45
摘要： A nonvolatile latch circuit includes: a latch circuit; a first magnetoresistance element and a second magnetoresistance element; and a current supply portion. The latch circuit temporarily holds data. Each of the first magnetoresistance element and the second magnetoresistance element includes a first magnetic layer and a second magnetic layer that are stacked with an insulating film sandwiched therebetween. The current supply portion complementarily changes magnetization states of the first magnetoresistance element and the second magnetoresistance element based on a state of the latch circuit. The first magnetic layer of the first magnetoresistance element and the first magnetic layer of the second magnetoresistance element are series-connected to each other in. The latch circuit has a function that brings data corresponding to the magnetization states to data held by the latch circuit.
摘要翻译：非易失性锁存电路包括：锁存电路; 第一磁阻元件和第二磁阻元件; 和电流供应部分。锁存电路暂时保存数据。第一磁阻元件和第二磁阻元件中的每一个包括层叠有绝缘膜的第一磁性层和第二磁性层。电流供应部分基于锁存电路的状态互补地改变第一磁阻元件和第二磁阻元件的磁化状态。第一磁阻元件的第一磁性层和第二磁阻元件的第一磁性层彼此串联连接。锁存电路具有将对应于磁化状态的数据带入由锁存电路保持的数据的功能。

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