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21. 发明授权

US4213840A Low-resistance, fine-line semiconductor device and the method for its manufacture 失效
标题翻译：低电阻，细线半导体器件及其制造方法
公开(公告)号：US4213840A
公开(公告)日：1980-07-22
申请号：US959792
申请日：1978-11-13
申请人： Masahiro Omori , James N. Wholey , J. Ross Anderson
发明人： Masahiro Omori , James N. Wholey , J. Ross Anderson
IPC分类号： H01L29/80 , H01L21/027 , H01L21/28 , H01L21/285 , H01L21/338 , H01L29/47 , H01L29/812 , H01L21/441
CPC分类号： H01L29/66863 , H01L21/0272 , H01L21/28587 , H01L29/47
摘要： A method of fabricating gate electrodes on microwave field effect transistors is described. A first layer of photo-resist is deposited and photolithographically defined on top of a semiconductor material with openings in the photoresist, corresponding to the gate electrode. In one embodiment, when drain and source electrodes have been previously formed, additional openings in the first layer of photoresist are defined that approximately overlay the drain and source electrodes. A metal layer is then deposited on top of this structure. A second layer of photoresist is then deposited and photolithographically defined on top of the first metal layer, with larger openings which overlay the openings in the first layer of photoresist. The thickness of the gate electrode, and in one embodiment, the sections overlaying the drain and source electrodes, is then increased by plating gold into the openings in the second layer of photoresist.
摘要翻译：描述了在微波场效应晶体管上制造栅电极的方法。沉积第一层光致抗蚀剂，并光刻地限定在半导体材料的顶部，在光刻胶中具有开口，对应于栅电极。在一个实施例中，当预先形成漏极和源电极时，限定第一光致抗蚀剂层中的附加开口，其大致覆盖漏极和源电极。然后在该结构的顶部沉积金属层。然后沉积第二层光致抗蚀剂，并光刻地限定在第一金属层的顶部上，其中较大的开口覆盖第一层光致抗蚀剂中的开口。然后通过将金镀在第二层光致抗蚀剂中的开口中，增加栅电极的厚度，并且在一个实施例中覆盖漏极和源电极的部分。

22. 发明授权

US3931472A Asynchronous quadriphase communications system and method 失效
标题翻译：异步四相通信系统和方法
公开(公告)号：US3931472A
公开(公告)日：1976-01-06
申请号：US467656
申请日：1974-05-07
申请人： Walter J. Gill , James A. Mellenger
发明人： Walter J. Gill , James A. Mellenger
IPC分类号： H04L5/12 , H04L25/03 , H04L27/20 , H04L27/227 , H04J3/06
CPC分类号： H04L27/2067 , H04L25/03866 , H04L27/2275 , H04L5/12 , Y10S370/914
摘要： A communications system and method for transmitting and receiving two independently timed (asynchronous) binary data signals on a quadriphase carrier. The four phase ambiguity ordinarily resulting from quadriphase transmission and reception is overcome by uniquely identifying one input channel, for example, by slightly increasing the clock rate of the channel. In reception each channel is demodulated and the data rate of each channel is examined to identify the increased clock rate channel. That channel is then returned to its original clock rate.
摘要翻译：一种用于在四相载波上发送和接收两个独立定时（异步）二进制数据信号的通信系统和方法。通常通过唯一地识别一个输入通道来克服通常由四相传输和接收产生的四相歧义，例如通过稍微增加信道的时钟速率。在接收中，解调每个信道，并检查每个信道的数据速率以识别增加的时钟速率信道。然后，该通道返回到其原始时钟速率。

23. 发明授权

US5306649A Method for producing a fully walled emitter-base structure in a bipolar transistor 失效
标题翻译：在双极晶体管中制造全壁发射极 - 基极结构的方法
公开(公告)号：US5306649A
公开(公告)日：1994-04-26
申请号：US982226
申请日：1992-11-25
申请人： Francois Hebert
发明人： Francois Hebert
IPC分类号： H01L21/331 , H01L21/265 , H01L29/70
CPC分类号： H01L29/66303 , Y10S148/011
摘要： A self-aligned fully-walled monocrystalline silicon emitter-base structure for a bipolar transistor and methods for producing the structure are provided. The methods involve creating an oxide side wall surrounding a monocrystalline silicon emitter-base structure by first defining the emitter region in a base island region. Successive oxide layers are deposited on top of the emitter region and etched back to produce an oxide wall around the entire perimeter of the emitter region. In a preferred embodiment of the invention a metal silicide is also formed across the top of the base island region of the semiconductor outside of the emitter region. Since the extrinsic base region, outside of the oxide sidewalls, is entirely covered by a low resistance silicide film, the base contact area can be significantly reduced compared to prior art devices.The process results in a fully-walled emitter-base structure made of monocrystalline silicon which exhibits improved high-frequency performance. The peripheral emitter-base capacitance is substantially decreased by the oxide walls which surround the emitter sides. Since the sides of the emitter are walled, no lateral current injection can occur. Bipolar transistors which employ the claimed process exhibit an increased emitter-base breakdown and a reduced forward tunneling current since high sidewall doping levels are eliminated.
摘要翻译：提供了一种用于双极晶体管的自对准全壁单晶硅发射极 - 基极结构及其制造方法。该方法包括通过首先限定基岛区域中的发射极区域来形成围绕单晶硅发射极 - 基极结构的氧化物侧壁。连续的氧化物层沉积在发射极区域的顶部并被回蚀刻以在发射极区域的整个周边周围产生氧化物壁。在本发明的一个优选实施例中，金属硅化物也形成在发射极区外部的半导体基岛区域的顶部。由于外部碱性区域在氧化物侧壁外部被低电阻硅化物膜完全覆盖，所以与现有技术的器件相比，基极接触面积可以显着降低。该过程产生了由单晶硅制成的完全壁的发射极 - 基极结构，其表现出改善的高频性能。外围发射极 - 基极电容通过围绕发射极侧面的氧化物壁显着减小。由于发射极的侧壁是壁的，因此不会发生横向电流注入。采用所要求保护的方法的双极晶体管表现出增加的发射极 - 基极击穿和减少的正向隧穿电流，因为消除了高侧壁掺杂水平。

24. 发明授权

US5288660A Method for forming self-aligned t-shaped transistor electrode 失效
标题翻译：用于形成自对准t形晶体管电极的方法
公开(公告)号：US5288660A
公开(公告)日：1994-02-22
申请号：US11998
申请日：1993-02-01
申请人： Chang-Hwang Hua , Simon S. Chan , Ding-Yuan Day
发明人： Chang-Hwang Hua , Simon S. Chan , Ding-Yuan Day
IPC分类号： H01L21/027 , H01L21/768 , H01L21/283 , H01L21/312
CPC分类号： H01L21/76802 , H01L21/0274
摘要： A T-shaped electrode is formed on a semiconductor substrate by first forming a dielectric film on the substrate. A first layer of photoresist is applied on the upper surface of the dielectric film, and a second layer of photoresist is applied over the first layer of photoresist. The first and second layers of photoresist have different optical properties, requiring different wavelengths of ultraviolet for exposure before developing. Portions of the first and second photoresist layers and the dielectric film are selectively removed by photolithographic techniques with one masking step for forming an opening to the substrate. The first and second photoresist layers adjacent to the opening are ion etched to expose the upper surface of the dielectric film adjacent to the opening. A portion of the first photoresist layer adjacent to the opening is removed to undercut the second photoresist layer. Metal is deposited in the opening and on the exposed upper surface of the dielectric film to form a T-shaped electrode. The first and second photoresist layers are then removed, thereby also removing metal deposited on top of the second layer of photoresist.
摘要翻译：首先在基板上形成电介质膜，在半导体基板上形成T字形电极。在电介质膜的上表面上施加第一层光致抗蚀剂，在第一层光致抗蚀剂上施加第二层光致抗蚀剂。第一层和第二层光致抗蚀剂具有不同的光学性质，在显影之前需要不同波长的紫外线进行曝光。通过光刻技术选择性地去除第一和第二光致抗蚀剂层和电介质膜的部分，其中一个掩模步骤用于形成对该基底的开口。邻近开口的第一和第二光致抗蚀剂层被离子蚀刻以暴露与开口相邻的电介质膜的上表面。去除与开口相邻的第一光致抗蚀剂层的一部分以切割第二光致抗蚀剂层。金属沉积在介质膜的开口和暴露的上表面上以形成T形电极。然后去除第一和第二光致抗蚀剂层，从而也去除沉积在第二层光致抗蚀剂上的金属。

25. 发明授权

US5127984A Rapid wafer thinning process 失效
标题翻译：快速晶圆薄化工艺
公开(公告)号：US5127984A
公开(公告)日：1992-07-07
申请号：US694904
申请日：1991-05-02
申请人： Chang-Hwang Hua , Ding Y. S. Day
发明人： Chang-Hwang Hua , Ding Y. S. Day
IPC分类号： H01L21/306
CPC分类号： H01L21/30612
摘要： A method for thinning a Gallium Arsenide (GaAs) layer on the backside of a wafer substrate is provided. The method involves spraying an etchant solution including NH.sub.4 OH and H.sub.2 O.sub.2, preferably in a 1:4 ratio, onto the GaAs layer as the wafer is rotated at approximately 2000 rpm. The etchant is sprayed through a plurality of spray nozzles. The process is capable of thinning a GaAs layer by about 500 .mu.m in approximately 14 to 18 minutes, depending on the etchant temperature and composition.
摘要翻译：提供了一种用于在晶片衬底的背面上稀释砷化镓（GaAs）层的方法。该方法包括当晶片以大约2000rpm旋转时，将包括NH 4 OH和H 2 O 2的蚀刻剂溶液，优选以1:4的比例喷涂到GaAs层上。蚀刻剂通过多个喷嘴喷射。该方法能够在约14至18分钟内使GaAs层减薄约500μm，这取决于蚀刻剂的温度和组成。

26. 发明授权

US5111455A Interleaved time-division multiplexor with phase-compensated frequency doublers 失效
标题翻译：具有相位补偿频率倍增器的交错时分复用器
公开(公告)号：US5111455A
公开(公告)日：1992-05-05
申请号：US572854
申请日：1990-08-24
申请人： Kevin J. Negus
发明人： Kevin J. Negus
IPC分类号： H04J3/04
CPC分类号： H04J3/047
摘要： A synchronous, interleaved, time-division M:1 multiplexor. Following an input stage of parallel synchronous latches for latching M incoming parallel data bits (where M is an integer power of two equal to or greater than four) is an intermediate stage of parallel synchronous latches. The intermediate latches are clocked with selected phases of an M-phase clock having M equally-spaced phases of a clock signal having a frequency of B/M (where B is the outgoing bit rate) to latch each bit at a time at least 2/B (i.e., two outgoing bit periods) after such bit is received from its respective input latch. A first stage of 2:1 multiplexors, following the intermediate latches and used to begin multiplexing the latched bits, are clocked with selected phases of the M-phase clock to begin multiplexing each bit at a time at least 1/B (i.e., one outgoing bit period) after such bit is received from its respective intermediate latch. Further stages of 2:1 multiplexors complete the multiplexing and are each clocked with clock signals which are successively doubled in frequency at each additional stage of 2:1 multiplexors (e.g., 2B/M, 4B/M, 8B/M, . . . ) and phase compensated so as to align the clock signals with their respective data. The phase-compensated, frequency doubling for each 2:1 multiplexor stage is done by "exclusive-ORing" pairs of quadrature clock signals from the immediately preceding 2:1 multiplexor stage.
摘要翻译：同步，交错的时分M：1多路复用器。在并行同步锁存器的输入级之后，用于锁存M个输入并行数据位（其中M是等于或大于4的2的整数幂）是并行同步锁存器的中间级。中间锁存器具有M相位时钟的选定相位的时钟，M相的时钟具有具有B / M频率（其中B是输出比特率）的时钟信号的具有M个等间隔相位的M个等时相位，以在至少2个时间锁存每个位 / B（即，两个输出位周期）之后，从其相应的输入锁存器接收该位。在中间锁存器之后并用于开始复用锁存位的第一级2：1多路复用器以M相时钟的选定相位进行计时，以便每次至少1 / B复用每个位（即一个输出比特周期）。 2：1多路复用器的进一步阶段完成了多路复用，并且每个时钟信号都是在2：1多路复用器的每个附加级（例如，2B / M，4B / M，8B / M，...，）并进行相位补偿，以便将时钟信号与它们各自的数据对准。每个2：1多路复用器级的相位补偿倍频通过“异或”来自紧接在前的2：1多路复用器级的正交时钟信号对进行。

27. 发明授权

US4975065A Microwave circuit module connector 失效
标题翻译：微波电路模块连接器
公开(公告)号：US4975065A
公开(公告)日：1990-12-04
申请号：US412651
申请日：1989-09-26
申请人： John C. Rosenberg , James P. Slupe
发明人： John C. Rosenberg , James P. Slupe
IPC分类号： H01P1/04
CPC分类号： H01P1/045
摘要： Adjacent microwave circuit modules are coaxially connected by means of insulating plugs, in which through-pins are embedded, recessed mounted in bores in the opposed walls of a pair of modules and an inter-connector made of an insulating material and containing sockets for mating with the through-pins, the inter-connector being dimensioned such that it can be inserted half way into each of the bores.
摘要翻译：相邻的微波电路模块通过绝缘插头同轴连接，其中嵌入有通孔，凹入安装在一对模块的相对壁中的孔中，以及由绝缘材料制成并包含用于与通孔，连接器的尺寸被设计成使得其可以被插入到每个孔中。

28. 发明授权

US4940949A High efficiency high isolation amplifier 失效
标题翻译：高效率高隔离放大器
公开(公告)号：US4940949A
公开(公告)日：1990-07-10
申请号：US430629
申请日：1989-11-01
申请人： Ernest D. Landi
发明人： Ernest D. Landi
IPC分类号： H03F1/22 , H03F3/30
CPC分类号： H03F3/3084 , H03F1/22
摘要： A broadband RF amplifier with high efficiency and high reverse isolation having a common emitter stage connected in a cascode configuration to a common base stage, said cascode driving the common base stage in a push-pull operation with a common collector stage.
摘要翻译：具有高效率和高反向隔离的宽带RF放大器，其具有以共源共栅配置连接到公共基极级的公共发射极级，所述共源共栅在具有公共集电极级的推挽操作中驱动公共基极级。

29. 发明授权

US4881050A Thin-film microwave filter 失效
标题翻译：薄膜微波过滤器
公开(公告)号：US4881050A
公开(公告)日：1989-11-14
申请号：US228288
申请日：1988-08-04
申请人： Daniel G. Swanson, Jr.
发明人： Daniel G. Swanson, Jr.
IPC分类号： H03H7/01
CPC分类号： H03H7/1766 , H03H7/0115 , H03H2001/0078 , H03H2001/0085
摘要： A thin-film, lumped element filter utilizing spiral inductors and capacitive pi networks is disclosed. The filter is fabricated from a planar dielectric substrate having a ground plane on one side thereof and two thin-film metal layers and an insulation layer disposed therebetween on the opposite side of the dielectric substrate. The metal and insulation layers are configured to form one or more capacitive pi networks and spiral inductors, which are electrically interconnected to form the filter.
摘要翻译：公开了一种利用螺旋电感和电容式π网络的薄膜集总元件滤波器。滤波器由平面电介质基片制成，该平面电介质基片在其一侧具有接地平面，两个薄膜金属层和设置在介质基片相对侧之间的绝缘层。金属和绝缘层被配置成形成一个或多个电容性π网络和螺旋电感器，其被电互连以形成滤波器。

30. 发明授权

US4842699A Method of selective via-hole and heat sink plating using a metal mask 失效
标题翻译：使用金属掩模的选择性通孔和散热电镀方法
公开(公告)号：US4842699A
公开(公告)日：1989-06-27
申请号：US192199
申请日：1988-05-10
申请人： Chang-Hwang Hua , Ding-Yuan S. Day , Simon S. Chan
发明人： Chang-Hwang Hua , Ding-Yuan S. Day , Simon S. Chan
IPC分类号： C25D5/02 , H01L21/768 , H01L23/48
CPC分类号： C25D5/022 , H01L21/76898 , H01L23/481 , H01L2924/0002
摘要： A method for simultaneous selective plating of viaholes and heat sinks associated with a semiconductor wafer using a metal mask and comprising the steps of:(a) coating a first side of the wafer with an insulating layer to prevent electroplating on this first side;(b) patterning on a second side of the wafer, opposite to the first side, a metal mask for defining the areas where plating should not occur;(c) forming via-holes through said wafer;(d) depositing a thin conductive film to coat the bottom and walls of the via-holes as well as areas of the second side of the wafer not covered by the metal mask; and(e) electrolytically plating the resulting wafer while ultrasonically agitating the electrolyte if necessary to ensure sufficient electrolyte transport into the via-holes for uniform plating.
摘要翻译：一种使用金属掩模同时选择性地电镀与半导体晶片相关的通孔和散热器的方法，包括以下步骤：（a）用绝缘层涂覆晶片的第一侧以防止在该第一侧上的电镀; （b）在晶片的与第一侧相对的第二面上图案化，用于限定不应发生电镀的区域的金属掩模; （c）通过所述晶片形成通孔; （d）沉积薄的导电膜以覆盖通孔的底部和壁以及未被金属掩模覆盖的晶片的第二面的区域; 和（e）如果需要的话，对所得的晶片进行电解电镀，同时超声波地搅动电解质，以确保足够的电解质输送到通孔中用于均匀的电镀。

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