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21. 发明授权

US08247300B2 Control of dopant diffusion from buried layers in bipolar integrated circuits 有权
标题翻译：控制双极集成电路中埋层的掺杂剂扩散
公开(公告)号：US08247300B2
公开(公告)日：2012-08-21
申请号：US12627794
申请日：2009-11-30
申请人： Jeffrey A. Babcock , Angelo Pinto , Manfred Schiekofer , Scott G. Balster , Gregory E. Howard , Alfred Hausler
发明人： Jeffrey A. Babcock , Angelo Pinto , Manfred Schiekofer , Scott G. Balster , Gregory E. Howard , Alfred Hausler
IPC分类号： H01L21/8222
CPC分类号： H01L29/66265 , H01L21/82285 , H01L29/66242 , H01L29/7317 , H01L29/7378
摘要： An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors (30, 50, 60), each having a buried collector region (26′). A carbon-bearing diffusion barrier (28c) is disposed over the buried collector region (26′), to inhibit the diffusion of dopant from the buried collector region (26′) into the overlying epitaxial layer (28). The diffusion barrier (28c) may be formed by incorporating a carbon source into the epitaxial formation of the overlying layer (28), or by ion implantation. In the case of ion implantation of carbon or SiGeC, masks (52, 62) may be used to define the locations of the buried collector regions (26′) that are to receive the carbon; for example, portions underlying eventual collector contacts (33, 44c) may be masked from the carbon implant so that dopant from the buried collector region (26′) can diffuse upward to meet the contact (33). MOS transistors (70, 80) including the diffusion barrier (28) are also disclosed.
摘要翻译：公开了一种集成电路及其制造方法。集成电路包括垂直双极晶体管（30,50,60），每个具有一个埋设集电极区域（26'）。含碳扩散阻挡层（28c）设置在掩埋集电极区域（26'）之上，以阻止掺杂剂从掩埋的集电极区域（26'）扩散到上覆的外延层（28）中。扩散阻挡层（28c）可以通过将碳源引入上覆层（28）的外延层中，或通过离子注入形成。在碳或SiGeC的离子注入的情况下，可以使用掩模（52,62）来限定待接收碳的掩埋收集器区域（26'）的位置; 例如，最终的集电极触点（33,44c）下面的部分可以从碳注入掩模，使得来自掩埋的集电极区域（26'）的掺杂剂可向上扩散以满足触点（33）。还公开了包括扩散阻挡层（28）的MOS晶体管（70,80）。

22. 发明申请

US20100032731A1 SCHOTTKY JUNCTION-FIELD-EFFECT-TRANSISTOR (JFET) STRUCTURES AND METHODS OF FORMING JFET STRUCTURES 有权
标题翻译：肖特基结场效应晶体管（JFET）结构和形成JFET结构的方法
公开(公告)号：US20100032731A1
公开(公告)日：2010-02-11
申请号：US12498141
申请日：2009-07-06
申请人： Jeffrey A. Babcock , Natalia Lavrovskaya , Saurabh Desai , Alexei Sadovnikov
发明人： Jeffrey A. Babcock , Natalia Lavrovskaya , Saurabh Desai , Alexei Sadovnikov
IPC分类号： H01L29/80
CPC分类号： H01L27/095 , H01L27/0207 , H01L29/1029 , H01L29/1058 , H01L29/808 , H01L29/812
摘要： In accordance with an aspect of the invention, A Schottky junction field effect transistor (JFET) is created using cobalt silicide, or other Schottky material, to form the gate contact of the JFET. The structural concepts can also be applied to a standard JFET that uses N− type or P− type dopants to form the gate of the JFET. In addition, the structures allow for an improved JFET linkup with buried linkup contacts allowing improved noise and reliability performance for both conventional diffusion (N− and P− channel) JFET structures and for Schottky JFET structures. In accordance with another aspect of the invention, the gate poly, as found in a standard CMOS or BiCMOS process flow, is used to perform the linkup between the source and the junction gate and/or between the drain and the junction gate of a junction filed effect transistor (JFET). Use of a bias on the gate linkup of the JFET allows an additional tuning knob for the JFET that can be optimized to trade off breakdown characteristics with reduced on resistance. In accordance with yet another aspect of the invention, a patterned buried layer is used to form the back gate control for a junction field effect transistor (JFET). The structure allows a layout or buried layer pattern change to adjust the pinch-off voltage of the JFET structure. Vertical and lateral diffusion of the buried layer is used to adjust the JFET operating parameters with a simple change in the buried layer patterns. In addition, the structures allow for increased breakdown voltage by leveraging charge sharing concepts and improving channel confinement for power JFET structures. These concepts can also be applied to both N− channel and P− channel diffusion JFETs and to Schottky JFET structures.
摘要翻译：根据本发明的一个方面，使用硅化钴或其它肖特基材料制造肖特基结场效应晶体管（JFET），以形成JFET的栅极接触。结构概念也可以应用于使用N型或P-型掺杂剂形成JFET栅极的标准JFET。此外，这些结构允许改进的JFET与嵌入式连接触点连接，从而可以改善常规扩散（N和P沟道）JFET结构和肖特基JFET结构的噪声和可靠性性能。根据本发明的另一方面，如标准CMOS或BiCMOS工艺流程中所发现的栅极聚合体用于执行源极和结栅极之间和/或在结的漏极和结栅之间的连接场效应晶体管（JFET）。在JFET的栅极连接上使用偏置可以为JFET提供一个额外的调谐旋钮，该调谐旋钮可以优化，以降低导通电阻的击穿特性。根据本发明的另一方面，图案化掩埋层用于形成结型场效应晶体管（JFET）的背栅极控制。该结构允许布局或掩埋层图案改变以调节JFET结构的夹断电压。掩埋层的垂直和横向扩散用于通过掩埋层图案的简单变化来调节JFET操作参数。此外，这些结构允许通过利用电荷共享概念并改善功率JFET结构的通道限制来增加击穿电压。这些概念也可以应用于N沟道和P沟道扩散JFET以及肖特基JFET结构。

23. 发明授权

US07422972B2 On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits 有权
标题翻译：片上加热用于多晶硅和多晶硅 - 锗 - 锗电阻器的电气修整和用于集成电路的电可编程保险丝
公开(公告)号：US07422972B2
公开(公告)日：2008-09-09
申请号：US11182981
申请日：2005-07-15
申请人： Jeffrey A. Babcock , Angelo Pinto , Gregory E. Howard , Philipp Steinmann , Scott Balster
发明人： Jeffrey A. Babcock , Angelo Pinto , Gregory E. Howard , Philipp Steinmann , Scott Balster
IPC分类号： H01L21/44
CPC分类号： H01L21/76886 , H01L21/76888 , H01L23/345 , H01L23/5256 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit programmable structure (60) is formed for use a trim resistor and/or a programmable fuse. The programmable structure comprises placing heating elements (70) in close proximity to the programmable structure (60) to heat the programmable structure (60) during programming.
摘要翻译：形成用于使用微调电阻器和/或可编程保险丝的集成电路可编程结构（60）。可编程结构包括将加热元件（70）放置在可编程结构（60）附近以在编程期间加热可编程结构（60）。

24. 发明授权

US07164186B2 Structure of semiconductor device with sinker contact region 有权
标题翻译：具有沉降片接触区域的半导体器件的结构
公开(公告)号：US07164186B2
公开(公告)日：2007-01-16
申请号：US10939221
申请日：2004-09-10
申请人： Angelo Pinto , Jeffrey A. Babcock , Michael Schober , Scott G. Balster , Christoph Dirnecker
发明人： Angelo Pinto , Jeffrey A. Babcock , Michael Schober , Scott G. Balster , Christoph Dirnecker
IPC分类号： H01L29/70
CPC分类号： H01L29/66272 , H01L29/41708
摘要： A method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer. A first isolation structure is formed adjacent at least a portion of the buried layer. A second isolation structure is formed adjacent at least a portion of the active region. A base layer is formed adjacent at least a portion of the active region. A dielectric layer is formed adjacent at least a portion of the base layer, and then at least part of the dielectric layer is removed at an emitter contact location and at a sinker contact location. An emitter structure is formed at the emitter contact location. Forming the emitter structure includes etching the semiconductor device at the sinker contact location to form a sinker contact region. The sinker contact region has a first depth. The method may also include forming a gate structure. Forming the gate structure includes etching the sinker contact region thereby increasing the first depth of the sinker contact region to a second depth.
摘要翻译：半导体器件的制造方法包括形成半导体衬底的掩埋层。在掩埋层的至少一部分附近形成有源区。在掩埋层的至少一部分附近形成第一隔离结构。在活性区域的至少一部分附近形成第二隔离结构。在活性区域的至少一部分附近形成基底层。在基底层的至少一部分附近形成电介质层，然后在发射极接触位置和沉降片接触位置移除介电层的至少一部分。发射极结构形成在发射极接触位置。形成发射极结构包括在沉降片接触位置蚀刻半导体器件以形成沉降片接触区域。沉降片接触区域具有第一深度。该方法还可以包括形成栅极结构。形成栅极结构包括蚀刻沉降片接触区域，从而将沉降片接触区域的第一深度增加到第二深度。

25. 发明授权

US07064399B2 Advanced CMOS using super steep retrograde wells 有权
公开(公告)号：US07064399B2
公开(公告)日：2006-06-20
申请号：US09948856
申请日：2001-09-07
申请人： Jeffrey A. Babcock , Angelo Pinto , Scott Balster , Alfred Haeusler , Gregory E. Howard
发明人： Jeffrey A. Babcock , Angelo Pinto , Scott Balster , Alfred Haeusler , Gregory E. Howard
IPC分类号： H01L31/119
CPC分类号： H01L29/66659 , H01L21/26506 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/823892 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/36 , H01L29/78612 , H01L29/78654
摘要： The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).

26. 发明授权

US06838348B2 Integrated process for high voltage and high performance silicon-on-insulator bipolar devices 有权
标题翻译：用于高电压和高性能绝缘体上的双极器件的集成工艺
公开(公告)号：US06838348B2
公开(公告)日：2005-01-04
申请号：US10844144
申请日：2004-05-12
申请人： Jeffrey A. Babcock , Gregory E. Howard , Angelo Pinto , Phillipp Steinmann , Scott G. Balster
发明人： Jeffrey A. Babcock , Gregory E. Howard , Angelo Pinto , Phillipp Steinmann , Scott G. Balster
IPC分类号： H01L21/331 , H01L21/84 , H01L27/082 , H01L27/12 , H01L29/06 , H01L29/08 , H01L29/73
CPC分类号： H01L29/66265 , H01L21/84 , H01L27/0826 , H01L27/1203 , H01L29/0692 , H01L29/0821 , H01L29/7317
摘要： High-voltage bipolar transistors (30, 60) in silicon-on-insulator (SOI) integrated circuits are disclosed. In one disclosed embodiment, an collector region (28) is formed in epitaxial silicon (24, 25) disposed over a buried insulator layer (22). A base region (32) and emitter (36) are disposed over the collector region (28). Buried collector region (31) are disposed in the epitaxial silicon (24) away from the base region (32). The transistor may be arranged in a rectangular fashion, as conventional, or alternatively by forming an annular buried collector region (31). According to another disclosed embodiment, a high voltage transistor (60) includes a central isolation structure (62), so that the base region (65) and emitter region (66) are ring-shaped to provide improved performance. A process for fabricating the high voltage transistor (30, 60) simultaneously with a high performance transistor (40) is also disclosed.
摘要翻译：公开了绝缘体上硅（SOI）集成电路中的高电压双极晶体管（30,60）。在一个公开的实施例中，集电极区域（28）形成在设置在掩埋绝缘体层（22）上的外延硅（24,25）中。基极区域（32）和发射极（36）设置在集电极区域（28）的上方。掩埋集电极区域（31）设置在远离基极区域（32）的外延硅（24）中。晶体管可以以常规方式布置成矩形方式，或者通过形成环形埋层集电极区域（31）来布置。根据另一公开的实施例，高压晶体管（60）包括中心隔离结构（62），使得基极区域（65）和发射极区域（66）是环形的，以提供改进的性能。还公开了与高性能晶体管（40）同时制造高压晶体管（30,60）的工艺。

27. 发明授权

US06774455B2 Semiconductor device with a collector contact in a depressed well-region 有权
标题翻译：半导体器件在凹陷阱区域具有集电极接触
公开(公告)号：US06774455B2
公开(公告)日：2004-08-10
申请号：US10262206
申请日：2002-09-30
申请人： Jeffrey A. Babcock , Christoph Dirnecker , Angelo Pinto , Scott G. Balster , Michael Schober , Alfred Haeusler
发明人： Jeffrey A. Babcock , Christoph Dirnecker , Angelo Pinto , Scott G. Balster , Michael Schober , Alfred Haeusler
IPC分类号： H01L29737
CPC分类号： H01L29/66265 , H01L29/41708 , H01L29/66272 , H01L29/7317 , H01L29/732
摘要： A method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer. At least part of the active region is removed to form a shallow trench opening. A dielectric layer is formed proximate the active region at least partially within the shallow trench opening. At least part of the dielectric layer is removed to form a collector contact region. A collector contact may be formed at the collector contact region. The collector contact may be operable to electrically contact the buried layer.
摘要翻译：半导体器件的制造方法包括形成半导体衬底的掩埋层。在掩埋层的至少一部分附近形成有源区。移除活性区域的至少一部分以形成浅沟槽开口。在浅沟槽开口内至少部分地在有源区域附近形成电介质层。去除介电层的至少一部分以形成集电极接触区域。集电极触点可以在集电极接触区域形成。集电极触点可操作以电接触埋层。

28. 发明授权

US08669157B2 Non-volatile memory cell having a heating element and a substrate-based control gate 有权
标题翻译：具有加热元件和基于基板的控制栅极的非易失性存储单元
公开(公告)号：US08669157B2
公开(公告)日：2014-03-11
申请号：US13477019
申请日：2012-05-21
申请人： Jeffrey A. Babcock , Yuri Mirgorodski , Natalia Lavrovskaya , Saurabh Desai
发明人： Jeffrey A. Babcock , Yuri Mirgorodski , Natalia Lavrovskaya , Saurabh Desai
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L27/11521 , H01L27/11558 , H01L29/66825 , H01L29/7841 , H01L29/7881
摘要： The number of times that a non-volatile memory (NVM) can be programmed and erased is substantially increased by utilizing a localized heating element that anneals the oxide that is damaged by tunneling charge carriers when the NVM is programmed and erased. The program and erase voltages are also reduced when heat from the heating element is applied prior to programming and erasing.
摘要翻译：可以通过利用局部加热元件来使得非易失性存储器（NVM）被编程和擦除的次数大大增加，所述局部加热元件在NVM被编程和擦除时使隧道电荷载体损坏的氧化物退火。在编程和擦除之前，加热元件的热量时，编程和擦除电压也会降低。

29. 发明申请

US20120060587A1 Gas Detector that Utilizes an Electric Field to Assist in the Collection and Removal of Gas Molecules 有权
标题翻译：气体探测器利用电场来辅助气体分子的收集和去除
公开(公告)号：US20120060587A1
公开(公告)日：2012-03-15
申请号：US12880464
申请日：2010-09-13
申请人： Jeffrey A. Babcock , Peter J. Hopper , Yuri Mirgorodski
发明人： Jeffrey A. Babcock , Peter J. Hopper , Yuri Mirgorodski
IPC分类号： G01N7/00 , H01L21/30
CPC分类号： G01N27/4141
摘要： A semiconductor-based gas detector enhances the collection of gas molecules and also provides a self-contained means for removing collected gas molecules by utilizing one or more electric fields to transport the gas molecules to and away from a metallic material that has a high permeability to the gas molecules.
摘要翻译：基于半导体的气体检测器增强了气体分子的收集，并且还提供了一种独立的装置，用于通过利用一个或多个电场来将气体分子输送到和远离具有高渗透性的金属材料气体分子。

30. 发明申请

US20110111553A1 ADVANCED CMOS USING SUPER STEEP RETROGRADE WELLS 有权
标题翻译：高级CMOS使用超级梯形变压器
公开(公告)号：US20110111553A1
公开(公告)日：2011-05-12
申请号：US13006224
申请日：2011-01-13
申请人： Jeffrey A. Babcock , Angelo Pinto , Scott Balster , Alfred Haeusler , Gregory E. Howard
发明人： Jeffrey A. Babcock , Angelo Pinto , Scott Balster , Alfred Haeusler , Gregory E. Howard
IPC分类号： H01L51/40
CPC分类号： H01L29/66659 , H01L21/26506 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/823892 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/36 , H01L29/78612 , H01L29/78654
摘要： The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
摘要翻译：本发明是一种用于在MOS晶体管结构中形成超陡掺杂分布的方法。该方法包括在栅极电介质（50）下面形成含碳层（110），并在MOS晶体管的源极和漏极区域（80）形成。含碳层（110）将防止掺杂剂扩散到栅极电介质层（50）正下方的区域（40）中。

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