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21. 发明授权

US06789248B1 Method and apparatus to perform resistance and capacitance (RC) parameter customization for better timing closure results in physical synthesis and optimization 有权
标题翻译：执行电阻和电容（RC）参数定制以更好的时序闭合的方法和装置导致物理合成和优化
公开(公告)号：US06789248B1
公开(公告)日：2004-09-07
申请号：US10178401
申请日：2002-06-24
申请人： Lee-Chung Lu , Cliff Hou , Chia-Lin Cheng , Chung-Hsing Wang , Hsing-Chien Huang , Yee-Wen Chen , Tsui-Ping Wang
发明人： Lee-Chung Lu , Cliff Hou , Chia-Lin Cheng , Chung-Hsing Wang , Hsing-Chien Huang , Yee-Wen Chen , Tsui-Ping Wang
IPC分类号： G06F1750
CPC分类号： G06F17/5068
摘要： A method and system for the design of an electronic device adjusts the resistance and capacitance values employed in preliminary timing analysis during physical synthesis of the electronic device. The physical synthesis uses resistance and capacitance unit values to determine the listing of the component circuits. The resistance and capacitance unit values are calibrated by preliminarily placing the initially synthesized component circuits to create a listing describing physical locations of the component circuits within the electronic device. A preliminary routing of the interconnections is performed to create a listing describing a network of physical wire segments that form each interconnection of the component circuits. A timing analysis of the electronic device determines the delay created by the component circuit and the networks of physical wire segments. The time delay resulting from the physical interconnects is extracted from the timing analysis of the electronic device and from the timing estimate performed during the physical synthesis. The time delay of the physical interconnection from the timing analysis and the timing estimate performed during the physical synthesis is then compared. The resistance and capacitance unit values used during the timing synthesis are then adjusted. The calibration is repeatedly executed until time delay of the physical interconnection from the timing analysis and the timing estimate performed during the physical synthesis are correlated.
摘要翻译：用于设计电子设备的方法和系统调节在电子设备的物理合成期间的初步时序分析中使用的电阻和电容值。物理合成使用电阻和电容单位值来确定元件电路的列表。电阻和电容单位值通过预先放置最初合成的组件电路来校准，以创建描述电子设备内的组件电路的物理位置的列表。执行互连的初步路由以创建描述形成组件电路的每个互连的物理线段的网络的列表。电子设备的定时分析确定由组件电路和物理线段网络产生的延迟。从物理互连产生的时间延迟从电子设备的定时分析以及在物理合成期间执行的定时估计提取。然后对来自定时分析的物理互连的时间延迟和在物理合成期间执行的定时估计进行比较。然后调整在定时合成期间使用的电阻和电容单位值。重复执行校准，直到来自定时分析的物理互连的时间延迟和在物理合成期间执行的定时估计相关。

22. 发明授权

US09672315B2 Optimization for circuit migration 有权
公开(公告)号：US09672315B2
公开(公告)日：2017-06-06
申请号：US12846594
申请日：2010-07-29
申请人： Lee-Chung Lu , Yi-Kan Cheng , Chung-Hsing Wang , Chen-Fu “Alex” Huang , Hsiao-Shu Chao , Chin-Yu Chiang , Ho Che Yu , Chih Sheng Tsai , Shu Yi Ying
发明人： Lee-Chung Lu , Yi-Kan Cheng , Chung-Hsing Wang , Chen-Fu “Alex” Huang , Hsiao-Shu Chao , Chin-Yu Chiang , Ho Che Yu , Chih Sheng Tsai , Shu Yi Ying
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/505 , G06F17/5068 , G06F17/5072
摘要： An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist.

23. 发明授权

US09608604B2 Voltage level shifter with single well voltage 有权
公开(公告)号：US09608604B2
公开(公告)日：2017-03-28
申请号：US11639006
申请日：2006-12-14
申请人： Lee-Chung Lu , Chung-Hsing Wang , Chun-Hui Tai , Li-Chun Tien , Shun-Li Chen
发明人： Lee-Chung Lu , Chung-Hsing Wang , Chun-Hui Tai , Li-Chun Tien , Shun-Li Chen
IPC分类号： H03L5/00 , H03K3/356
CPC分类号： H03K3/35613
摘要： This invention discloses a voltage level shifter, which comprises a first P-type metal-oxide-semiconductor (PMOS) transistor having a gate, a source and a bulk coupled to an input terminal, a first positive voltage power supply and a second positive voltage power supply, respectively, and a second PMOS transistor having a source, a drain and a bulk coupled to a third positive voltage power supply, an output node and the second positive voltage power supply, respectively, wherein the first and second PMOS transistors are formed in a single Nwell.

24. 发明授权

US08418117B2 Chip-level ECO shrink 有权
标题翻译：芯片级ECO收缩
公开(公告)号：US08418117B2
公开(公告)日：2013-04-09
申请号：US12831982
申请日：2010-07-07
申请人： Huang-Yu Chen , Ho Che Yu , Chung-Hsing Wang , Hsiao-Shu Chao , Yi-Kan Cheng , Lee-Chung Lu
发明人： Huang-Yu Chen , Ho Che Yu , Chung-Hsing Wang , Hsiao-Shu Chao , Yi-Kan Cheng , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L27/0207
摘要： In a method of forming an integrated circuit, a layout of a chip representation including a first intellectual property (IP) is provided. Cut lines that overlap, and extend out from, edges of the first IP, are generated. The cut lines divide the chip representation into a plurality of circuit regions. The plurality of circuit regions are shifted outward with relative to a position of the first IP to generate a space. The first IP is blown out into the space to generate a blown IP. A direct shrink is then performed.
摘要翻译：在形成集成电路的方法中，提供包括第一知识产权（IP）的芯片表示的布局。生成与第一个IP重叠并从第一个IP边缘延伸出来的切割线。切割线将芯片表示划分成多个电路区域。多个电路区域相对于第一IP的位置向外偏移以产生空间。第一个IP被吹入空间，产生一个IP地址。然后执行直接收缩。

25. 发明申请

US20110035715A1 SYSTEM AND METHOD FOR ON-CHIP-VARIATION ANALYSIS 有权
标题翻译：用于片上变化分析的系统和方法
公开(公告)号：US20110035715A1
公开(公告)日：2011-02-10
申请号：US12538507
申请日：2009-08-10
申请人： Lee-Chung Lu , Chung-Hsing Wang , Yuan-Te Hou
发明人： Lee-Chung Lu , Chung-Hsing Wang , Yuan-Te Hou
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： Apparatus is provided for performing timing analysis on a circuit. A first storage device portion stores a state dependent stage weight for each of a rising time arc and a falling time arc of each of a plurality of cells in a cell library. An adder is provided for calculating a sum of the state dependent stage weights for each of the cells that are included in a circuit path. A second storage device portion stores a table containing on chip variation (OCV) derating factors. The table is indexed by values of the sum. A total path delay is calculated for the circuit path, based on the OCV derating factor corresponding to the sum of the state dependent stage weights for the cells in the circuit path.
摘要翻译：提供了一种用于在电路上执行定时分析的装置。第一存储设备部分存储单元库中的多个单元中的每一个的上升时间弧和下降时间弧中的每一个的状态依赖级加权。提供一个加法器，用于计算包括在电路路径中的每个单元格的状态依赖级加权之和。第二存储设备部分存储包含片上变化（OCV）降额因子的表。该表由值的值索引。基于对应于电路路径中的单元的状态依赖级加权之和的OCV降额因子，计算电路路径的总路径延迟。

26. 发明申请

US20100174933A1 System and Method for Reducing Processor Power Consumption 有权
标题翻译：降低处理器功耗的系统和方法
公开(公告)号：US20100174933A1
公开(公告)日：2010-07-08
申请号：US12619428
申请日：2009-11-16
申请人： Lee-Chung Lu , Chung-Hsing Wang , Myron Shak , Wei-Pin Changchien , Kuo-Yin Chen , Chi Wei Hu , Kevin Hung , Wu-An Kuo
发明人： Lee-Chung Lu , Chung-Hsing Wang , Myron Shak , Wei-Pin Changchien , Kuo-Yin Chen , Chi Wei Hu , Kevin Hung , Wu-An Kuo
IPC分类号： G06F1/00
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/3237 , Y02D10/128 , Y02D10/171 , Y02D50/20
摘要： A system and method for reducing active power in processors is disclosed. A method embodiment comprises the steps of determining when a particular logic block is inactive, determining the powered state of the particular logic block, isolating the particular logic block from a main processor core, and powering off the particular logic block. When the system needs the particular logic block, the method further comprises reactivating the block. A system embodiment comprises software and a processor coupled to a clock control module, an isolation control module and a header/footer module, operable to isolate a particular logic block and power off a particular logic block, thereby reducing power. Another embodiment comprises a logic module coupled to a clock by a clock gating module, an isolation module for isolating the logic module, a header/footer module for disabling power to the logic module, and a power and clock gating control module for controlling the clock gating module and the header/footer module.
摘要翻译：公开了一种用于减少处理器中的有功功率的系统和方法。方法实施例包括以下步骤：确定特定逻辑块何时不活动，确定特定逻辑块的供电状态，将特定逻辑块与主处理器内核隔离，以及断开特定逻辑块。当系统需要特定逻辑块时，该方法还包括重新激活该块。系统实施例包括耦合到时钟控制模块，隔离控制模块和报头/页脚模块的软件和处理器，其可操作以隔离特定逻辑块并关闭特定逻辑块，从而降低功率。另一个实施例包括通过时钟门控模块耦合到时钟的逻辑模块，用于隔离逻辑模块的隔离模块，用于禁止对逻辑模块供电的报头/页脚模块，以及用于控制时钟的电源和时钟门控控制模块门控模块和页眉/页脚模块。

27. 发明申请

US20080115024A1 System and method for testing state retention circuits 有权
标题翻译：用于测试状态保持电路的系统和方法
公开(公告)号：US20080115024A1
公开(公告)日：2008-05-15
申请号：US11595143
申请日：2006-11-10
申请人： Chung-Hsing Wang , Lee-Chung Lu
发明人： Chung-Hsing Wang , Lee-Chung Lu
IPC分类号： G06F11/25 , G06F11/27
CPC分类号： G01R31/318544 , G01R31/318536
摘要： This invention discloses a system and method for testing a plurality of state retention circuits in an integrated circuit (IC) chip, that comprises a built-in test circuit configured to invoke a clock, a save and a restore signal, and a plurality of serially connected data latches receiving the clock, save and restore signals, wherein each data latch employs one of the plurality of state retention circuits, wherein the plurality of data latches save their existing data in their corresponding state retention circuits upon an assertion of the save signal, restore the data from the plurality of state retention circuits back to their corresponding data latches upon an assertion of the restore signal, and shifting the existing data along the series of the data latches one latch a cycle of the clock signal.
摘要翻译：本发明公开了一种用于测试集成电路（IC）芯片中的多个状态保持电路的系统和方法，该系统和方法包括被配置为调用时钟，保存和还原信号以及多个串行的内置测试电路接收时钟的连接数据锁存器，保存和恢复信号，其中每个数据锁存器采用多个状态保持电路中的一个，其中多个数据锁存器在保存信号被断言时将其现有数据保存在其相应的状态保持电路中，在断言恢复信号时，将数据从多个状态保持电路恢复回相应的数据锁存器，并且沿数据锁存器序列移位现有数据一个锁存器是时钟信号的周期。

28. 发明申请

US20060225007A1 Antenna effect prevention by model extraction in a circuit design for advanced processes 审中-公开
标题翻译：通过模型提取在电路设计中进行高级处理的天线效应预防
公开(公告)号：US20060225007A1
公开(公告)日：2006-10-05
申请号：US11100105
申请日：2005-04-05
申请人： Chung-Hsing Wang , Shou-Yi Lee , Lee-Chung Lu
发明人： Chung-Hsing Wang , Shou-Yi Lee , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method is disclosed for determining an antenna ratio for an interconnect in a circuit. The interconnect may be routed through one or more connection layers and may be electrically coupled to one or more gate oxide areas. A cumulative antenna ratio for all components on each connection layer is determined by considering an antenna effect caused by each component on a predetermined connection layer with regard to the gate oxide areas coupled thereto and any components on one or more connection layers coupled between the component of the present connection layer and the gate oxide areas. In the same fashion, a top layer cumulative antenna ratio for the interconnect is determined based on the cumulative antenna ratios for the connection layers below the top layer.
摘要翻译：公开了一种用于确定电路中互连的天线比率的方法。互连可以被路由穿过一个或多个连接层并且可以电耦合到一个或多个栅极氧化物区域。通过考虑由耦合到其上的栅极氧化物区域的预定连接层上的每个分量引起的天线效应，以及耦合在一个或多个连接层上的组件之间的任何组件来确定每个连接层上的所有组件的累积天线比本连接层和栅极氧化物区域。以相同的方式，基于顶层下面的连接层的累积天线比来确定互连的顶层累积天线比。

29. 发明授权

US09311440B2 System and method of electromigration avoidance for automatic place-and-route 有权
标题翻译：自动放置路由的电迁移避免系统和方法
公开(公告)号：US09311440B2
公开(公告)日：2016-04-12
申请号：US13468055
申请日：2012-05-10
申请人： Jerry Kao , King-Ho Tam , Meng-Xiang Lee , Li-Chung Hsu , Chi-Yeh Yu , Chung-Min Fu , Chung-Hsing Wang
发明人： Jerry Kao , King-Ho Tam , Meng-Xiang Lee , Li-Chung Hsu , Chi-Yeh Yu , Chung-Min Fu , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077 , G06F2217/76
摘要： A method includes identifying at least one local power segment of a circuit, estimating at least one performance parameter of the at least one power segment based on a computer-based simulation of the circuit, and changing a design of the circuit based on at least one electromigration avoidance strategy if the at least one parameter is greater than or equal to a threshold value. A data file representing the circuit is stored if the at least one parameter is less than the threshold value.
摘要翻译：一种方法包括识别电路的至少一个局部电力部分，基于电路的基于计算机的仿真来估计所述至少一个电力部分的至少一个性能参数，以及基于至少一个电路来改变所述电路的设计如果至少一个参数大于或等于阈值，则电迁移避免策略。如果至少一个参数小于阈值，则存储表示电路的数据文件。

30. 发明授权

US08816486B2 Pad structure for 3D integrated circuit 有权
标题翻译：三维集成电路的垫结构
公开(公告)号：US08816486B2
公开(公告)日：2014-08-26
申请号：US12119255
申请日：2008-05-12
申请人： Chih-Sheng Tsai , Chung-Hsing Wang
发明人： Chih-Sheng Tsai , Chung-Hsing Wang
IPC分类号： H01L23/02 , H01L23/48
CPC分类号： H01L25/0657 , H01L23/481 , H01L24/05 , H01L24/12 , H01L2224/0401 , H01L2224/05093 , H01L2224/05096 , H01L2224/0558 , H01L2224/05624 , H01L2224/1134 , H01L2224/13025 , H01L2224/13099 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00013 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/01087 , H01L2924/14 , H01L2924/00014
摘要： An I/O pad structure in an integrated circuit (IC) comprises a first vertical region in the IC including a top metal layer and one or more semiconductor devices formed thereunder, the top metal layer in the first vertical region serving as a first pad, the semiconductor devices being electrically connected to the first pad, and a second vertical region in the IC next to the first vertical region including the top metal layer and one or more through-silicon-vias (TSVs) formed thereunder, the top metal layer in the second vertical region serving as a second pad, and no semiconductor devices being formed beneath the second pad, the TSVs being electrically connected to the second pad, wherein the first and the second pad are electrically connected through at least one metal layer.
摘要翻译：集成电路（IC）中的I / O焊盘结构包括IC中的第一垂直区域，其包括顶部金属层和形成在其上的一个或多个半导体器件，第一垂直区域中的顶部金属层用作第一焊盘，所述半导体器件电连接到所述第一焊盘，并且所述IC中的第二垂直区域位于包括顶部金属层的第一垂直区域和在其之下形成的一个或多个穿硅通孔（TSV），所述顶部金属层所述第二垂直区域用作第二焊盘，并且没有半导体器件形成在所述第二焊盘下方，所述TSV电连接到所述第二焊盘，其中所述第一焊盘和所述第二焊盘通过至少一个金属层电连接。

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