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21. 发明授权

US06518835B2 Semiconductor integrated circuit device having an optimal circuit layout to ensure stabilization of internal source voltages without lowering circuit functions and/or operating performance 有权
标题翻译：具有最佳电路布局以确保内部源电压的稳定而不降低电路功能和/或操作性能的半导体集成电路器件
公开(公告)号：US06518835B2
公开(公告)日：2003-02-11
申请号：US10142897
申请日：2002-05-13
申请人： Yoshiro Riho , Kiyoshi Nakai , Hidekazu Egawa , Yukihide Suzuki , Isamu Fujii
发明人： Yoshiro Riho , Kiyoshi Nakai , Hidekazu Egawa , Yukihide Suzuki , Isamu Fujii
IPC分类号： H01L2500
CPC分类号： H01L23/5222 , H01L23/50 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor integrated circuit device which comprises a first interconnect channel including a plurality of second-layer metal interconnect layers extended in a first direction over a semiconductor chip, a second interconnect channel including a plurality of, third-layer metal interconnect layers extended in a second direction perpendicular to the first direction, an internal power supply circuit which receives a source voltage supplied from an external terminal and generates a voltage different from the source voltage, and which is provided with stabilizing capacitors, a large part of the stabilizing capacitors are formed in an area in which the second- and third-layer metal interconnect lines intersect each other.
摘要翻译：一种半导体集成电路器件，包括：第一互连沟道，包括在半导体芯片上沿第一方向延伸的多个第二层金属互连层;第二互连沟道，包括多个第三层金属互连层，第二方向垂直于第一方向;内部电源电路，其接收从外部端子提供的源极电压并产生与源极电压不同的电压，并且设置有稳定电容器，形成大部分稳定化电容器在第二和第三层金属互连线彼此相交的区域中。

22. 发明授权

US06411160B1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06411160B1
公开(公告)日：2002-06-25
申请号：US09376470
申请日：1999-08-18
申请人： Yoshiro Riho , Kiyoshi Nakai , Hidekazu Egawa , Yukihide Suzuki , Isamu Fujii
发明人： Yoshiro Riho , Kiyoshi Nakai , Hidekazu Egawa , Yukihide Suzuki , Isamu Fujii
IPC分类号： H01L2500
CPC分类号： H01L23/5222 , H01L23/50 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor integrated circuit device which comprises a first interconnect channel including a plurality of second-layer metal interconnect layers extended in a first direction over a semiconductor chip, a second interconnect channel including a plurality of third-layer metal interconnect layers extended in a second direction perpendicular to the first direction, an internal power supply circuit which receives a source voltage supplied from an external terminal and generates a voltage different from the source voltage, and which is provided with stabilizing capacitors, a large part of the stabilizing capacitors are in an area in which the second- and third-layer metal interconnect lines intersect each other.
摘要翻译：在一种半导体集成电路器件中，包括第一互连通道，第一互连通道包括在半导体芯片上沿第一方向延伸的多个第二层金属互连层，第二互连通道，包括在第二互连层中延伸的多个第三层金属互连层内部电源电路，其接收从外部端子提供的源极电压，并产生与源极电压不同的电压，并且设置有稳定电容器，大部分稳定化电容器处于第二和第三层金属互连线彼此相交的区域。

23. 发明授权

US5625234A Semiconductor memory device with bit line and select line arrangement maintaining parasitic capacitance in equilibrium 失效
标题翻译：具有位线和选择线路布置的半导体存储器件使寄生电容保持平衡
公开(公告)号：US5625234A
公开(公告)日：1997-04-29
申请号：US292480
申请日：1994-08-18
申请人： Yukihide Suzuki , Hiroyuki Yoshida
发明人： Yukihide Suzuki , Hiroyuki Yoshida
IPC分类号： H01L27/10 , G11C7/06 , G11C11/408 , G11C11/4091 , G11C11/4097 , H01L21/8242 , H01L27/108 , G11C7/02 , G11C5/06
CPC分类号： G11C7/06 , G11C11/4087 , G11C11/4091 , G11C11/4097
摘要： A semiconductor memory device in which sensing of the memory information stored in a memory cell can be carried out stably, and reliably by equilibrating a parasitic capacitance existing between a select line and its adjacent bit line pair. Each Y select line YS is arranged at a position where it uniformly spans over both members of a bit line pair which extend straight in parallel to each other without the twist part TW within an area of four bit line pairs (eight bit lines or auxiliary bit lines) that are simultaneously sensed. Within an area of the first set of bit line pairs (BL0,BL0-)-(BL3,BL3-), in addition to the bit line pair (BL1,BL1-), the line pairs (BL0,BL0-) and (BL2,BL2-) with the twist part TW are substantially capacitance-coupled with the Y select line YS0. In these bit line pairs, the parasitic capacitance for the Y select line YS0 is at equilibrium between a bit line and an auxiliary bit line.
摘要翻译：可以通过平衡存在于选择线与其相邻位线对之间的寄生电容来稳定地且可靠地执行存储在存储单元中的存储器信息的感测的半导体存储器件。每个Y选择线YS被布置在其均匀地跨越位线对的两个部件的位置上，这两个部件在四位位线对（八位线或辅助位置）的区域内彼此并行延伸，而没有扭转部分TW 线），同时感测。除了位线对（BL1，BL1-）之外，在第一组位线对（BL0，BL0 - ） - （BL3，BL3-）的区域内，线对（BL0，BL0-）和（ BL2，BL2-）与扭转部分TW基本上与Y选择线YS0电容耦合。在这些位线对中，Y选择线YS0的寄生电容在位线和辅助位线之间处于平衡状态。

24. 发明授权

US5615156A Semiconductor memory device having plural memory mats with centrally located reserve bit or word lines 失效
标题翻译：半导体存储器件具有多个具有中心位置的保留位或字线的存储垫
公开(公告)号：US5615156A
公开(公告)日：1997-03-25
申请号：US250130
申请日：1994-05-27
申请人： Hiroyuki Yoshida , Takashi Inui , Shigeki Numaga , Kiyoshi Nakai , Yukihide Suzuki
发明人： Hiroyuki Yoshida , Takashi Inui , Shigeki Numaga , Kiyoshi Nakai , Yukihide Suzuki
IPC分类号： G11C11/401 , G11C29/00 , G11C29/04 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： G11C29/80
摘要： A semiconductor memory device having reserve bit lines or word lines for replacing defective bit lines or word lines which can increase a defect relief probability and improve an operational margin. The reserve bit lines or word lines are provided approximately in a central portion of a memory mat. Because of a low probability of defect occurrence in the reserve word lines or bit lines, the probability of defect occurrence can be made low when a defective word line or bit line is replaced with a reserve word line or bit line.
摘要翻译：具有备用位线或字线的半导体存储器件，用于替换有缺陷的位线或字线，这些位线或字线可以增加缺陷消除概率并提高操作余量。保留位线或字线大致设置在存储垫的中央部分。由于在备用字线或位线中存在缺陷发生的可能性低的情况，当用保留字线或位线替换缺陷字线或位线时，可能会使缺陷发生的概率变低。

25. 发明授权

US5301142A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5301142A
公开(公告)日：1994-04-05
申请号：US895598
申请日：1992-06-08
申请人： Yukihide Suzuki , Masaya Muranaka , Hiromi Matsuura , Yoshinobu Nakagome , Hitoshi Tanaka , Eiji Yamasaki , Toshiyuki Sakuta
发明人： Yukihide Suzuki , Masaya Muranaka , Hiromi Matsuura , Yoshinobu Nakagome , Hitoshi Tanaka , Eiji Yamasaki , Toshiyuki Sakuta
IPC分类号： G11C11/401 , G11C7/10 , G11C11/409 , G11C29/00 , G11C29/34 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C13/00
CPC分类号： G11C7/10
摘要： Each of a plurality of memory arrays is divided into a plurality of memory mats MAT00L-MAT07L to MAT10R-MAT17R in directions in which word lines and bit lines extend. First common data lines, that is, sub-IO lines, are provided which correspond to these memory mats and which are disposed in parallel to the word lines. Bit lines designating the corresponding memory mats are selectively connected to the first common data lines. Second common data lines, that is, main IO line groups MIOG0-MIOG7, are also provided and are disposed in parallel to the bit lines. Designated sub-IO lines are selectively connected to the second common data lines. Moreover, a plurality of main amplifiers forming a main amplifier unit MAU0 are orderly arranged in the direction in which the bit lines extend. These include a first main amplifier comprising a static current mirror amplifier which requires a relatively large operating current and a second main amplifier comprising a dynamic CMOS latch amplifier which requires only a relatively small operating current. These main amplifiers are put to proper use in conformity with the operating mode involved. By virtue of these arrangements, the number of parallel bits in a multibit parallel test mode of a dynamic RAM becomes expandable without being restricted by the number of the sub-IO lines correspondingly provided for each memory mat.
摘要翻译：在字线和位线延伸的方向上，多个存储器阵列中的每一个被分成多个存储器块MAT00L-MAT07L到MAT10R-MAT17R。提供了与这些存储垫对应并且与字线平行设置的第一公共数据线，即子IO线。指定对应的存储器垫的位线选择性地连接到第一公共数据线。还提供第二公共数据线，即主IO线组MIOG0-MIOG7，并且与位线并行设置。指定的子IO线选择性地连接到第二公共数据线。此外，形成主放大器单元MAU0的多个主放大器在位线延伸的方向上有序排列。这些包括第一主放大器，其包括需要相对大的工作电流的静态电流镜放大器，以及包括仅需要较小工作电流的动态CMOS锁存放大器的第二主放大器。这些主放大器按照所涉及的工作模式正确使用。由于这些布置，动态RAM的多位并行测试模式中的并行比特数可以扩展，而不受对应于每个存储器垫的子IO线数的限制。

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