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21. 发明申请

US20060068537A1 Method of manufacturing semiconductor device 有权
公开(公告)号：US20060068537A1
公开(公告)日：2006-03-30
申请号：US11231799
申请日：2005-09-22
申请人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka
发明人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/7828 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/7827
摘要： A method of manufacturing a semiconductor device having: forming a hetero semiconductor layer on at least the major surface of the semiconductor substrate body of a first conductivity type; etching the hetero semiconductor layer selectively by use of a mask layer having openings in way that the hetero semiconductor layer remains to be not etched with a predetermined thickness; oxidizing an exposed parts of the hetero semiconductor layer; forming the hetero semiconductor region by etching a oxidized film formed in the oxidizing; and forming the gate insulating film in a way that the gate insulating film makes an intimate contact with the hetero semiconductor region and the semiconductor substrate body. The bandgap of the hetero semiconductor layer is different from that of the semiconductor substrate body. The gate electrode is arranged in a junction part between the hetero semiconductor region and the semiconductor substrate body with the gate insulating film interposed between the gate electrode and the junction part.

22. 发明授权

US09048103B2 Method for producing semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US09048103B2
公开(公告)日：2015-06-02
申请号：US11988305
申请日：2006-06-26
申请人： Yoshio Shimoida , Hideaki Tanaka , Tetsuya Hayashi , Masakatsu Hoshi , Shigeharu Yamagami , Noriaki Kawamoto , Takayuki Kitou , Mineo Miura , Takashi Nakamura
发明人： Yoshio Shimoida , Hideaki Tanaka , Tetsuya Hayashi , Masakatsu Hoshi , Shigeharu Yamagami , Noriaki Kawamoto , Takayuki Kitou , Mineo Miura , Takashi Nakamura
IPC分类号： H01L21/336 , H01L21/3105 , H01L29/78 , H01L21/04 , H01L29/267 , H01L29/66 , H01L29/16 , H01L29/772
CPC分类号： H01L21/049 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/772 , H01L29/7828
摘要： A method for producing a semiconductor device (20) is disclosed. The semiconductor device (20) includes: 1) a semiconductor substrate (1, 2), 2) a hetero semiconductor area (3) configured to contact a first main face (1A) of the semiconductor substrate (1, 2) and different from the semiconductor substrate (1, 2) in band gap, 3) a gate electrode (7) contacting, via a gate insulating film (6), a part of a junction part (13) between the hetero semiconductor area (3) and the semiconductor substrate (1, 2), 4) a source electrode (8) configured to connect to the hetero semiconductor area (3), and 5) a drain electrode (9) configured to make an ohmic connection with the semiconductor substrate (1, 2). The method includes the following sequential operations: i) forming the gate insulating film (6); and ii) nitriding the gate insulating film (6).
摘要翻译：公开了一种用于制造半导体器件（20）的方法。半导体器件（20）包括：1）半导体衬底（1,2），2）异质半导体区域（3），被配置为接触半导体衬底（1,2）的第一主面（1A）所述半导体衬底（1,2）具有带隙，3）栅极电极（7）经由栅极绝缘膜（6）与所述异质半导体区域（3）之间的接合部分（13）的一部分半导体衬底（1,2），4）构造成连接到所述异质半导体区域（3）的源电极（8），以及5）被配置为与所述半导体衬底（1,2）形成欧姆连接的漏电极（9） 2）。该方法包括以下顺序操作：i）形成栅绝缘膜（6）; 和ii）氮化所述栅极绝缘膜（6）。

23. 发明授权

US07768035B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07768035B2
公开(公告)日：2010-08-03
申请号：US12066145
申请日：2006-08-02
申请人： Yoshio Shimoida , Tetsuya Hayashi , Masakatsu Hoshi , Hideaki Tanaka , Shigeharu Yamagami
发明人： Yoshio Shimoida , Tetsuya Hayashi , Masakatsu Hoshi , Hideaki Tanaka , Shigeharu Yamagami
IPC分类号： H01L31/0328
CPC分类号： H01L29/0847 , H01L21/0445 , H01L29/0696 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/7828
摘要： A semiconductor device has a semiconductor base of a first conductivity type; a hetero semiconductor region in contact with the semiconductor base; a gate electrode adjacent to a portion of a junction between the hetero semiconductor region and the semiconductor base across a gate insulating film; a source electrode connected to the hetero semiconductor region; and a drain electrode connected to the semiconductor base. The hetero semiconductor region has a band gap different from that of the semiconductor base. The hetero semiconductor region includes a first hetero semiconductor region and a second hetero semiconductor region. The first hetero semiconductor region is formed before the gate insulating film is formed. The second hetero semiconductor region is formed after the gate insulating film is formed.
摘要翻译：半导体器件具有第一导电类型的半导体基底; 与半导体基底接触的异质半导体区域; 与栅极绝缘膜相邻的异质半导体区域和半导体基底之间的结的部分相邻的栅电极; 连接到所述异质半导体区的源电极; 以及连接到半导体基底的漏电极。异质半导体区域具有与半导体基底不同的带隙。异质半导体区域包括第一异质半导体区域和第二异质半导体区域。在形成栅极绝缘膜之前形成第一异质半导体区域。在形成栅极绝缘膜之后形成第二异质半导体区域。

24. 发明授权

US07749845B2 Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：US07749845B2
公开(公告)日：2010-07-06
申请号：US11988944
申请日：2006-06-26
申请人： Shigeharu Yamagami , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka , Yoshio Shimoida
发明人： Shigeharu Yamagami , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka , Yoshio Shimoida
IPC分类号： H01L21/336
CPC分类号： H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/7827
摘要： A method of manufacturing a semiconductor device having a polycrystalline silicon layer (5) includes; a step of forming a mask layer (7) on the polycrystalline silicon layer (5); a step of forming a side wall (8) that is provided on a side face of the mask layer (7) and covers part of the polycrystalline silicon layer (6); a step of doping an impurity (52) into the polycrystalline silicon layer (5) by using at least one of the mask layer (7) and the side wall (8) as a mask; and a step of etching the polycrystalline silicon layer (5, 6) by using at least one of the mask layer (7) and the side wall (8) as a mask.
摘要翻译：一种制造具有多晶硅层（5）的半导体器件的方法包括：在多晶硅层（5）上形成掩模层（7）的步骤; 形成设置在掩模层（7）的侧面并覆盖多晶硅层（6）的一部分的侧壁（8）的步骤; 通过使用掩模层（7）和侧壁（8）中的至少一个作为掩模将杂质（52）掺杂到多晶硅层（5）中的步骤; 以及通过使用掩模层（7）和侧壁（8）中的至少一个作为掩模来蚀刻多晶硅层（5,6）的步骤。

25. 发明申请

US20090200575A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090200575A1
公开(公告)日：2009-08-13
申请号：US12423207
申请日：2009-04-14
申请人： Yoshio SHIMOIDA , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka , Shigeharu Yamagami
发明人： Yoshio SHIMOIDA , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka , Shigeharu Yamagami
IPC分类号： H01L29/78
CPC分类号： H01L29/78 , H01L21/047 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/772 , H01L29/7828
摘要： A semiconductor device is provided with a semiconductor region, a gate electrode, a source electrode and a drain electrode. The semiconductor region is formed on a semiconductor substrate surface and includes a first semiconductor portion of a first conducting type, a second semiconductor portion of a second conducting type, a band gap distinct from the substrate's band gap, more than two accumulated semiconductor layers, and junctions between the layers. The semiconductor layers each contain an impurity of the first conducting type. The gate electrode adjoins a heterojunction between the second semiconductor portion and the semiconductor substrate through a gate insulation film. The source electrode is coupled to the semiconductor region. The drain electrode is coupled to the semiconductor substrate.
摘要翻译：半导体器件设置有半导体区域，栅极电极，源极电极和漏极电极。半导体区域形成在半导体衬底表面上，并且包括第一导电类型的第一半导体部分，第二导电类型的第二半导体部分，与衬底带隙不同的带隙，多于两个的累积半导体层，以及层之间的交叉点。半导体层各自含有第一导电类型的杂质。栅极通过栅极绝缘膜与第二半导体部分和半导体衬底之间的异质结相邻。源电极耦合到半导体区域。漏电极耦合到半导体衬底。

26. 发明授权

US07521731B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07521731B2
公开(公告)日：2009-04-21
申请号：US11444433
申请日：2006-06-01
申请人： Yoshio Shimoida , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka
发明人： Yoshio Shimoida , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka
IPC分类号： H01L31/0328
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/1608 , H01L29/2003 , H01L29/66068 , H01L29/66712 , H01L29/66734 , H01L29/7813 , H01L29/8083
摘要： A semiconductor device of the invention includes a first conductive type semiconductor base substrate; and a switching mechanism which is formed on a first main surface of the semiconductor base substrate and switches ON/OFF of a current. In the semiconductor base substrate, a plurality of columnar hetero-semiconductor regions are formed at spaced intervals within the semiconductor substrate, and the hetero-semiconductor regions are made of a semiconductor material having a different band gap from the semiconductor substrate and extend between the first main surface and a second main surface opposite to the first main surface.
摘要翻译：本发明的半导体器件包括：第一导电型半导体基底; 以及切换机构，其形成在所述半导体基板的第一主面上并切换电流的开/关。在半导体基板中，多个柱状异质半导体区域在半导体衬底内隔开间隔地形成，并且异质半导体区域由与半导体衬底具有不同带隙的半导体材料制成，并且在第一主表面和与第一主表面相对的第二主表面。

27. 发明授权

US07436004B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07436004B2
公开(公告)日：2008-10-14
申请号：US11289460
申请日：2005-11-30
申请人： Yoshio Shimoida , Masakatsu Hoshi , Hideaki Tanaka , Tetsuya Hayashi , Toshiro Shinohara , Shigeharu Yamagami
发明人： Yoshio Shimoida , Masakatsu Hoshi , Hideaki Tanaka , Tetsuya Hayashi , Toshiro Shinohara , Shigeharu Yamagami
IPC分类号： H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109 , H01L31/111
CPC分类号： H01L29/7398 , H01L29/0834 , H01L29/1608 , H01L29/267 , H01L29/7391 , H01L29/7392 , H01L29/7395 , H01L29/7397
摘要： An aspect of the present invention provides a semiconductor device that includes, a first semiconductor body of a first conductivity type, a first switching mechanism provided on the first semiconductor body, configured and arranged to switch on/off current flowing through the semiconductor device, and a first reverse-blocking heterojunction diode provided on the semiconductor body, configured and arranged to block current reverse to the current switched on/off by the first switching mechanism.
摘要翻译：本发明的一个方面提供一种半导体器件，其包括：第一导电类型的第一半导体本体，设置在第一半导体本体上的第一开关机构，被配置和布置成用于接通流过半导体器件的导通/截止电流;以及设置在所述半导体本体上的第一反向阻挡异质结二极管，被配置和布置成阻止与所述第一开关机构相反的电流接通/断开。

28. 发明申请

US20070298586A1 Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20070298586A1
公开(公告)日：2007-12-27
申请号：US11454818
申请日：2006-06-21
申请人： Hideaki Tanaka , Masakatsu Hoshi , Yoshio Shimoida , Tetsuya Hayashi
发明人： Hideaki Tanaka , Masakatsu Hoshi , Yoshio Shimoida , Tetsuya Hayashi
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L29/66068 , H01L21/6835 , H01L29/0619 , H01L29/0623 , H01L29/1608 , H01L29/267 , H01L29/6606 , H01L29/7828 , H01L29/861 , H01L2221/68363
摘要： The present invention provides a method of manufacturing a semiconductor device. The semiconductor device comprises a semiconductor base made of a first semiconductor material; and a hetero-semiconductor region made of a second semiconductor material having a different band gap from the first semiconductor material and forming a heterojunction with the semiconductor base. The formation of the heterojunction is accomplished by bonding together the semiconductor base and a substrate made of the second semiconductor material.
摘要翻译：本发明提供一种制造半导体器件的方法。半导体器件包括由第一半导体材料制成的半导体基底; 以及由与第一半导体材料具有不同带隙并与半导体基底形成异质结的第二半导体材料制成的异质半导体区域。异质结的形成通过将半导体基底和由第二半导体材料制成的基底结合在一起来实现。

29. 发明申请

US20060223274A1 Semiconductor device and manufacturing method thereof 有权
公开(公告)号：US20060223274A1
公开(公告)日：2006-10-05
申请号：US11377909
申请日：2006-03-16
申请人： Yoshio Shimoida , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka , Shigeharu Yamagami
发明人： Yoshio Shimoida , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka , Shigeharu Yamagami
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L29/78 , H01L21/047 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/772 , H01L29/7828
摘要： In general, this disclosure describes a semiconductor device that exhibits an increased resistance and reduced leakage current in a reverse-biased state, and a method for manufacturing such a semiconductor device. For example, in one embodiment, the increased resistance in the reverse-biased state is obtained by introducing either a P+ or P− type impurity in a polycrystalline silicon layer formed on an N− type epitaxial layer. Additionally, the semiconductor device maintains a low resistance in a forward-biased state. To keep the forward-biased resistance low, the polycrystalline silicon layer in the vicinity of a gate electrode may be of an N+ type. Furthermore, an N+ type source extracting region is formed on the surface of the polycrystalline silicon layer to connect a source electrode to a drain electrode and maintain a low resistance when forward-biased.

30. 发明授权

US07880199B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07880199B2
公开(公告)日：2011-02-01
申请号：US11790791
申请日：2007-04-27
申请人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka , Shigeharu Yamagami
发明人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka , Shigeharu Yamagami
IPC分类号： H01L29/66
CPC分类号： H01L29/0847 , H01L29/1033 , H01L29/1608 , H01L29/267 , H01L29/4916 , H01L29/66068 , H01L29/7828
摘要： A semiconductor device is provided with: a semiconductor substrate of a predetermined electroconduction type; a hetero semiconductor region contacted with a first main surface of the semiconductor substrate and comprising a semiconductor material having a bandgap different from that of the semiconductor substrate; a gate electrode formed through a gate insulator layer at a position adjacent to a junction region between the hetero semiconductor region and the semiconductor substrate; a source electrode connected to the hetero semiconductor region; and a drain electrode connected to the semiconductor substrate; wherein the hetero semiconductor region includes a contact portion contacted with the source electrode, at least a partial region of the contact portion is of the same electroconduction type as the electroconduction type of the semiconductor substrate, and the partial region has an impurity concentration higher than an impurity concentration of at least that partial region of a gate-electrode facing portion in the hetero semiconductor region which is positioned to face toward the gate electrode through the gate insulator layer.
摘要翻译：半导体器件具有：预定的导电型的半导体衬底; 与所述半导体衬底的第一主表面接触并且包括具有与所述半导体衬底的带隙不同的带隙的半导体材料的异质半导体区域; 在与所述异质半导体区域和所述半导体基板之间的接合区域相邻的位置处形成的栅极电极，连接到所述异质半导体区的源电极; 和连接到半导体衬底的漏电极; 其中所述异质半导体区域包括与所述源电极接触的接触部分，所述接触部分的至少一部分区域具有与所述半导体衬底的导电型相同的导电类型，并且所述部分区域的杂质浓度高于至少通过栅极绝缘体层位于面向栅电极的异质半导体区域中的栅电极面对部分的部分区域的杂质浓度。

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