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21. 发明申请

US20060003573A1 Method to fabricate aligned dual damacene openings 有权
标题翻译：制造对齐双重断裂孔的方法
公开(公告)号：US20060003573A1
公开(公告)日：2006-01-05
申请号：US11174805
申请日：2005-07-05
申请人： Yeow Lim , Wuping Liu , Tae Lee , Bei Zhang , Juan Boon Tan , Alan Cuthbertson , Chin Neo
发明人： Yeow Lim , Wuping Liu , Tae Lee , Bei Zhang , Juan Boon Tan , Alan Cuthbertson , Chin Neo
IPC分类号： H01L21/4763
CPC分类号： H01L21/76807 , H01L21/76829 , H01L21/76834
摘要： An aligned dual damascene opening structure, comprising the following. A structure having a metal structure formed thereover. A patterned layer stack over the metal structure; the layer stack comprising, in ascending order: a patterned bottom etch stop layer; a patterned lower dielectric material layer; a patterned middle etch stop layer; and a patterned middle dielectric material layer; the lower and middle dielectric layers being comprised of the same material. An upper trench opening in the patterned bottom etch stop layer and the patterned lower dielectric material layer; and a lower via opening in the patterned middle etch stop layer and the patterned middle dielectric material layer. The lower via opening being in communication with the upper trench opening. Wherein the upper trench opening and the lower via opening comprise an aligned dual damascene opening.
摘要翻译：对准的双镶嵌开口结构，包括以下。具有形成在其上的金属结构的结构。金属结构上的图案层叠层; 所述层堆叠按升序包括：图案化的底部蚀刻停止层; 图案化的下介电材料层; 图案化的中间蚀刻停止层; 和图案化的中间介电材料层; 下部和中间介电层由相同的材料组成。在图案化的底部蚀刻停止层和图案化的下部介电材料层中的上部沟槽开口; 以及图案化的中间蚀刻停止层和图案化的中间介电材料层中的下通孔开口。下通道开口与上沟槽开口连通。其中上沟槽开口和下通孔开口包括对准的双镶嵌开口。

22. 发明申请

US20050191851A1 Barrier metal cap structure on copper lines and vias 审中-公开
标题翻译：铜线和通孔上的金属盖结构
公开(公告)号：US20050191851A1
公开(公告)日：2005-09-01
申请号：US11119274
申请日：2005-04-29
申请人： Wuping Liu , Beichao Zhang , Liang Hsia
发明人： Wuping Liu , Beichao Zhang , Liang Hsia
IPC分类号： H01L21/768 , H01L21/4763 , H01L21/44 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76849 , H01L21/76805 , H01L21/76807 , H01L21/7684 , H01L21/76865 , H01L21/76877
摘要： A new method is provided for the creation of damascene copper interconnects. A method is provided whereby created copper surfaces are capped with a layer of barrier material. With the cap structure of barrier material, the surface of the created copper interconnect is shielded against outside influences such as effects of processing chemicals. As a result of the creation of a cap of barrier material, conventional concerns of copper oxidation, copper back-sputtering and the like are eliminated.
摘要翻译：提供了一种用于创建镶嵌铜互连的新方法。提供了一种方法，由此产生的铜表面被一层屏障材料盖住。通过阻挡材料的盖结构，所制造的铜互连的表面被屏蔽以防止诸如加工化学品的影响等外部影响。作为阻挡材料盖的形成的结果，消除了铜氧化，铜背溅射等的常规问题。

23. 发明申请

US20050127495A1 Method of fabrication of a die oxide ring 有权
标题翻译：芯片氧化物环的制造方法
公开(公告)号：US20050127495A1
公开(公告)日：2005-06-16
申请号：US10734423
申请日：2003-12-12
申请人： Fan Zhang , Bei Zhang , Wuping Liu , Kho Chok , Liang Hsia , Tae Lee , Juan Tan , Xian Wang
发明人： Fan Zhang , Bei Zhang , Wuping Liu , Kho Chok , Liang Hsia , Tae Lee , Juan Tan , Xian Wang
IPC分类号： H01L23/00 , H01L23/31 , H01L23/04 , H01L21/4763
CPC分类号： H01L23/562 , H01L23/3178 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： In accordance with the objectives of the invention a new design and method for the implementation thereof is provided in the form of an “oxide ring”. A conventional die is provided with a guard ring or sealing ring, which surrounds and isolates the active surface area of an individual semiconductor die. The “oxide ring” of the invention surrounds the guard ring or sealing ring and forms in this manner a mechanical stress release buffer between the sawing paths of the die and the active surface area of the singulated individual semiconductor die.
摘要翻译：根据本发明的目的，以“氧化物环”的形式提供了一种用于实施本发明的新设计和方法。传统的模具设置有保护环或密封环，其围绕并隔离单个半导体管芯的有源表面积。本发明的“氧化物环”围绕保护环或密封环，并以这种方式形成在管芯的锯切路径和单个化的半导体管芯的有源表面区域之间的机械应力释放缓冲器。

24. 发明申请

US20130017656A1 METHOD OF FABRICATING A SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20130017656A1
公开(公告)日：2013-01-17
申请号：US13289983
申请日：2011-11-04
申请人： Qingsong Wei , Wei Lu , Wuping Liu , Yonggen He
发明人： Qingsong Wei , Wei Lu , Wuping Liu , Yonggen He
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L21/30608 , H01L21/26533 , H01L21/3083 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A method of fabricating semiconductor device is provided. First, a recess having a substantially rectangular cross section is formed in a substrate. Then, oxide layers are formed on sidewalls and bottom of the recess by oxygen ion implantation process, wherein oxide layer on sidewalls of recess is thinner than oxide layer on bottom of recess. Thereafter, oxide layer on sidewalls of recess is completely removed, and only a portion of oxide layer on bottom of recess remains. Then, sidewalls of recess are shaped into Σ form by orientation selective wet etching using oxide layer remained on bottom of recess as a stop layer. Finally, oxide layer on bottom of recess is removed. By forming oxide layer on bottom of recess and using it as stop layer in subsequent orientation selective wet etching, the disclosed method can prevent a Σ-shaped recess with a cuspate bottom.
摘要翻译：提供一种制造半导体器件的方法。首先，在基板上形成具有大致矩形截面的凹部。然后，通过氧离子注入工艺在凹槽的侧壁和底部形成氧化物层，其中凹陷侧壁上的氧化物层比凹部底部的氧化物层薄。此后，凹槽侧壁上的氧化物层被完全去除，并且凹部底部仅有一部分氧化物层残留。然后，凹槽的侧壁成形为＆Sgr; 通过使用氧化物层的取向选择性湿法蚀刻形成残留在凹陷的底部作为停止层的形式。最后，去除凹槽底部的氧化物层。通过在凹部的底部形成氧化物层并将其用作随后的取向选择性湿蚀刻中的停止层，所公开的方法可以防止具有尖端底部的“形”凹槽。

25. 发明申请

US20100013104A1 INTEGRATED CIRCUIT HARD MASK PROCESSING SYSTEM 有权
标题翻译：集成电路硬掩模处理系统
公开(公告)号：US20100013104A1
公开(公告)日：2010-01-21
申请号：US12567490
申请日：2009-09-25
申请人： Wuping Liu , Michael Beck , John A. Fitzsimmons
发明人： Wuping Liu , Michael Beck , John A. Fitzsimmons
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76804 , H01L21/02063 , H01L21/76814 , H01L21/76835
摘要： An integrated circuit processing system is provided including a substrate having an integrated circuit; an interconnect layer over the integrated circuit; a low-K dielectric layer over the interconnect layer; a hard mask layer over the low-K dielectric layer; a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; and an interconnect metal in the via opening.
摘要翻译：提供一种集成电路处理系统，其包括具有集成电路的基板; 集成电路上的互连层; 互连层上的低K电介质层; 在低K电介质层上的硬掩模层; 穿过所述硬掩模层和所述低K电介质层到所述互连层的通孔; 和通孔开口中的互连金属。

26. 发明授权

US07372156B2 Method to fabricate aligned dual damascene openings 有权
标题翻译：制造对准双镶嵌开口的方法
公开(公告)号：US07372156B2
公开(公告)日：2008-05-13
申请号：US11174805
申请日：2005-07-05
申请人： Yeow Kheng Lim , Wuping Liu , Tae Jong Lee , Bei Chao Zhang , Juan Boon Tan , Alan Cuthbertson , Chin Chuan Neo
发明人： Yeow Kheng Lim , Wuping Liu , Tae Jong Lee , Bei Chao Zhang , Juan Boon Tan , Alan Cuthbertson , Chin Chuan Neo
IPC分类号： H01L29/40
CPC分类号： H01L21/76807 , H01L21/76829 , H01L21/76834
摘要： An aligned dual damascene opening structure, comprising the following. A structure having a metal structure formed thereover. A patterned layer stack over the metal structure; the layer stack comprising, in ascending order: a patterned bottom etch stop layer; a patterned lower dielectric material layer; a patterned middle etch stop layer; and a patterned middle dielectric material layer; the lower and middle dielectric layers being comprised of the same material. An upper trench opening in the patterned bottom etch stop layer and the patterned lower dielectric material layer; and a lower via opening in the patterned middle etch stop layer and the patterned middle dielectric material layer. The lower via opening being in communication with the upper trench opening. Wherein the upper trench opening and the lower via opening comprise an aligned dual damascene opening.
摘要翻译：对准的双镶嵌开口结构，包括以下。具有形成在其上的金属结构的结构。金属结构上的图案层叠层; 所述层堆叠按升序包括：图案化的底部蚀刻停止层; 图案化的下介电材料层; 图案化的中间蚀刻停止层; 和图案化的中间介电材料层; 下部和中间介电层由相同的材料组成。在图案化的底部蚀刻停止层和图案化的下部介电材料层中的上部沟槽开口; 以及图案化的中间蚀刻停止层和图案化的中间介电材料层中的下通孔开口。下通道开口与上沟槽开口连通。其中上沟槽开口和下通孔开口包括对准的双镶嵌开口。

27. 发明授权

US07256136B2 Self-patterning of photo-active dielectric materials for interconnect isolation 有权
标题翻译：用于互连隔离的光电介质材料的自构图
公开(公告)号：US07256136B2
公开(公告)日：2007-08-14
申请号：US11345890
申请日：2006-02-02
申请人： Wuping Liu , Bei Chao Zhang , Liang Choo Hsia
发明人： Wuping Liu , Bei Chao Zhang , Liang Choo Hsia
IPC分类号： H01L21/64
CPC分类号： H01L21/76814 , H01L21/4846 , H01L21/76802 , H01L21/76807 , H01L21/76828 , H01L23/5329 , H01L2221/1026 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： In accordance with the objectives of the invention a new method is provided for the creation of an interconnect pattern. The invention provides for a layer of Photo-Active Dielectric (PAD) to be used for the insulation material in which the interconnect pattern is created, this without the use of an overlying exposure mask of photoresist.
摘要翻译：根据本发明的目的，提供了一种用于创建互连图案的新方法。本发明提供了一种用于产生互连图案的绝缘材料的光电介质（PAD）层，不需要使用光致抗蚀剂的上覆曝光掩模。

28. 发明授权

US07153766B2 Metal barrier cap fabrication by polymer lift-off 有权
公开(公告)号：US07153766B2
公开(公告)日：2006-12-26
申请号：US10339188
申请日：2003-01-09
申请人： Beichao Zhang , Wuping Liu , Liang-Choo Hsia
发明人： Beichao Zhang , Wuping Liu , Liang-Choo Hsia
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76834 , H01L21/76849 , H01L21/76865 , H01L21/76883 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A new method is provided for the creation of copper interconnects. A pattern of copper interconnects is created, a protective layer of semiconductor material is deposited over the surface of the created copper interconnects. The protective layer is patterned and etched, exposing the surface of the pattern of copper interconnects. The exposed copper surface is Ar sputtered after which a first barrier layer is deposited. The patterned and etched layer of protective material is removed, leaving in place overlying the pattern of copper interconnects a protective layer of first barrier material. A dielectric barrier layer, in the form of a layer of etch stop material, is deposited after which additional layers of dielectric interspersed with layers of etch stop material are deposited. Via and trench patterns are etched aligned with a copper pattern to which an electrical contact is to be established, the copper pattern being protected by the first layer of barrier material. A second barrier layer is deposited, the via and trench pattern is filled with copper after which excess copper is removed by polishing the surface of the deposited layer of copper.

29. 发明申请

US20060088995A1 Metal barrier cap fabrication by polymer lift-off 有权
标题翻译：通过聚合物剥离制造金属阻挡帽
公开(公告)号：US20060088995A1
公开(公告)日：2006-04-27
申请号：US11299457
申请日：2005-12-12
申请人： Beichao Zhang , Wuping Liu , Liang-Choo Hsia
发明人： Beichao Zhang , Wuping Liu , Liang-Choo Hsia
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76834 , H01L21/76849 , H01L21/76865 , H01L21/76883 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A new method is provided for the creation of copper interconnects. A pattern of copper interconnects is created, a protective layer of semiconductor material is deposited over the surface of the created copper interconnects. The protective layer is patterned and etched, exposing the surface of the pattern of copper interconnects. The exposed copper surface is Ar sputtered after which a first barrier layer is deposited. The patterned and etched layer of protective material is removed, leaving in place overlying the pattern of copper interconnects a protective layer of first barrier material. A dielectric barrier layer, in the form of a layer of etch stop material, is deposited after which additional layers of dielectric interspersed with layers of etch stop material are deposited. Via and trench patterns are etched aligned with a copper pattern to which an electrical contact is to be established, the copper pattern being protected by the first layer of barrier material. A second barrier layer is deposited, the via and trench pattern is filled with copper after which excess copper is removed by polishing the surface of the deposited layer of copper.
摘要翻译：提供了一种用于创建铜互连的新方法。产生铜互连的图案，半导体材料的保护层沉积在所产生的铜互连的表面上。保护层被图案化和蚀刻，暴露铜互连图案的表面。暴露的铜表面是Ar溅射，之后沉积第一势垒层。去除保护材料的图案化和蚀刻层，留在覆盖铜图案的位置使第一阻挡材料的保护层互连。沉积了一层蚀刻停止材料形式的电介质阻挡层，之后沉积了分层的蚀刻停止材料层。通孔和沟槽图案被蚀刻成与将要建立电接触的铜图案对齐，铜图案被第一层屏障材料保护。沉积第二阻挡层，通孔和沟槽图案填充有铜，之后通过抛光沉积的铜层的表面去除多余的铜。

30. 发明授权

US06967156B2 Method to fabricate aligned dual damascene openings 有权
标题翻译：制造对准双镶嵌开口的方法
公开(公告)号：US06967156B2
公开(公告)日：2005-11-22
申请号：US10690998
申请日：2003-10-22
申请人： Yeow Kheng Lim , Wuping Liu , Tae Jong Lee , Bei Chao Zhang , Juan Boon Tan , Alan Cuthbertson , Chin Chuan Neo
发明人： Yeow Kheng Lim , Wuping Liu , Tae Jong Lee , Bei Chao Zhang , Juan Boon Tan , Alan Cuthbertson , Chin Chuan Neo
IPC分类号： H01L21/4763 , H01L21/768 , H01L29/06
CPC分类号： H01L21/76807 , H01L21/76829 , H01L21/76834
摘要： A method of forming an aligned dual damascene opening, comprising including the following sequential steps. A layer stack is formed over the metal structure. The layer stack comprises, in ascending order: a bottom etch stop layer; a lower dielectric material layer; a middle etch stop layer; a middle dielectric material layer; and an upper dielectric layer. A patterned mask layer is formed over the patterned upper dielectric layer leaving exposed opposing portions of the patterned upper dielectric layer. The middle dielectric material layer is patterned to form an opening therein using the patterned mask layer and the exposed portions of the upper dielectric layer as masks. Simultaneously patterning the patterned middle dielectric material layer using the patterned upper dielectric layer as a mask to form an inchoate upper trench opening; and the lower dielectric material layer using the patterned mask layer and the patterned middle etch stop layer as masks to form an inchoate lower via opening aligned with the inchoate upper trench opening.
摘要翻译：一种形成对准的双镶嵌开口的方法，包括以下顺序步骤。在金属结构上形成层叠。层叠层按升序包括底蚀刻停止层; 下介电材料层; 中间蚀刻停止层; 中间介电材料层; 和上介电层。图案化的掩模层形成在图案化的上介电层上，留下图案化的上介电层的暴露的相对部分。使用图案化掩模层和上介电层的暴露部分作为掩模，将中介电材料层图案化以形成开口。使用图案化的上电介质层作为掩模，同时对图案化的中间介电材料层进行图案化以形成初始上沟槽开口; 并且使用图案化掩模层和图案化的中间蚀刻停止层作为掩模的下部电介质材料层形成与前述上部沟槽开口对准的开口下部通孔。

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