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21. 发明授权

US06459625B1 Three metal process for optimizing layout density 有权
标题翻译：三金属工艺优化布局密度
公开(公告)号：US06459625B1
公开(公告)日：2002-10-01
申请号：US09767341
申请日：2001-01-23
申请人： Colin S. Bill , Jonathan S. Su , Ravi P. Gutala
发明人： Colin S. Bill , Jonathan S. Su , Ravi P. Gutala
IPC分类号： G11C1604
CPC分类号： G11C5/025 , G11C16/0408
摘要： The present invention discloses a method and system to optimize electrical interconnection of electrical components in a periphery area of a memory device thereby minimizing the periphery area. The periphery area is divided into a plurality of sub-circuits formed by selectively electrically connecting the electrical components. Electrical interconnection of the electrical components to form the sub-circuits is accomplished using a first metal layer and a second metal layer. The first metal layer is formed to create a plurality of first metal layer lines that are oriented to extend in substantially one direction on the memory device. The second metal layer is formed to create a plurality of second metal layer lines that are oriented to extend substantially perpendicular to the first metal layer lines. The plurality of sub-circuits are electrically interconnected using a third metal layer that is formed to create a plurality of third metal layer lines that are oriented to extend substantially parallel to the first metal layer lines.
摘要翻译：本发明公开了一种用于优化存储器件周边区域中的电气元件的电互连从而最小化外围区域的方法和系统。周边区域被分成通过选择性地电连接电气部件而形成的多个子电路。使用第一金属层和第二金属层实现电气部件的电互连以形成子电路。形成第一金属层以形成多个第一金属层线，其被定向成在存储器件上沿基本上一个方向延伸。形成第二金属层以形成多个第二金属层线，其被定向成基本上垂直于第一金属层线延伸。多个子电路使用第三金属层电互连，第三金属层被形成以形成多个第三金属层线，其被定向成基本上平行于第一金属层线延伸。

22. 发明授权

US6163481A Flash memory wordline tracking across whole chip 有权
标题翻译：整个芯片上的闪存字线跟踪
公开(公告)号：US6163481A
公开(公告)日：2000-12-19
申请号：US431296
申请日：1999-10-29
申请人： Shigekasu Yamada , Colin S. Bill , Michael A. VanBuskirk
发明人： Shigekasu Yamada , Colin S. Bill , Michael A. VanBuskirk
IPC分类号： G11C16/06 , G11C8/08 , G11C8/14 , G11C16/08 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C16/04
CPC分类号： G11C16/08 , G11C8/08 , G11C8/14
摘要： A wordline tracking structure for use in an array of Flash EEPROM memory cells is provided. The tracking structure serves to match reference and sector core wordline voltages across the entire chip regardless of sector location. The tracking structure includes a second VPXG conductor line operatively connected between sector wordlines of a "far" sector and a reference cell mini-array. The second VPXG conductor line has a substantially smaller time constant than in a first VPXG conductor line operatively connected between an output of a boosting circuit and the sector wordlines of the "far" sector. As a consequence, the reference wordline voltage associated with the reference cell mini-array will track closely the sector wordline voltage during the read operation regardless of the location of the selected sector.
摘要翻译：提供了一种用于闪存EEPROM存储单元阵列的字线跟踪结构。跟踪结构用于匹配整个芯片上的参考和扇区核心字线电压，而不考虑扇区位置。跟踪结构包括可操作地连接在“远”扇区的扇区字线与参考单元微阵列之间的第二VPXG导体线。第二VPXG导体线具有比可操作地连接在升压电路的输出和“远”部分的扇区字线之间的第一VPXG导线中的时间常数更小的时间常数。因此，与参考单元小型阵列相关联的参考字线电压将在读取操作期间密切跟踪扇区字线电压，而与所选扇区的位置无关。

23. 发明授权

US5712815A Multiple bits per-cell flash EEPROM capable of concurrently programming and verifying memory cells and reference cells 失效
标题翻译：多位每单元闪存EEPROM能够同时编程和验证存储单元和参考单元
公开(公告)号：US5712815A
公开(公告)日：1998-01-27
申请号：US635995
申请日：1996-04-22
申请人： Colin S. Bill , Sameer S. Haddad
发明人： Colin S. Bill , Sameer S. Haddad
IPC分类号： G11C11/56 , G11C16/34 , G11C16/06
CPC分类号： G11C16/3486 , G11C11/5621 , G11C11/5628 , G11C16/3468 , G11C16/3481 , G11C2211/5621 , G11C2211/5622 , G11C2211/5624 , G11C2211/5642 , G11C2211/5645 , G11C2216/14
摘要： An improved programming structure for performing a program operation in an array of multiple bits-per-cell flash EEPROM memory cells is provided. A memory core array (12) includes a plurality of memory cells and a reference cell array (22) having a plurality of reference core cells which are selected together with a selected memory core cell. A precharge circuit (36a) is used to precharge all of the array bit lines and the reference bit lines to a predetermined potential prior to a program operation. A reference generator circuit (134) is used for selectively generating one of a plurality of target memory core cell bit line program-verify voltages, each one corresponding to one of a plurality of programmable memory states. A switching circuit (P1,N1) is used to selectively connect a program current source to the selected certain ones of the columns of array bit lines containing the selected memory core cells which are to be programmed. A sensing logic circuit (26,27) continuously compares a potential on one of the selected bit lines and one of the plurality of target program-verify voltages. The sensing logic circuit generates a logic signal which is switched to a low logic level when the potential on the selected bit line falls below the selected one of the plurality of target program-verify voltages. The switching circuit is responsive to the low logic level for disconnecting the program current source so as to inhibit further programming of the selected memory core cells.
摘要翻译：提供了一种改进的编程结构，用于执行多个比特单元闪存EEPROM存储单元阵列中的程序操作。存储器核心阵列（12）包括多个存储器单元和具有多个参考核心单元的参考单元阵列（22），所述参考单元阵列与选定的存储器核心单元一起选择。预充电电路（36a）用于在编程操作之前将所有阵列位线和参考位线预充电至预定电位。参考发生器电路（134）用于选择性地产生多个目标存储器核心单元位线程序验证电压中的一个，每一个对应于多个可编程存储器状态之一。切换电路（P1，N1）用于选择性地将程序电流源连接到包含要编程的所选择的存储器核心单元的阵列位线列中选定的某些列。感测逻辑电路（26,27）连续地比较所选位线之一上的电位和多个目标程序验证电压中的一个。感测逻辑电路产生逻辑信号，当所选位线上的电位低于多个目标程序验证电压中选定的一个时，逻辑信号被切换到低逻辑电平。开关电路响应于低逻辑电平以断开程序电流源，从而禁止进一步编程所选择的存储器核心单元。

24. 发明授权

US5059815A High voltage charge pumps with series capacitors 失效
标题翻译：具有串联电容器的高压充电泵
公开(公告)号：US5059815A
公开(公告)日：1991-10-22
申请号：US505335
申请日：1990-04-05
申请人： Colin S. Bill , Michael A. Van Buskirk , Antonio J. Montalvo
发明人： Colin S. Bill , Michael A. Van Buskirk , Antonio J. Montalvo
IPC分类号： H02M3/07 , G05F3/20 , H01L27/02
CPC分类号： G05F3/205 , H01L27/0222
摘要： A charge pump circuit is provided comprising a MOS capacitor, a capacitor ("series capacitor") connected in series, a MOSFET diode, and a voltage clamp connected to the common node of the MOS capacitor and the series capacitor. A number of these charge pump circuits may be cascaded to form a multi-stage charge pump circuit. Each charge pump circuit may attain output voltage higher than the oxide breakdown voltage of each individual MOS capacitor. This charge pump circuit can also operate under low voltage power supply conditions.

25. 发明授权

US07579631B2 Variable breakdown characteristic diode 有权
标题翻译：可变击穿特性二极管
公开(公告)号：US07579631B2
公开(公告)日：2009-08-25
申请号：US11087000
申请日：2005-03-22
申请人： David Gaun , Colin S. Bill , Swaroop Kaza
发明人： David Gaun , Colin S. Bill , Swaroop Kaza
IPC分类号： H01L29/00
CPC分类号： H01L51/0575 , B82Y10/00 , G11C11/5664 , G11C11/5692 , G11C13/0009 , G11C13/0014 , G11C13/0016 , G11C2213/11 , G11C2213/12 , G11C2213/15 , G11C2213/56 , G11C2213/71 , G11C2213/77 , H01L27/285
摘要： A memory cell made of at least two electrodes with a controllably conductive media between the at least two electrodes is disclosed. The controllably conductive media includes a passive layer made of super ionic material and an active layer. When an external stimuli, such as an applied electric field, is imposed upon the first and second electrode, ions move and dope and/or de-dope the polymer. The applied external stimuli used to dope the polymer is larger than an applied external stimuli to operate the memory cell. The polymer functions as a variable breakdown characteristic diode with electrical characteristics which are a consequence of the doping degree. The memory element may have a current limited read signal. Methods of making the memory devices/cells, methods of using the memory devices/cells, and devices such as computers, hand-held electronic devices and memory devices containing the memory cell(s) are also disclosed.
摘要翻译：公开了一种由在至少两个电极之间具有可控导电介质的至少两个电极制成的存储单元。可控导电介质包括由超离子材料和有源层制成的钝化层。当诸如施加的电场的外部刺激施加在第一和第二电极上时，离子移动并掺杂和/或去透明聚合物。用于掺杂聚合物的应用外部刺激物大于施加的外部刺激以操作记忆单元。该聚合物用作具有电特性的可变击穿特性二极管，这是掺杂度的结果。存储元件可以具有电流受限读取信号。还公开了制造存储器件/单元的方法，使用存储器件/单元的方法，以及诸如计算机，手持式电子设备和包含存储单元的存储器件的设备。

26. 发明授权

US07450416B1 Utilization of memory-diode which may have each of a plurality of different memory states 有权
标题翻译：利用可能具有多个不同存储器状态中的每一个的存储器二极管
公开(公告)号：US07450416B1
公开(公告)日：2008-11-11
申请号：US11021944
申请日：2004-12-23
申请人： Swaroop Kaza , Juri Krieger , David Gaun , Stuart Spitzer , Richard Kingsborough , Zhida Lan , Colin S. Bill , Wei Daisy Cai , Igor Sokolik
发明人： Swaroop Kaza , Juri Krieger , David Gaun , Stuart Spitzer , Richard Kingsborough , Zhida Lan , Colin S. Bill , Wei Daisy Cai , Igor Sokolik
IPC分类号： G11C11/34
CPC分类号： G11C11/36 , G11C11/56 , G11C13/02 , G11C2213/56 , G11C2213/72
摘要： The present invention is a method of undertaking a procedure on a memory-diode, wherein a memory-diode is provided which is programmable so as to have each of a plurality of different threshold voltages. A reading of the state of the memory-diode indicates the so determined threshold voltage of the memory-diode.
摘要翻译：本发明是一种在存储器二极管上进行程序的方法，其中提供可编程以便具有多个不同阈值电压中的每一个的存储器二极管。存储二极管的状态的读取指示存储二极管的阈值电压是如此确定的。

27. 发明授权

US07443710B2 Control of memory devices possessing variable resistance characteristics 有权
标题翻译：具有可变电阻特性的存储器件的控制
公开(公告)号：US07443710B2
公开(公告)日：2008-10-28
申请号：US10983919
申请日：2004-11-08
申请人： Tzu-Ning Fang , Michael Allen Van Buskirk , Colin S. Bill
发明人： Tzu-Ning Fang , Michael Allen Van Buskirk , Colin S. Bill
IPC分类号： G11C11/00
CPC分类号： G11C11/5664 , B82Y10/00 , G11C13/0014 , G11C13/0069 , G11C13/0097 , G11C2013/0071 , G11C2013/0078 , G11C2213/15 , G11C2213/79
摘要： Systems and methods employing at least one constant current source to facilitate programming of an organic memory cell and/or employing at least one constant voltage source to facilitate erasing of a memory device. The present invention is utilized in single memory cell devices and memory cell arrays. Employing a constant current source prevents current spikes during programming and allows accurate control of a memory cell's state during write cycles, independent of the cell's resistance. Employing a constant voltage source provides a stable load for memory cells during erase cycles and allows for accurate voltage control across the memory cell despite large dynamic changes in cell resistance during the process.
摘要翻译：采用至少一个恒定电流源的系统和方法促进有机存储器单元的编程和/或采用至少一个恒定电压源以便于擦除存储器件。本发明用于单个存储器单元装置和存储单元阵列。使用恒流源防止编程期间的电流尖峰，并允许在写周期期间精确控制存储单元的状态，而与电池的电阻无关。使用恒定电压源在擦除周期期间为存储器单元提供稳定的负载，并且允许跨过存储器单元的精确的电压控制，尽管在该过程中电池电阻的大的动态变化。

28. 发明申请

US20080151669A1 USE OF PERIODIC REFRESH IN MEDIUM RETENTION MEMORY ARRAYS 有权
标题翻译：在中继记忆阵列中使用周期性刷新
公开(公告)号：US20080151669A1
公开(公告)日：2008-06-26
申请号：US11613832
申请日：2006-12-20
申请人： Colin S. Bill , Swaroop Kaza , Wei Daisy Cai , Tzu-Ning Fang , David Gaun , Eugen Gershon , Michael A. Van Buskirk , Jean Wu
发明人： Colin S. Bill , Swaroop Kaza , Wei Daisy Cai , Tzu-Ning Fang , David Gaun , Eugen Gershon , Michael A. Van Buskirk , Jean Wu
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40615 , G11C13/0033 , G11C13/0069 , G11C16/3431
摘要： Systems and methods are disclosed that facilitate extending data retention time in a data retention device, such as a nanoscale resistive memory cell array, via assessing a resistance level in a tracking element associated with the memory array and refreshing the memory array upon a determination that the resistance of the tracking element has reached or exceeded a predetermined reference threshold resistance value. The tracking element can be a memory cell within the array itself and can have an initial resistance value that is substantially higher than an initial resistance value for a programmed memory cell in the array, such that resistance increase in the tracking cell will cause the tracking cell to reach the threshold value and trigger refresh of the array before data corruption/loss occurs in the core memory cells.
摘要翻译：公开了通过评估与存储器阵列相关联的跟踪元件中的电阻水平并在确定存储器阵列的情况下刷新存储器阵列时有助于在诸如纳米级电阻存储器单元阵列之类的数据保持装置中扩展数据保留时间的系统和方法跟踪元件的电阻已达到或超过预定参考阈值电阻值。跟踪元件可以是阵列本身内的存储器单元，并且可以具有基本上高于阵列中的编程存储器单元的初始电阻值的初始电阻值，使得跟踪单元中的电阻增加将导致跟踪单元在核心存储器单元中发生数据损坏/丢失之前达到阈值并触发阵列刷新。

29. 发明授权

US07379317B2 Method of programming, reading and erasing memory-diode in a memory-diode array 有权
标题翻译：在存储二极管阵列中编程，读取和擦除存储二极管的方法
公开(公告)号：US07379317B2
公开(公告)日：2008-05-27
申请号：US11021958
申请日：2004-12-23
申请人： Colin S. Bill , Swaroop Kaza , Tzu-Ning Fang , Stuart Spitzer
发明人： Colin S. Bill , Swaroop Kaza , Tzu-Ning Fang , Stuart Spitzer
IPC分类号： G11C5/06 , G11C17/06
CPC分类号： G11C11/36
摘要： A memory array includes first and second sets of conductors and a plurality of memory-diodes, each connecting in a forward direction a conductor of the first set with a conductor of the second set. An electrical potential is applied across a selected memory-diode, from higher to lower potential in the forward direction, intended to program the selected memory-diode. During this intended programming, each other memory-diode in the array has provided thereacross in the forward direction thereof an electrical potential lower than its threshold voltage. The threshold voltage of each memory-diode can be established by applying an electrical potential across that memory-diode from higher to lower potential in the reverse direction. By so establishing a sufficient threshold voltage, and by selecting appropriate electrical potentials applied to conductors of the array, problems related to current leakage and disturb are avoided.
摘要翻译：存储器阵列包括第一和第二组导体和多个存储器二极管，每个存储器二极管以正向方向连接第一组的导体与第二组的导体。在选定的存储器二极管上施加电位，从正向上的较高电位到较低的电位，用于对所选存储二极管进行编程。在该期望的编程期间，阵列中的每个其它存储器二极管在其正向方向上提供低于其阈值电压的电位。每个存储器二极管的阈值电压可以通过在该存储器二极管上从相反方向上从较高电位向较低电位施加电位来建立。通过这样建立足够的阈值电压，并且通过选择适用于阵列导体的适当电位，避免了与电流泄漏和干扰有关的问题。

30. 发明授权

US07286388B1 Resistive memory device with improved data retention 有权
标题翻译：具有改善数据保持性的电阻式存储器件
公开(公告)号：US07286388B1
公开(公告)日：2007-10-23
申请号：US11165005
申请日：2005-06-23
申请人： An Chen , Sameer Haddad , Tzu-Ning Fang , Yi-Ching Jean Wu , Colin S. Bill
发明人： An Chen , Sameer Haddad , Tzu-Ning Fang , Yi-Ching Jean Wu , Colin S. Bill
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/02 , G11C2013/009 , G11C2213/11 , G11C2213/56 , G11C2213/79
摘要： In the present method of programming a memory device from an erased state, the memory device includes first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second electrodes. In the programming method, (i) an electrical potential is applied across the first and second electrodes from higher to lower potential in one direction to reduce the resistance of the memory device, and (ii) an electrical potential is applied across the first and second electrodes from higher to lower potential in the other direction to further reduce the resistance of the memory device.
摘要翻译：在从擦除状态编程存储器件的本方法中，存储器件包括第一和第二电极，第一和第二电极之间的无源层以及第一和第二电极之间的有源层。在编程方法中，（i）在一个方向上跨越第一和第二电极施加电位从较高电位到较低的电位，以减小存储器件的电阻，并且（ii）电势跨越第一和第二电极在另一个方向从较高电位变为较低电位，以进一步降低存储器件的电阻。

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