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21. 发明申请

US20120300349A1 GATE DIELECTRIC BREAKDOWN PROTECTION DURING ESD EVENTS 有权
标题翻译：防静电事件期间门电绝缘保护
公开(公告)号：US20120300349A1
公开(公告)日：2012-11-29
申请号：US13115492
申请日：2011-05-25
申请人： Michel J. Abou-Khalil , James P. Di Sarro , Robert J. Gauthier, JR. , Junjun Li , Souvick Mitra , Yang Yang
发明人： Michel J. Abou-Khalil , James P. Di Sarro , Robert J. Gauthier, JR. , Junjun Li , Souvick Mitra , Yang Yang
IPC分类号： H02H9/00 , G06F17/50
CPC分类号： H02H9/046 , G06F17/5063 , H01L27/0285
摘要： Protection circuits, design structures, and methods for isolating the gate and gate dielectric of a field-effect transistor from electrostatic discharge (ESD). A protection field-effect transistor is located between a protected field-effect transistor and a voltage rail. Under normal operating conditions, the protection field-effect transistor is saturated so that the protected field-effect transistor is coupled to the voltage rail. The protection field-effect transistor may be driven into a cutoff condition in response to an ESD event while the chip is unpowered, which increases the series resistance of an ESD current path between the gate of the protected field-effect transistor and the voltage rail. The voltage drop across the protection field-effect transistor may reduce the ESD stress on the gate dielectric of the protected field-effect transistor. Alternatively, the gate and source of an existing field-effect transistor are selectively coupled provide ESD isolation to the protected field-effect transistor.
摘要翻译：用于将场效应晶体管的栅极和栅极电介质与静电放电（ESD）隔离的保护电路，设计结构和方法。保护场效应晶体管位于受保护的场效应晶体管和电压轨之间。在正常工作条件下，保护场效应晶体管饱和，使受保护的场效应晶体管耦合到电压轨。保护场效应晶体管可以在芯片无电源时响应于ESD事件而被驱动成截止状态，这增加了受保护的场效应晶体管的栅极与电压轨之间的ESD电流路径的串联电阻。保护场效应晶体管两端的电压降可以降低受保护的场效应晶体管的栅极电介质上的ESD应力。或者，现有的场效应晶体管的栅极和源极被选择性地耦合到提供ESD隔离到受保护的场效应晶体管。

22. 发明申请

US20110185332A1 MODEL BASED SIMULATION AND OPTIMIZATION METHODOLOGY FOR DESIGN CHECKING 有权
标题翻译：基于模型的模拟和优化方法设计检查
公开(公告)号：US20110185332A1
公开(公告)日：2011-07-28
申请号：US12695494
申请日：2010-01-28
申请人： Robert J. Gauthier, JR. , Bradford L. Hunter , Amol A. Joshi , Junjun Li , Gregory Joseph Schroer
发明人： Robert J. Gauthier, JR. , Bradford L. Hunter , Amol A. Joshi , Junjun Li , Gregory Joseph Schroer
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method, apparatus and program product are provided for simulating a circuit. A plurality of elements of the circuit is represented by device models including pass/fail criteria. A circuit simulation program is executed on a hardware implemented processor where the circuit simulation program is configured to obtain simulation results from the device models in response to applied parameters. The circuit simulation program identifies a failure of one or more of the plurality of elements of the circuit based on the pass/fail criteria of the device models. The circuit simulation program is further configured to output the failures during simulation of the one or more of the plurality of elements that are identified in response to the applied parameters.
摘要翻译：提供了一种用于模拟电路的方法，装置和程序产品。电路的多个元件由包括通过/不合格标准的器件模型表示。在硬件实现的处理器上执行电路仿真程序，其中电路仿真程序被配置为响应于所应用的参数从设备模型获得仿真结果。电路仿真程序基于设备模型的通过/不合格标准来识别电路的多个元件中的一个或多个元件的故障。电路仿真程序还被配置为在模拟响应于所应用的参数识别的多个元件中的一个或多个元件期间输出故障。

23. 发明申请

US20090310267A1 METHOD, DESIGN STRUCTURES, AND SYSTEMS FOR CURRENT MODE LOGIC (CML) DIFFERENTIAL DRIVER ESD PROTECTION CIRCUITRY 失效
标题翻译：电流模式逻辑（CML）差分驱动器ESD保护电路的方法，设计结构和系统
公开(公告)号：US20090310267A1
公开(公告)日：2009-12-17
申请号：US12140485
申请日：2008-06-17
申请人： Robert J. Gauthier, JR. , Junjun Li , Ankit Srivastava
发明人： Robert J. Gauthier, JR. , Junjun Li , Ankit Srivastava
IPC分类号： H02H9/00
CPC分类号： H03F3/45188 , H01L27/0251 , H03F1/52 , H03F1/523 , H03F2203/45466 , H03F2203/45486 , H03F2203/45504
摘要： A hardware description language (HDL) design structure encoded on a machine readable data storage medium, the HDL design comprising elements that when processed in a computer aided design system generates a machine executable representation of a device for implementing dynamic refresh protocols for DRAM based cache. The HDL design structure further comprises an integrated circuit having a differential driver, comprising: a first driver and a second driver forming the differential driver, the drivers are coupled in parallel between a first voltage source and a second voltage source; a first switch coupled to the first driver and configured to turn off the first driver during an ESD event such that the first driver sustains stress during the ESD event; and a second switch coupled to the second driver and configured to turn off the second driver during the ESD event such that the second driver sustains stress during the ESD event.
摘要翻译：在机器可读数据存储介质上编码的硬件描述语言（HDL）设计结构，所述HDL设计包括在计算机辅助设计系统中处理时的元件，生成用于实现基于DRAM的高速缓存的动态刷新协议的设备的机器可执行表示。 HDL设计结构还包括具有差分驱动器的集成电路，包括：形成差分驱动器的第一驱动器和第二驱动器，驱动器并联耦合在第一电压源和第二电压源之间; 第一开关，其耦合到所述第一驱动器并且被配置为在ESD事件期间关闭所述第一驱动器，使得所述第一驱动器在所述ESD事件期间保持应力; 以及耦合到所述第二驱动器并被配置为在所述ESD事件期间关闭所述第二驱动器的第二开关，使得所述第二驱动器在所述ESD事件期间维持应力。

24. 发明申请

US20090302416A1 Programmable Electrical Fuse 有权
标题翻译：可编程电气保险丝
公开(公告)号：US20090302416A1
公开(公告)日：2009-12-10
申请号：US12135242
申请日：2008-06-09
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , William Tonti
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , William Tonti
IPC分类号： H01L23/525 , H01L21/44
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to e-fuse devices, and more particularly to a device and method of forming an e-fuse device, the method comprising providing a first conductive layer connected to a second conductive layer, the first and second conductive layers separated by a barrier layer having a first diffusivity different than a second diffusivity of the first conductive layer. A void is created in the first conductive layer by driving an electrical current through the e-fuse device.
摘要翻译：本发明涉及电熔丝装置，更具体地说，涉及一种形成电熔丝装置的装置和方法，所述方法包括提供连接到第二导电层的第一导电层，所述第一和第二导电层由阻挡层具有与第一导电层的第二扩散率不同的第一扩散率。通过驱动电流通过电熔丝装置而在第一导电层中产生空隙。

25. 发明申请

US20090179267A1 SEMICONDUCTOR-ON-INSULATOR HIGH-VOLTAGE DEVICE STRUCTURES, METHODS OF FABRICATING SUCH DEVICE STRUCTURES, AND DESIGN STRUCTURES FOR HIGH-VOLTAGE CIRCUITS 失效
标题翻译：半导体绝缘体高压器件结构，制造这种器件结构的方法以及高压电路的设计结构
公开(公告)号：US20090179267A1
公开(公告)日：2009-07-16
申请号：US12013101
申请日：2008-01-11
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Christopher S. Putnam , Mitra Souvick
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Christopher S. Putnam , Mitra Souvick
IPC分类号： H01L27/12 , H01L21/786
CPC分类号： H01L27/1203 , H01L21/84
摘要： High-voltage device structures, methods for fabricating such device structures using complementary metal-oxide-semiconductor (CMOS) processes, and design structures for high-voltage circuits. The planar device structure, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a semiconductor body positioned between two gate electrodes. The gate electrodes and the semiconductor body may be formed from the monocrystalline SOI layer of the SOI substrate. A dielectric layer separates each of the gate electrodes from the semiconductor body. These dielectric layers are formed by defining trenches in the SOI layer and filling the trenches with a dielectric material, which may occur concurrent with a process forming device isolation regions.
摘要翻译：高电压器件结构，使用互补金属氧化物半导体（CMOS）工艺制造这种器件结构的方法，以及高压电路的设计结构。使用绝缘体上半导体（SOI）衬底形成的平面器件结构包括位于两个栅电极之间的半导体本体。栅电极和半导体本体可以由SOI衬底的单晶SOI层形成。电介质层将每个栅电极与半导体本体分开。这些电介质层通过在SOI层中限定沟槽并用介电材料填充沟槽而形成，其可以与形成器件隔离区的工艺同时发生。

26. 发明申请

US20090140338A1 METHOD OF FABRICATING PATTERNED SOI DEVICES AND THE RESULTING DEVICE STRUCTURES 失效
标题翻译：制作图案化SOI器件的方法和结果的器件结构
公开(公告)号：US20090140338A1
公开(公告)日：2009-06-04
申请号：US11949973
申请日：2007-12-04
申请人： Robert J. Gauthier, JR. , Rajendran Krishnasamy
发明人： Robert J. Gauthier, JR. , Rajendran Krishnasamy
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/7848 , H01L21/26533 , H01L21/76243 , H01L21/76267 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L29/165 , H01L29/66575 , H01L29/66636 , H01L29/78
摘要： A method and resulting structure for fabricating a FET transistor for an integrated circuit on a silicon oxide (SOI) substrate comprising the steps of forming recesses in a substrate on both sides of a gate on the substrate, implanting oxygen ions into the recesses, and annealing the substrate to convert the oxygen ions into a SOI layer below each recess.
摘要翻译：一种用于制造氧化硅（SOI）衬底上的集成电路的FET晶体管的方法和结果，包括以下步骤：在衬底上的栅极两侧的衬底中形成凹槽，将氧离子注入到凹槽中，并退火将氧离子转换成每个凹槽下方的SOI层的衬底。

27. 发明申请

US20090089719A1 Structure for a Stacked Power Clamp Having a BigFET Gate Pull-Up Circuit 有权
标题翻译：具有BigFET栅极上拉电路的堆叠电源钳位的结构
公开(公告)号：US20090089719A1
公开(公告)日：2009-04-02
申请号：US12127245
申请日：2008-05-27
申请人： Robert J. Gauthier, JR. , Junjun Li
发明人： Robert J. Gauthier, JR. , Junjun Li
IPC分类号： H02H9/00 , G06F17/50
CPC分类号： G06F17/5045 , H01L27/0285 , H01L2924/0002 , H01L2924/00
摘要： Design structure for an electrostatic discharge (ESD) protection circuit for protecting an integrated circuit chip from an ESD event. The design structure for the ESD protection circuit includes a stack of BigFETs, a BigFET gate driver for driving the gates of the BigFETs, and a trigger for triggering the BigFET gate driver to drive the gates of the BigFETs in response to an ESD event. The BigFET gate driver includes gate pull-up circuitry for pulling up the gate of a lower one of the BigFETs. The gate pull-up circuitry is configured so as to obviate the need for a diffusion contact between the stacked BigFETs, resulting in a significant savings in terms of the chip area needed to implement the ESD protection circuit.
摘要翻译：用于保护集成电路芯片免受ESD事件的静电放电（ESD）保护电路的设计结构。 ESD保护电路的设计结构包括一堆BigFET，用于驱动BigFET栅极的BigFET栅极驱动器，以及用于触发BigFET栅极驱动器以响应于ESD事件来驱动BigFET栅极的触发器。 BigFET栅极驱动器包括用于拉低下一个BigFET的栅极的栅极上拉电路。栅极上拉电路被配置为消除对堆叠的BigFET之间的扩散接触的需要，导致实现ESD保护电路所需的芯片面积的显着节省。

28. 发明申请

US20130285211A1 DEVICE STRUCTURES COMPATIBLE WITH FIN-TYPE FIELD-EFFECT TRANSISTOR TECHNOLOGIES 有权
标题翻译：与FIN型场效应晶体管技术兼容的器件结构
公开(公告)号：US20130285211A1
公开(公告)日：2013-10-31
申请号：US13455732
申请日：2012-04-25
申请人： Robert J. Gauthier, JR. , Jeffrey B. Johnson , Junjun Li
发明人： Robert J. Gauthier, JR. , Jeffrey B. Johnson , Junjun Li
IPC分类号： H01L29/00 , G06F17/50 , H01L21/20
CPC分类号： H01L27/1211 , G06F17/5068 , H01L21/3086 , H01L21/845
摘要： Device structures, design structures, and fabrication methods for fin-type field-effect transistor integrated circuit technologies. First and second fins, which constitute electrodes of the device structure, are each comprised of a first semiconductor material. The second fin is formed adjacent to the first fin to define a gap separating the first and second fins. Positioned in the gap is a layer comprised of a second semiconductor material.
摘要翻译：鳍式场效应晶体管集成电路技术的器件结构，设计结构和制造方法。构成器件结构的电极的第一和第二鳍片均由第一半导体材料构成。第二翅片邻近第一翅片形成以限定分隔第一和第二翅片的间隙。位于间隙中的是由第二半导体材料构成的层。

29. 发明申请

US20130271883A1 INTEGRATED CIRCUIT PROTECTION DURING HIGH-CURRENT ESD TESTING 有权
标题翻译：在高电流ESD测试期间的集成电路保护
公开(公告)号：US20130271883A1
公开(公告)日：2013-10-17
申请号：US13446394
申请日：2012-04-13
申请人： Shunhua Chang , James Paul Di Sarro , Robert J. Gauthier, JR. , Nathan Jack , Souvick Mitra
发明人： Shunhua Chang , James Paul Di Sarro , Robert J. Gauthier, JR. , Nathan Jack , Souvick Mitra
IPC分类号： H02H9/04
CPC分类号： G01R31/002 , G01R31/2851 , H01L27/0248 , H02H9/046 , H05K9/0067
摘要： A method of protecting devices within an integrated circuit during electro-static discharge (ESD) testing using an ESD test system is provided. The method includes applying a direct current (DC) bias voltage to an input of at least one device of the integrated circuit and applying an ESD simulated signal to at least one other input of the integrated circuit. The applied ESD simulated signal is conducted along a first current path to a first ground, while a low-current signal associated with the at least one device is conducted along a second current path to the second ground. The DC bias voltage is maintained between the input of the at least one device and the second ground at a substantially constant value in response to a signal variation on the second ground that results from the applied ESD simulated signal.
摘要翻译：提供了使用ESD测试系统在静电放电（ESD）测试期间保护集成电路内的器件的方法。该方法包括将直流（DC）偏置电压施加到集成电路的至少一个器件的输入，并将ESD仿真信号施加到集成电路的至少一个其他输入。施加的ESD模拟信号沿着第一电流路径传导到第一地，而与至少一个装置相关联的低电流信号沿着第二电流路径传导到第二地。响应于由所施加的ESD模拟信号产生的第二接地上的信号变化，DC偏置电压在至少一个器件的输入和第二接地之间以基本恒定的值保持。

30. 发明申请

US20130020645A1 ESD FIELD-EFFECT TRANSISTOR AND INTEGRATED DIFFUSION RESISTOR 有权
标题翻译： ESD场效应晶体管和集成扩散电阻
公开(公告)号：US20130020645A1
公开(公告)日：2013-01-24
申请号：US13188094
申请日：2011-07-21
申请人： John B. Campi, JR. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Rahul Mishra , Junjun Li , Mujahid Muhammad
发明人： John B. Campi, JR. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Rahul Mishra , Junjun Li , Mujahid Muhammad
IPC分类号： H01L29/772 , G06F9/45 , H01L21/336
CPC分类号： H01L29/41775 , H01L27/0266 , H01L29/1087 , H01L29/66659 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge protection device, methods of fabricating an electrostatic discharge protection device, and design structures for an electrostatic discharge protection device. A drain of a first field-effect transistor and a diffusion resistor of higher electrical resistance may be formed as different portions of a doped region. The diffusion resistor, which is directly coupled with the drain of the first field-effect transistor, may be defined using an isolation region of dielectric material disposed in the doped region and selective silicide formation. The electrostatic discharge protection device may also include a second field-effect transistor having a drain as a portion the doped region that is directly coupled with the diffusion resistor and indirectly coupled by the diffusion resistor with the drain of the first field-effect transistor.
摘要翻译：静电放电保护装置，静电放电保护装置的制造方法以及静电放电保护装置的设计结构。第一场效应晶体管的漏极和较高电阻的扩散电阻可以形成为掺杂区域的不同部分。可以使用布置在掺杂区域中的介电材料的隔离区域和选择性硅化物形成来限定与第一场效应晶体管的漏极直接耦合的扩散电阻器。静电放电保护器件还可以包括第二场效应晶体管，其具有作为与扩散电阻器直接耦合并且由扩散电阻器与第一场效应晶体管的漏极间接耦合的掺杂区域的一部分的漏极。

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