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21. 发明申请

US20110223706A1 METHOD OF FORMING A PHOTODETECTOR 审中-公开
标题翻译：形成光电转换器的方法
公开(公告)号：US20110223706A1
公开(公告)日：2011-09-15
申请号：US12721278
申请日：2010-03-10
申请人： JILL C. HILDRETH , Stanley M. Filipiak , Marc A. Rossow , Gregory S. Spencer , Bret T. Wilkerson
发明人： JILL C. HILDRETH , Stanley M. Filipiak , Marc A. Rossow , Gregory S. Spencer , Bret T. Wilkerson
IPC分类号： H01L31/18
CPC分类号： H01L31/1812 , H01L31/028 , Y02E10/547
摘要： A photodetector is formed to have a germanium detector on a waveguide. The germanium detector has a first surface on the waveguide and a second surface that, when exposed to ambient conditions, forms germanium oxide. In a processing platform, an oxygen-free plasma is applied to the second surface. The oxygen-free plasma removes oxygen that is bonded to germanium at the second surface. A cap layer is formed on the second surface prior to removing the germanium detector from the processing platform.
摘要翻译：光电检测器形成为在波导上具有锗检测器。锗探测器具有波导上的第一表面和暴露于环境条件时形成氧化锗的第二表面。在处理平台中，将无氧等离子体施加到第二表面。无氧等离子体去除在第二表面与锗结合的氧。在从处理平台移除锗检测器之前，在第二表面上形成盖层。

22. 发明授权

US07846803B2 Multiple millisecond anneals for semiconductor device fabrication 有权
标题翻译：用于半导体器件制造的多毫秒退火
公开(公告)号：US07846803B2
公开(公告)日：2010-12-07
申请号：US11756197
申请日：2007-05-31
申请人： Gregory S. Spencer , Vishal P. Trivedi
发明人： Gregory S. Spencer , Vishal P. Trivedi
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L21/324 , H01L29/6659 , H01L29/7833
摘要： A method of forming a doped region includes, in one embodiment, implanting a dopant into a region in a semiconductor substrate, recrystallizing the region by performing a first millisecond anneal, wherein the first millisecond anneal has a first temperature and a first dwell time, and activating the region using as second millisecond anneal after recrystallizing the region, wherein the second millisecond anneal has a second temperature and a second dwell time. In one embodiment, the first millisecond anneal and the second millisecond anneal use a laser. In one embodiment, the first temperature is the same as the second temperature and the first dwell time is the same as the second dwell time. In another embodiment, the first temperature is different from the second temperature and the first dwell time is different from the second dwell time.
摘要翻译：在一个实施例中，形成掺杂区域的方法包括：将掺杂剂注入到半导体衬底中的区域中，通过执行第一毫秒退火使该区域再结晶，其中第一毫秒退火具有第一温度和第一停留时间，以及在重新区域之后使用第二毫秒退火来激活该区域，其中第二毫秒退火具有第二温度和第二停留时间。在一个实施例中，第一毫秒退火和第二毫秒退火使用激光。在一个实施例中，第一温度与第二温度相同，并且第一停留时间与第二停留时间相同。在另一实施例中，第一温度与第二温度不同，第一停留时间不同于第二停留时间。

23. 发明申请

US20080274595A1 Dual substrate orientation or bulk on SOI integrations using oxidation for silicon epitaxy spacer formation 有权
标题翻译：使用氧化硅外延隔离层形成的SOI集成上的双衬底取向或体积
公开(公告)号：US20080274595A1
公开(公告)日：2008-11-06
申请号：US11742778
申请日：2007-05-01
申请人： Gregory S. Spencer , John M. Grant , Gauri V. Karve
发明人： Gregory S. Spencer , John M. Grant , Gauri V. Karve
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/76283 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L27/1207
摘要： A semiconductor process and apparatus provide a planarized hybrid substrate (15) by thermally oxidizing SOI sidewalls (90) in a trench opening (93) to form SOI sidewall oxide spacers (94) which are trimmed while etching through a buried oxide layer (80) to expose the underlying bulk substrate (70) for subsequent epitaxial growth of an epitaxial semiconductor layer (96). In this way, SOI sidewall oxide spacers (94) are formed that prevent epitaxial SOI sidewalls from being formed in the trench opening (93) during the epitaxial growth step, and that can be readily removed during any subsequent STI etch process
摘要翻译：半导体工艺和装置通过在沟槽开口（93）中热氧化SOI侧壁（90）来提供平坦化的混合衬底（15），以形成SOI侧壁氧化物间隔物（94），其在蚀刻通过掩埋氧化物层（80）时被修整，以暴露下面的体基板（70），用于外延半导体层（96）的后续外延生长。以这种方式，形成了在外延生长步骤期间防止在沟槽开口（93）中形成外延SOI侧壁的SOI侧壁氧化物间隔物（94），并且可以在任何后续STI蚀刻工艺期间容易地去除

24. 发明授权

US07416605B2 Anneal of epitaxial layer in a semiconductor device 有权
标题翻译：在半导体器件中退火外延层
公开(公告)号：US07416605B2
公开(公告)日：2008-08-26
申请号：US11620987
申请日：2007-01-08
申请人： Stefan Zollner , Veeraraghavan Dhandapani , Paul A. Grudowski , Gregory S. Spencer
发明人： Stefan Zollner , Veeraraghavan Dhandapani , Paul A. Grudowski , Gregory S. Spencer
IPC分类号： C30B25/14 , C30B25/12
CPC分类号： H01L29/7848 , H01L29/1054 , H01L29/665 , H01L29/66636 , H01L29/7834
摘要： An anneal of an epitaxially grown crystalline semiconductor layer comprising a combination of group-IV elements. The layer contains at least one of the group of carbon and tin. The layer of epitaxially grown material is annealed at a temperature substantially in a range of 1,000 to 1,400 degrees Celsius for a period not to exceed 100 milliseconds within 10% of the peak temperature. The anneal is performed for example with a laser anneal or a flash lamp anneal. The limited-time anneal may improve carrier mobility of a transistor.
摘要翻译：包含IV族元素组合的外延生长的晶体半导体层的退火。该层含有碳和锡中的至少一种。外延生长材料层在峰值温度的10％以内，在1000〜1400摄氏度的温度下退火不超过100毫秒。退火例如通过激光退火或闪光灯退火来进行。有限时间退火可以改善晶体管的载流子迁移率。

25. 发明授权

US06992003B2 Integration of ultra low K dielectric in a semiconductor fabrication process 失效
标题翻译：在半导体制造工艺中集成超低K电介质
公开(公告)号：US06992003B2
公开(公告)日：2006-01-31
申请号：US10659885
申请日：2003-09-11
申请人： Gregory S. Spencer , Kurt H. Junker , Jason A. Vires
发明人： Gregory S. Spencer , Kurt H. Junker , Jason A. Vires
IPC分类号： H01L21/302
CPC分类号： H01L21/02164 , H01L21/02126 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/31053 , H01L21/3122 , H01L21/31633 , H01L21/76832
摘要： A backend semiconductor fabrication process includes forming an interlevel dielectric (ILD) overlying a wafer substrate by forming a low K dielectric (K
摘要翻译：后端半导体制造工艺包括通过在晶片的衬底上形成覆盖在低K电介质上的有机氧化硅胶层而形成覆盖在晶片衬底上的层间电介质（ILD），形成覆盖晶片衬底的低K电介质（K <3.0），以及形成覆盖胶层电介质的CMP阻挡层电介质。然后在ILD中形成空隙，沉积导电材料以填充空隙，并且抛光工艺除去过量的导电材料。通过使用有机前体和氧前体形成CVD等离子体并且通过形成胶层电介质和停止层来保持等离子体来实现形成胶层电介质和CMP停止层电介质。有机前体的流速相对于氧气前体流速减小以形成基本上不含碳的CMP停止层。

26. 发明授权

US08722530B2 Method of making a die with recessed aluminum die pads 有权
标题翻译：用凹槽铝模片制作模具的方法
公开(公告)号：US08722530B2
公开(公告)日：2014-05-13
申请号：US13192976
申请日：2011-07-28
申请人： Gregory S. Spencer , Phillip E. Crabtree , Dean J. Denning , Kurt H. Junker , Gerald A. Martin
发明人： Gregory S. Spencer , Phillip E. Crabtree , Dean J. Denning , Kurt H. Junker , Gerald A. Martin
IPC分类号： H01L23/48 , H01L33/62 , H01L21/768 , H01L23/488
CPC分类号： H01L21/76879 , H01L21/31053 , H01L21/31056 , H01L21/76804 , H01L21/76885 , H01L24/03 , H01L24/05 , H01L2224/02166 , H01L2224/0345 , H01L2224/0362 , H01L2224/0391 , H01L2224/0392 , H01L2224/0401 , H01L2224/04042 , H01L2224/05556 , H01L2224/05567 , H01L2224/05572 , H01L2224/05582 , H01L2224/05624 , H01L2224/05681 , H01L2224/05686 , H01L2924/00014 , H01L2924/1305 , H01L2924/1461 , H01L2924/00012 , H01L2924/04941 , H01L2924/01029 , H01L2924/00 , H01L2224/05552
摘要： A method for making a semiconductor device comprises forming an electrical interconnect layer, forming a first dielectric layer over the interconnect layer, forming an opening in the first dielectric layer over a first electrical interconnect of the interconnect layer, forming an aluminum layer over the first dielectric layer, etching the aluminum layer to form an aluminum die pad, forming a second dielectric layer over the aluminum die pad and the first dielectric layer, and forming a conductive via through the first and second dielectric layers to contact a second electrical interconnect of the interconnect layer.
摘要翻译：制造半导体器件的方法包括形成电互连层，在互连层上形成第一介电层，在互连层的第一电互连上在第一介电层中形成开口，在第一电介质上形成铝层蚀刻所述铝层以形成铝管芯焊盘，在所述铝管芯焊盘和所述第一介电层上形成第二电介质层，以及通过所述第一和第二电介质层形成导电通孔以接触所述互连的第二电互连层。

27. 发明授权

US08242564B2 Semiconductor device with photonics 有权
标题翻译：具有光子学的半导体器件
公开(公告)号：US08242564B2
公开(公告)日：2012-08-14
申请号：US13313806
申请日：2011-12-07
申请人： Gregory S. Spencer , Jill C. Hildreth , Robert E. Jones
发明人： Gregory S. Spencer , Jill C. Hildreth , Robert E. Jones
IPC分类号： H01L27/12
CPC分类号： G02B6/12004 , H01L21/76283 , H01L27/1203 , H01L31/028 , H01L31/112
摘要： A semiconductor structure having a transistor region and an optical device region includes a transistor in a first semiconductor layer of the semiconductor structure, wherein the first semiconductor layer is over a first insulating layer, the first insulating layer is over a second semiconductor layer, and the second semiconductor layer is over a second insulating layer. A gate dielectric of the transistor is in physical contact with a top surface of the first semiconductor layer, and the transistor is formed in the transistor region of the semiconductor structure. A waveguide device in the optical device region and a third semiconductor layer over a portion of the second semiconductor layer.
摘要翻译：具有晶体管区域和光学器件区域的半导体结构包括在半导体结构的第一半导体层中的晶体管，其中第一半导体层在第一绝缘层之上，第一绝缘层在第二半导体层上，并且第二半导体层在第二绝缘层之上。晶体管的栅极电介质与第一半导体层的顶表面物理接触，并且晶体管形成在半导体结构的晶体管区域中。光学器件区域中的波导器件和第二半导体层的一部分上的第三半导体层。

28. 发明申请

US20080163813A1 ANNEAL OF EPITAXIAL LAYER IN A SEMICONDUCTOR DEVICE 有权
标题翻译：外延层在半导体器件中的退火
公开(公告)号：US20080163813A1
公开(公告)日：2008-07-10
申请号：US11620987
申请日：2007-01-08
申请人： Stefan Zollner , Veeraraghavan Dhandapani , Paul A. Grudowski , Gregory S. Spencer
发明人： Stefan Zollner , Veeraraghavan Dhandapani , Paul A. Grudowski , Gregory S. Spencer
IPC分类号： H01L21/02 , C30B19/12
CPC分类号： H01L29/7848 , H01L29/1054 , H01L29/665 , H01L29/66636 , H01L29/7834
摘要： An anneal of an epitaxially grown crystalline semiconductor layer comprising a combination of group-IV elements. The layer contains at least one of the group of carbon and tin. The layer of epitaxially grown material is annealed at a temperature substantially in a range of 1,000 to 1,400 degrees Celsius for a period not to exceed 100 milliseconds within 10% of the peak temperature. The anneal is performed for example with a laser anneal or a flash lamp anneal. The limited-time anneal may improve carrier mobility of a transistor.
摘要翻译：包含IV族元素组合的外延生长的晶体半导体层的退火。该层含有碳和锡中的至少一种。外延生长材料层在峰值温度的10％以内，在1000〜1400摄氏度的温度下退火不超过100毫秒。退火例如通过激光退火或闪光灯退火来进行。有限时间退火可以改善晶体管的载流子迁移率。

29. 发明授权

US07378306B2 Selective silicon deposition for planarized dual surface orientation integration 有权
标题翻译：用于平面化双面取向积分的选择性硅沉积
公开(公告)号：US07378306B2
公开(公告)日：2008-05-27
申请号：US11375763
申请日：2006-03-14
申请人： Gregory S. Spencer , Peter J. Beckage , Mariam G. Sadaka , Veer Dhandapani
发明人： Gregory S. Spencer , Peter J. Beckage , Mariam G. Sadaka , Veer Dhandapani
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L27/1207
摘要： A semiconductor process and apparatus provide a planarized hybrid substrate (225) having a more uniform polish surface (300) by thickening an SOI semiconductor layer (210) in relation to a previously or subsequently formed epitaxial silicon layer (220) with a selective silicon deposition process that covers the SOI semiconductor layer (210) with a crystalline semiconductor layer (216). By forming first gate electrodes (151) over a first SOI substrate (90) using deposited (100) silicon and forming second gate electrodes (161) over an epitaxially grown (110) silicon substrate (70), a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes (161) having improved hole mobility.
摘要翻译：半导体工艺和设备通过使用选择性硅沉积物相对于先前或随后形成的外延硅层（220）增厚SOI半导体层（210）来提供具有更均匀的抛光表面（300）的平坦化的混合衬底（225）用SOI晶体半导体层（216）覆盖SOI半导体层（210）的工艺。通过使用沉积（100）硅并在外延生长（110）硅衬底（70）上形成第二栅电极（161）在第一SOI衬底（90）上形成第一栅电极（151），获得高性能CMOS器件其包括具有改善的空穴迁移率的高k金属PMOS栅电极（161）。

30. 发明申请

US20070298623A1 METHOD FOR STRAINING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：用于应变半导体器件的方法
公开(公告)号：US20070298623A1
公开(公告)日：2007-12-27
申请号：US11426463
申请日：2006-06-26
申请人： Gregory S. Spencer , Stanley M. Filipiak , Narayannan C. Ramani , Michael D. Turner
发明人： Gregory S. Spencer , Stanley M. Filipiak , Narayannan C. Ramani , Michael D. Turner
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/268 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A strained semiconductor layer is achieved by an overlying stressed dielectric layer. The stress in the dielectric layer is increased by a radiation anneal. The radiation anneal can be either by scanning using a laser beam or a flash tool that provides the anneal to the whole dielectric layer simultaneously. The heat is intense, preferably 900-1400 degrees Celcius, but for a very short duration of less than 10 milliseconds; preferably about 1 millisecond or even shorter. The result of the radiation anneal can also be used to activate the source/drain. Thus, this type of radiation anneal can result in a larger change in stress, activation of the source/drain, and still no expansion of the source/drain.
摘要翻译：应变半导体层通过覆盖的应力介电层实现。电介质层中的应力通过辐射退火而增加。辐射退火可以是通过使用激光束进行扫描或者同时向整个电介质层提供退火的闪光工具。热量很强，最好是900-1400摄氏度，但持续时间不到10毫秒; 优选约1毫秒甚至更短。辐射退火的结果也可用于激活源极/漏极。因此，这种类型的辐射退火可导致应力的变化较大，源极/漏极的激活以及源极/漏极的扩展。

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