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21. 发明授权

US07173312B2 Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification 失效
标题翻译：用于产生MOSFET通道迁移率修正的局部机械栅极应力的结构和方法
公开(公告)号：US07173312B2
公开(公告)日：2007-02-06
申请号：US10905101
申请日：2004-12-15
申请人： Cyril Cabral, Jr. , Bruce B. Doris , Thomas S. Kanarsky , Xiao H. Liu , Huilong Zhu
发明人： Cyril Cabral, Jr. , Bruce B. Doris , Thomas S. Kanarsky , Xiao H. Liu , Huilong Zhu
IPC分类号： H01L29/76
CPC分类号： H01L29/7845 , H01L21/3215 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/4966 , H01L29/517 , H01L29/665
摘要： A semiconductor structure and method that is capable of generating a local mechanical gate stress for channel mobility modification are provided. The semiconductor structure includes at least one NFET and at least one PFET on a surface of a semiconductor substrate. The at least one NFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer, a Si-containing second gate electrode layer and a compressive metal, and the at least one PFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer and a tensile metal or a silicide.
摘要翻译：提供了能够产生用于信道迁移率修改的局部机械栅极应力的半导体结构和方法。半导体结构在半导体衬底的表面上包括至少一个NFET和至少一个PFET。所述至少一个NFET具有包括栅极电介质，第一栅极电极层，阻挡层，含Si的第二栅极电极层和压缩金属的栅极堆叠结构，并且所述至少一个PFET具有包括栅极电介质，第一栅电极层，阻挡层和拉伸金属或硅化物。

22. 发明授权

US06333533B1 Trench storage DRAM cell with vertical three-sided transfer device 失效
标题翻译：沟槽存储DRAM单元，具有垂直三面传输设备
公开(公告)号：US06333533B1
公开(公告)日：2001-12-25
申请号：US09394964
申请日：1999-09-10
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Thomas S. Kanarsky , Jack A. Mandelman
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Thomas S. Kanarsky , Jack A. Mandelman
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10876
摘要： A pair of dynamic random access memory cells having each end of the active area surrounded on three sides by a gate conductor. The width of each end of the active area that is surrounded by a gate conductor preferably is less than fifty percent of the width of the deep trench intersected by that end of the active area.
摘要翻译：一对动态随机存取存储器单元，其有源区域的每个端部由三个侧面由栅极导体包围。由栅极导体围绕的有源区域的每个端部的宽度优选地小于由有源区域的该端部相交的深沟槽的宽度的百分之五十。

23. 发明授权

US06258661B1 Formation of out-diffused bitline by laser anneal 失效
标题翻译：通过激光退火形成扩散位线
公开(公告)号：US06258661B1
公开(公告)日：2001-07-10
申请号：US09651614
申请日：2000-08-30
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Thomas S. Kanarsky
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Thomas S. Kanarsky
IPC分类号： H01L27108
CPC分类号： H01L27/10885 , H01L21/2254 , H01L21/2257 , H01L21/268 , H01L21/743 , H01L27/10876
摘要： The present invention provides methods of forming an out-diffused bitline in a semiconductor substrate by utilizing a laser annealing step wherein the dopant material in the trench region is out-diffused into the semiconductor substrate. The out-diffused bitline can also be formed utilizing an ion implantation step.
摘要翻译：本发明提供了通过利用其中沟槽区域中的掺杂剂材料扩散到半导体衬底中的激光退火步骤在半导体衬底中形成向外扩散位线的方法。外扩散位线也可以利用离子注入步骤形成。

24. 发明申请

US20090189242A1 METHOD FOR NON-SELECTIVE SHALLOW TRENCH ISOLATION REACTIVE ION ETCH FOR PATTERNING HYBRID-ORIENTED DEVICES COMPATIBLE WITH HIGH-PERFORMANCE HIGHLY-INTEGRATED LOGIC DEVICES 失效
标题翻译：用于非选择性低温分离隔离反应离子蚀刻的方法，适用于兼容高性能高度集成逻辑器件的混合器件
公开(公告)号：US20090189242A1
公开(公告)日：2009-07-30
申请号：US12020887
申请日：2008-01-28
申请人： Gregory Costrini , David M. Dobuzinsky , Thomas S. Kanarsky , Munir D. Naeem , Christopher D. Sheraw , Richard Wise
发明人： Gregory Costrini , David M. Dobuzinsky , Thomas S. Kanarsky , Munir D. Naeem , Christopher D. Sheraw , Richard Wise
IPC分类号： H01L29/00 , H01L21/762
CPC分类号： H01L29/045 , H01L21/76224
摘要： Disclosed are embodiments of a hybrid-orientation technology (HOT) wafer and a method of forming the HOT wafer with improved shallow trench isolation (STI) structures for patterning devices in both silicon-on-insulator (SOI) regions, having a first crystallographic orientation, and bulk regions, having a second crystallographic orientation. The improved STI structures are formed using a non-selective etch process to ensure that all of the STI structures and, particularly, the STI structures at the SOI-bulk interfaces, each extend to the semiconductor substrate and have an essentially homogeneous (i.e., single material) and planar (i.e., divot-free) bottom surface that is approximately parallel to the top surface of the substrate. Optionally, an additional selective etch process can be used to extend the STI structures a predetermined depth into the substrate.
摘要翻译：公开了混合取向技术（HOT）晶片的实施例以及形成具有改进的浅沟槽隔离（STI）结构的HOT晶片的方法，用于在绝缘体上硅（SOI）区域中图案化器件，具有第一晶体取向和具有第二结晶取向的体区。使用非选择性蚀刻工艺形成改进的STI结构，以确保所有STI结构，特别是SOI-体界面处的STI结构各自延伸到半导体衬底并且具有基本均匀的（即，单个材料）和大致平行于衬底的顶表面的平面（即，无自由）底表面。可选地，可以使用附加的选择性蚀刻工艺来将STI结构延伸到衬底中的预定深度。

25. 发明授权

US07041538B2 Method of manufacturing a disposable reversed spacer process for high performance recessed channel CMOS 失效
标题翻译：制造用于高性能凹陷通道CMOS的一次性反向间隔器工艺的方法
公开(公告)号：US07041538B2
公开(公告)日：2006-05-09
申请号：US10713971
申请日：2003-11-14
申请人： Meikei Ieong , Omer H. Dokumaci , Thomas S. Kanarsky , Victor Ku
发明人： Meikei Ieong , Omer H. Dokumaci , Thomas S. Kanarsky , Victor Ku
IPC分类号： H01L21/00
CPC分类号： H01L29/78696 , H01L29/456 , H01L29/4908 , H01L29/66545 , H01L29/66772 , H01L29/78618 , H01L29/78621
摘要： A high-performance recessed channel CMOS device including an SOI layer having a recessed channel region and adjoining extension implant regions and optional halo implant regions; and at least one gate region present atop the SOI layer and a method for fabricating the same are provided. The adjoining extension and optional halo implant regions have an abrupt lateral profile and are located beneath said gate region.
摘要翻译：一种高性能凹陷沟道CMOS器件，包括具有凹陷沟道区域和相邻的延伸注入区域和可选的晕轮植入区域的SOI层; 并且提供存在于SOI层顶上的至少一个栅极区域及其制造方法。邻接的延伸部分和可选的晕轮植入区域具有突然的侧向轮廓并且位于所述栅极区域下方。

26. 发明授权

US06376873B1 Vertical DRAM cell with robust gate-to-storage node isolation 失效
标题翻译：垂直DRAM单元具有鲁棒的栅极到存储节点隔离
公开(公告)号：US06376873B1
公开(公告)日：2002-04-23
申请号：US09287410
申请日：1999-04-07
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Thomas S. Kanarsky , Jeffrey J. Welser
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Thomas S. Kanarsky , Jeffrey J. Welser
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10876
摘要： A dynamic random access memory device formed in a substrate having a trench. The trench has a side wall, a top, a lower portion, and a circumference. The device includes a signal storage node including a storage node conductor formed in the lower portion of the trench and isolated from the side wall by a node dielectric and a collar oxide above the node dielectric. A buried strap is coupled to the storage node conductor and contacts a portion of the side wall of the trench above the collar oxide. A trench-top dielectric which is formed upon the buried strap has a trench-top dielectric thickness. A signal transfer device includes a first diffusion region extending into the substrate adjacent the portion of the trench side wall contacted by the buried strap, a gate insulator having a gate insulator thickness formed on the trench side wall above the first buried strap, wherein the gate insulator thickness is less than the trench-top dielectric thickness, and a gate conductor formed within the trench upon the trench-top dielectric and adjacent the gate insulator.
摘要翻译：形成在具有沟槽的衬底中的动态随机存取存储器件。沟槽具有侧壁，顶部，下部和圆周。该装置包括信号存储节点，该信号存储节点包括形成在沟槽下部的存储节点导体，并且通过节点电介质和节点电介质上方的环形氧化物与侧壁隔离。埋置的带子耦合到存储节点导体并且与套环氧化物上方的沟槽的侧壁的一部分接触。形成在掩埋带上的沟槽电介质具有沟槽顶部的介电厚度。信号传送装置包括：第一扩散区域，其延伸到与所述掩埋带接触的所述沟槽侧壁的所述部分相邻的所述衬底;门绝缘体，其具有形成在所述第一掩埋带的上方的所述沟槽侧壁上的栅绝缘体厚度，绝缘体厚度小于沟槽顶部电介质厚度，以及形成在沟槽顶部电介质并且邻近栅极绝缘体的沟槽内的栅极导体。

27. 发明授权

US5620611A Method to improve uniformity and reduce excess undercuts during chemical etching in the manufacture of solder pads 失效
标题翻译：在制造焊盘的化学蚀刻期间改善均匀性并减少多余的底切的方法
公开(公告)号：US5620611A
公开(公告)日：1997-04-15
申请号：US659459
申请日：1996-06-06
申请人： Madhav Datta , Thomas S. Kanarsky , Michael B. Pike , Ravindra V. Shenoy
发明人： Madhav Datta , Thomas S. Kanarsky , Michael B. Pike , Ravindra V. Shenoy
IPC分类号： H01L21/60 , H01L23/48
CPC分类号： H01L24/11 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/14
摘要： Reduced undercutting of a titanium-tungsten layer in a ball limiting metallurgy (BLM) is achieved in the preparation of solder ball interconnect structures by removing metal oxide film which forms on the titanium-tungsten layer and etching the titanium-tungsten layer in different steps. Removing the metal oxide with an acid solution prior to etching the titanium-tungsten layer provides for a more uniform etch of the titanium-tungsten layer.
摘要翻译：通过去除在钛 - 钨层上形成的金属氧化物膜并以不同的步骤蚀刻钛 - 钨层，在制备焊球互连结构中实现了在极限极限冶金（BLM）中减少钛钨层的底切。在蚀刻钛 - 钨层之前用酸溶液去除金属氧化物提供对钛 - 钨层的更均匀的蚀刻。

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