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21. 发明授权

US07236634B2 Image encoding of moving pictures 失效
标题翻译：运动图像的图像编码
公开(公告)号：US07236634B2
公开(公告)日：2007-06-26
申请号：US10703547
申请日：2003-11-10
申请人： Junichi Miyakoshi , Masayuki Miyama , Masahiko Yoshimoto , Hideo Hashimoto , Kousuke Imamura
发明人： Junichi Miyakoshi , Masayuki Miyama , Masahiko Yoshimoto , Hideo Hashimoto , Kousuke Imamura
IPC分类号： G06K9/36
CPC分类号： H04N19/61 , H04N19/51
摘要： In an encoding method of moving pictures which generates a predictive picture for a current picture based on a reference picture and a motion vector, a macroblock is divided into subblocks. In each of the plurality of subblocks, an initial value of the motion vector is set and an evaluated value E on a difference between the current picture and the reference picture is calculated along a steepest descent direction to determine the minimum value. Then, the smallest evaluated value is selected among the minimum values obtained on the plurality of subblocks to determine the motion vector based on the pixel position of the smallest value.
摘要翻译：在基于参考图像和运动矢量生成当前图像的预测图像的运动图像的编码方法中，宏块被划分为子块。在多个子块中的每一个中，设置运动矢量的初始值，并且沿最陡下降方向计算当前画面与参考画面之间的差值的评估值E，以确定最小值。然后，从在多个子块上获得的最小值中选择最小的评估值，以基于最小值的像素位置来确定运动矢量。

22. 发明授权

US4878125A Method and apparatus for image processing with fed-back error correction 失效
标题翻译：具有反馈误差校正的图像处理方法和装置
公开(公告)号：US4878125A
公开(公告)日：1989-10-31
申请号：US140029
申请日：1987-12-31
申请人： Akihiro Katayama , Hidefumi Ohsawa , Izuru Sunohara , Hiroshi Hosokawa , Masahiko Yoshimoto
发明人： Akihiro Katayama , Hidefumi Ohsawa , Izuru Sunohara , Hiroshi Hosokawa , Masahiko Yoshimoto
IPC分类号： G06T5/00 , H04N1/405 , H04N1/52 , H04N7/26
CPC分类号： H04N19/90 , G06T7/0083 , H04N1/4052 , H04N1/52 , G06T2207/10008
摘要： There is an image processing apparatus for digitally processing an image. This apparatus comprises: a binarization circuit to binarize image data by a predetermined threshold value; a processor to correct errors generated in binarization; a first detector to detect an edge direction of the image from the image data; and a second detector to detect an edge quantum of the image from the image data. The process corrects the error data in accordance with the edge direction detected by the first detector or the edge quantum detected by the second detector. The errors to be corrected by the processor are the errors between the output concentration data after the binarization and the image concentration data. The processor adds weight coefficients to the error data in a predetermined range stored in a memory and then adds the weighted error data to image data to be newly binarized. The sum of the weight coefficients which are used in the weighting process is set to "1". With this apparatus, a high quality apparatus can be reproduced with a high fidelity from an original including many edges.
摘要翻译：存在用于数字处理图像的图像处理装置。该装置包括：将图像数据二值化预定阈值的二值化电路; 处理器，用于校正二值化中产生的错误; 第一检测器，用于从图像数据检测图像的边缘方向; 以及第二检测器，用于从图像数据检测图像的边缘量子。该过程根据由第一检测器检测到的边缘方向或由第二检测器检测到的边缘量子来校正误差数据。处理器要纠正的错误是二值化后的输出浓度数据与图像浓度数据之间的误差。处理器将加权系数加到存储在存储器中的预定范围内的误差数据上，然后将加权的误差数据加到新二进制化的图像数据上。在加权处理中使用的加权系数的和被设置为“1”。利用该装置，可以从包括许多边缘的原稿以高保真度再现高质量的装置。

23. 发明授权

US4554646A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4554646A
公开(公告)日：1985-11-19
申请号：US542388
申请日：1983-10-17
申请人： Masahiko Yoshimoto , Tsutomu Yoshihara , Kenji Anami , Hirofumi Shinohara
发明人： Masahiko Yoshimoto , Tsutomu Yoshihara , Kenji Anami , Hirofumi Shinohara
IPC分类号： G11C8/12 , G11C8/14 , G11C11/40
CPC分类号： G11C8/14 , G11C8/12
摘要： A memory matrix is segmented in the direction of columns into a plurality of groups of memory cells. The memory cells are accessible through respective preceding word lines each of which is provided for each of the rows of the matrix and commonly to all of the groups of the memory cells and group word lines each of which is provided per group and per row, so that a path for column current is set up during access time only in the column which belongs to a particular group including a particular memory to be accessed.
摘要翻译：存储器矩阵在列的方向上分割成多组存储器单元。存储器单元可以通过各自的前面的字线访问，每个字线是为矩阵的每一行提供的，并且通常是存储器单元的所有组以及每个组和每行提供的组字线，因此在访问时间期间仅在属于包括要访问的特定存储器的特定组的列中建立列电流的路径。

24. 发明申请

US20130223137A1 LOW-VOLTAGE SEMICONDUCTOR MEMORY 有权
标题翻译：低电压半导体存储器
公开(公告)号：US20130223137A1
公开(公告)日：2013-08-29
申请号：US13816718
申请日：2011-08-14
申请人： Masahiko Yoshimoto , Hiroshi Kawaguchi , Yohei Nakata , Shunsuke Okumura
发明人： Masahiko Yoshimoto , Hiroshi Kawaguchi , Yohei Nakata , Shunsuke Okumura
IPC分类号： G11C11/417
CPC分类号： G11C11/417 , G11C8/12 , G11C8/14 , G11C11/412 , G11C11/413 , G11C15/00 , G11C15/04 , G11C29/74 , G11C2211/5641
摘要： Provided is memory which is capable of dynamically changing memory cell bit reliability and of switching the operating mode so as to accommodate process variations, thereby reducing the operating voltage. The memory is provided with a mode control line selection circuit for dividing mode control lines in to word units and using control line selection signals and global control signals to control the mode control lines divided into word units, and a word line selection circuit for dividing the word lines that control the conduction of switching unit into word units and using word line selection signals and global word signals to control the word lines divided into word units. The mode control line switching circuit is used to switch between a 1 bit/1 cell mode and a 1 bit/n cell mode in word units.
摘要翻译：提供了能够动态地改变存储单元位可靠性和切换操作模式以适应过程变化的存储器，从而降低工作电压。存储器设置有模式控制线选择电路，用于将模式控制线分成单位，并且使用控制线选择信号和全局控制信号来控制分成字单元的模式控制线，以及字线选择电路，用于将控制开关单元导通到单元的字线，并使用字线选择信号和全局字信号来控制划分为字单位的字线。模式控制线切换电路用于以单位单位在1位/ 1个单元模式和1位/ n单元模式之间切换。

25. 发明授权

US08519880B2 Ad converter and TD converter configured without operational amplifier and capacitor 失效
标题翻译： Ad转换器和TD转换器配置无运算放大器和电容
公开(公告)号：US08519880B2
公开(公告)日：2013-08-27
申请号：US13470605
申请日：2012-05-14
申请人： Hiroshi Kawaguchi , Masahiko Yoshimoto , Toshihiro Konishi , Shintaro Izumi
发明人： Hiroshi Kawaguchi , Masahiko Yoshimoto , Toshihiro Konishi , Shintaro Izumi
IPC分类号： H03M1/50
CPC分类号： H03M1/50 , H03M3/416
摘要： An AD converter includes a VT converter circuit part which inputs an analog input voltage and a sampling clock, converts the analog input voltage to a corresponding delay time, and outputs time domain data. A ring oscillator circuit part of N stages inputs the time domain data, and an error propagation circuit part takes out delay information containing a quantization error from phase information of the ring oscillator circuit part of the previous stage, and propagate the delay information to the ring oscillator circuit part of a subsequent stage. A counter circuit part measures a number of waves of an output oscillation waveform of the ring oscillator circuit part of each stage, and an output signal generator part generates an output signal from an output counted value of each counter circuit part. A reset part resets each error propagation circuit part and each counter circuit part with a sampling clock.
摘要翻译： AD转换器包括输入模拟输入电压和采样时钟的VT转换器电路部分，将模拟输入电压转换为相应的延迟时间，并输出时域数据。 N级的环形振荡器电路部分输入时域数据，误差传播电路部分从前级的环形振荡电路部分的相位信息中取出包含量化误差的延迟信息，并将延迟信息传播到环振荡电路是后续阶段的一部分。计数器电路部分测量每个级的环形振荡器电路部分的输出振荡波形的波数，并且输出信号发生器部分根据每个计数器电路部分的输出计数值产生输出信号。复位部分将采样时钟复位每个误差传播电路部分和每个计数器电路部分。

26. 发明申请

US20060174303A1 Moving picture encoding or decoding processing system and mobin g picture encoding or decoding processing method 审中-公开
标题翻译：运动图像编码或解码处理系统和移动图像编码或解码处理方法
公开(公告)号：US20060174303A1
公开(公告)日：2006-08-03
申请号：US10553651
申请日：2004-04-15
申请人： Masahiko Yoshimoto , Kentaro Kawakami , Miwako Kanamori , Hideo Ohira
发明人： Masahiko Yoshimoto , Kentaro Kawakami , Miwako Kanamori , Hideo Ohira
IPC分类号： H04N7/173 , H04N7/16
CPC分类号： H04N19/42 , H04N19/127 , H04N19/136 , H04N19/172 , H04N19/61
摘要： This invention is aimed at providing a motion picture encoding or decoding system and a motion picture encoding or decoding method which economize the electric power consumption efficiently as compared with the conventional technique. They are provided with at least one failure avoiding means adapted to calculate a necessary volume Kp of operation required for encoding or decoding one frame, decide an operating frequency F capable of encoding or decoding the necessary volume Kp of operation within a duration Te allocated in advance to the operation of encoding or decoding the one frame, perform the operation of encoding or decoding the one frame while continuing the operation of the processor at the operating frequency F and an operating voltage V befitting the operating frequency F, and avoid the failure situation which occurs when the necessary volume Kp of operation is smaller than the actually necessary volume of operation.
摘要翻译：本发明旨在提供一种与常规技术相比有效地节省电力消耗的运动图像编码或解码系统和运动图像编码或解码方法。它们被提供有至少一个故障避免装置，其适于计算编码或解码一帧所需的操作的必要体积Kp，决定能够在预先分配的持续时间Te内编码或解码所需体积Kp的操作频率F 对于一帧编码或解码的操作，在操作频率F持续处理器的操作和与操作频率F相匹配的操作电压V的同时执行对一帧进行编码或解码的操作，并避免出现故障情况当必需的操作量Kp小于实际所需的操作量时发生。

27. 发明授权

US5453994A Semiconductor test system, semiconductor test method, method of wiring pattern formation and semiconductor integrated circuit 失效
标题翻译：半导体测试系统，半导体测试方法，布线图案形成方法和半导体集成电路
公开(公告)号：US5453994A
公开(公告)日：1995-09-26
申请号：US91261
申请日：1993-07-15
申请人： Kiyofumi Kawamoto , Masahiko Yoshimoto
发明人： Kiyofumi Kawamoto , Masahiko Yoshimoto
IPC分类号： G01R31/28 , G01R31/311 , G06F17/50 , H01L21/66 , H01L21/822 , H01L27/04 , G06F11/00
CPC分类号： G01R31/311
摘要： The semiconductor test system comprises an OBIC measuring device (8) and a tester (5). The tester (5) transmits a test signal to an input pad (2a) of a semiconductor integrated circuit (1). In synchronization with this, the OBIC measuring device (8) irradiates drain regions (6) of the semiconductor integrated circuit (1) with a laser beam (7) one after another, to thereby detect the generation of the OBIC. An comparator (5c) in the tester (5) compares an output signal from an output pad (2b) of the semiconductor integrated circuit (1) and an OBIC detection signal from the OBIC measuring device (8) with expected values (5b).
摘要翻译：半导体测试系统包括OBIC测量装置（8）和测试仪（5）。测试器（5）将测试信号发送到半导体集成电路（1）的输入焊盘（2a）。与此同步，OBIC测量装置（8）一个接一个地用激光束（7）照射半导体集成电路（1）的漏极区域（6），从而检测OBIC的产生。测试器（5）中的比较器（5c）将来自半导体集成电路（1）的输出焊盘（2b）的输出信号和来自OBIC测量装置（8）的OBIC检测信号与期望值（5b）进行比较。

28. 再颁专利

USRE33280E Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：USRE33280E
公开(公告)日：1990-07-31
申请号：US123106
申请日：1987-11-19
申请人： Masahiko Yoshimoto , Tsutomu Yoshihara , Kenji Anami , Hirofumi Shinohara
发明人： Masahiko Yoshimoto , Tsutomu Yoshihara , Kenji Anami , Hirofumi Shinohara
IPC分类号： G11C5/06 , G11C8/14
CPC分类号： G11C5/063 , G11C8/14
摘要： A memory matrix is segmented in the direction of columns into a plurality of groups of memory cells. The memory cells are accessible through respective preceding word lines each of which is provided for each of the rows of the matrix and commonly to all of the groups of the memory cells and group word lines each of which is provided per group and per row, so that a path for column current is set up during access time only in the column which belongs to a particular group including a particular memory to be accessed.

29. 发明授权

US4772930A Complementary metal oxide semiconductor integrated circuit with unequal reference voltages 失效
标题翻译：具有不等参考电压的互补金属氧化物半导体集成电路
公开(公告)号：US4772930A
公开(公告)日：1988-09-20
申请号：US48509
申请日：1987-05-04
申请人： Kenji Anami , Masahiko Yoshimoto , Satoru Kamoto
发明人： Kenji Anami , Masahiko Yoshimoto , Satoru Kamoto
IPC分类号： H01L27/08 , H01L21/74 , H01L23/528 , H01L23/535 , H01L27/092 , H01L27/02
CPC分类号： H01L27/0921 , H01L21/743 , H01L23/5286 , H01L23/535 , H01L2924/0002
摘要： A power supply voltage to be applied to a metallic connection 36a is supplied through an n.sup.+ diffusion region 34a, an N type well 22, an n.sup.+ diffusion region 34c and a metallic connection 36C to a p.sup.+ diffusion region 23b serving as a power supply line. An n.sup.+ diffusion region 73 serving as a ground line is grounded through a metallic connection 76c, a p.sup.+ diffusion region 74c, a P type well 72, a p.sup.+ diffusion region 74b and a metallic connection 76b.
摘要翻译：施加到金属连接36a的电源电压通过n +扩散区域34a，N型阱22，n +扩散区域34c和金属连接件36C提供给用作电源线的p +扩散区域23b。用作接地线的n +扩散区73通过金属连接76c，p +扩散区74c，P型阱72，p +扩散区74b和金属连接76b接地。

30. 发明授权

US4542486A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4542486A
公开(公告)日：1985-09-17
申请号：US500608
申请日：1983-06-02
申请人： Kenji Anami , Masahiko Yoshimoto , Hirofumi Shinohara , Osamu Tomisawa
发明人： Kenji Anami , Masahiko Yoshimoto , Hirofumi Shinohara , Osamu Tomisawa
IPC分类号： G11C11/417 , G11C5/02 , G11C5/06 , G11C8/12 , G11C8/14 , G11C11/41 , G11C11/40
CPC分类号： G11C5/06 , G11C5/02 , G11C8/12 , G11C8/14
摘要： A semiconductor memory device is improved as regards current consumption and access time by dividing the memory cells into a plurality of columner groups and providing group selecting lines. Front-end word lines of low resistance are connected to outputs of row decoders, and AND gates receive selecting signals on the group selecting lines and the outputs of the front-end word lines. Word lines of a comparatively short length are connected to the AND outputs.
摘要翻译：通过将存储单元划分成多个电容器组并提供组选择线，半导体存储器件关于电流消耗和存取时间被改进。低电阻的前端字线连接到行解码器的输出，与门接收组选择线上的选择信号和前端字线的输出。长度相对较短的字线连接到AND输出。

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