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21. 发明申请

US20090294798A1 Bipolar Device Compatible with CMOS Process Technology 有权
标题翻译：双极器件兼容CMOS工艺技术
公开(公告)号：US20090294798A1
公开(公告)日：2009-12-03
申请号：US12256376
申请日：2008-10-22
申请人： Shine Chung , Fu-Lung Hsueh
发明人： Shine Chung , Fu-Lung Hsueh
IPC分类号： H01L29/739
CPC分类号： H01L29/735 , H01L27/0207 , H01L27/0623 , H01L29/0692 , H01L29/1008
摘要： A bipolar device includes: an emitter of a first polarity type constructed on a semiconductor substrate; a collector of the first polarity type constructed on the semiconductor substrate; a gate pattern in a mesh configuration defining the emitter and the collector; an intrinsic base of a second polarity type underlying the gate pattern; and an extrinsic base constructed atop the gate pattern and coupled with the intrinsic base, for functioning together with the intrinsic base as a base of the bipolar device.
摘要翻译：双极器件包括：构造在半导体衬底上的第一极性类型的发射极; 在半导体衬底上构造的第一极性类型的集电极; 限定发射极和集电极的网格配置中的栅极图案; 位于栅极图案下方的第二极性类型的本征基极; 以及构造在栅极图案顶部并与本征基极耦合的外部基极，用于与作为双极器件的基极的本征基极一起工作。

22. 发明申请

US20090174487A1 VOLTAGE-CONTROL OSCILLATOR CIRCUITS WITH COMBINED MOS AND BIPOLAR DEVICE 有权
标题翻译：具有组合MOS和双极器件的电压控制振荡器电路
公开(公告)号：US20090174487A1
公开(公告)日：2009-07-09
申请号：US12237187
申请日：2008-09-24
申请人： Shine Chung , Fu-Lung Hsueh
发明人： Shine Chung , Fu-Lung Hsueh
IPC分类号： H03K3/00 , H03B5/02
CPC分类号： H03B5/1228 , H03B5/1203 , H03B5/1212 , H03B5/1215 , H03B5/1231 , H03B5/124
摘要： A voltage controlled oscillator includes: a first merged device having a first bipolar transistor and a first MOS transistor, the first bipolar transistor having a collector sharing a common active area with a source/drain of the first MOS transistor, and an emitter sharing the common active area with another source/drain of the first MOS transistor, a second merged device having a second bipolar transistor and a second MOS transistor, the second bipolar transistor having a collector sharing a common active area with a source/drain of the second MOS transistor, and an emitter sharing the common active area with another source/drain of the second MOS transistor, and a first inductor connected to both the collector of the first bipolar transistor and a base of the second bipolar transistor.
摘要翻译：压控振荡器包括：具有第一双极晶体管和第一MOS晶体管的第一合并器件，所述第一双极晶体管具有与第一MOS晶体管的源极/漏极共用公共有效面积的集电极，以及共享公共具有第一MOS晶体管的另一源/漏极的有源区，具有第二双极晶体管和第二MOS晶体管的第二合并器件，所述第二双极晶体管具有与第二MOS晶体管的源极/漏极共用共用有效面积的集电极以及与第二MOS晶体管的另一个源极/漏极共用公共有源区域的发射极，以及连接到第一双极晶体管的集电极和第二双极晶体管的基极的第一电感器。

23. 发明申请

US20090141573A1 System and Method for Better Testability of OTP Memory 有权
标题翻译： OTP内存的可测试性的系统和方法
公开(公告)号：US20090141573A1
公开(公告)日：2009-06-04
申请号：US12124989
申请日：2008-05-21
申请人： Fu Lung Hsueh , Shine Chung , Wen-Kuan Fang , Po-Hung Chen
发明人： Fu Lung Hsueh , Shine Chung , Wen-Kuan Fang , Po-Hung Chen
IPC分类号： G11C29/00
CPC分类号： G11C29/08 , G11C2216/26
摘要： A system for testing logic circuits for executing writing and reading operations in a one-time programmable (OTP) memory having an array of memory cells is disclosed, the system comprising a column of testing cells having the same number of cells as that of an entire column of the array of memory cells, a row of testing cells having the same number of cells as that of an entire row of the array of memory cells, wherein both the column and row of testing cells are first written to and then read out from during a testing operation, and can never be accessed during non-testing operations of the OTP memory.
摘要翻译：公开了一种用于测试在具有存储器单元阵列的一次可编程（OTP）存储器中执行写入和读取操作的逻辑电路的系统，该系统包括具有与整个存储器单元相同数量的单元格的测试单元列存储单元阵列的列，一行具有与存储器单元阵列的整行相同数量的单元的测试单元，其中测试单元的列和行首先被写入然后从在测试操作期间，并且在OTP存储器的非测试操作期间永远不能被访问。

24. 发明申请

US20080283963A1 Electrical Fuse Circuit for Security Applications 有权
标题翻译：用于安全应用的电保险电路
公开(公告)号：US20080283963A1
公开(公告)日：2008-11-20
申请号：US11748959
申请日：2007-05-15
申请人： Shine Chung , Fu-Lung Hsueh , Fu-Chieh Hsu
发明人： Shine Chung , Fu-Lung Hsueh , Fu-Chieh Hsu
IPC分类号： H01L23/62 , H01L29/00
CPC分类号： G11C17/18
摘要： A fuse circuit is disclosed, which comprises at least one electrical fuse element having a resistance that changes after being stressed in an electromigration mode, a switching device serially coupled with the electrical fuse element in a predetermined path between a fuse programming power supply (VDDQ) and a low voltage power supply (GND) for selectively allowing a programming current passing through the electrical fuse element during a programming operation, and at least one peripheral circuit coupled to the VDDQ, wherein the peripheral circuit is active and draws current from the VDDQ during a fuse programming operation.
摘要翻译：公开了一种熔丝电路，其包括至少一个电熔丝元件，该电熔丝元件具有在电迁移模式下受到应力之后变化的电阻;开关装置，其在熔丝编程电源（VDDQ）之间的预定路径中与电熔丝元件串联连接，以及用于在编程操作期间选择性地允许通过电熔丝元件的编程电流的低电压电源（GND），以及耦合到所述VDDQ的至少一个外围电路，其中所述外围电路是有效的并且在VDDQ期间从VDDQ引出电流保险丝编程操作。

25. 发明授权

US07968971B2 Thin-body bipolar device 有权
标题翻译：薄体双极器件
公开(公告)号：US07968971B2
公开(公告)日：2011-06-28
申请号：US12500915
申请日：2009-07-10
申请人： Shine Chung , Fu-Lung Hsueh
发明人： Shine Chung , Fu-Lung Hsueh
IPC分类号： H01L21/02
CPC分类号： H01L29/7317 , H01L29/0692 , H01L29/0804
摘要： A thin-body bipolar device includes: a semiconductor substrate, a semiconductor fin constructed over the semiconductor substrate, a first region of the semiconductor fin having a first conductivity type, the first region serving as a base of the thin-body bipolar device, and a second and third region of the semiconductor fin having a second conductivity type opposite to the first conductivity type, the second and third region being both juxtaposed with and separated by the first region, the second and third region serving as an emitter and collector of the thin-body bipolar device, respectively.
摘要翻译：薄体双极器件包括：半导体衬底，半导体衬底上构造的半导体鳍片，具有第一导电类型的半导体鳍片的第一区域，用作薄体双极器件的基底的第一区域，以及所述半导体鳍片的第二和第三区域具有与所述第一导电类型相反的第二导电类型，所述第二和第三区域与所述第一区域并置并分隔开，所述第二和第三区域用作所述第一和第三区域的发射极和集电极薄体双极器件。

26. 发明授权

US07782656B2 SRAM with improved read/write stability 有权
标题翻译： SRAM具有改善的读/写稳定性
公开(公告)号：US07782656B2
公开(公告)日：2010-08-24
申请号：US12178420
申请日：2008-07-23
申请人： Fu-Lung Hsueh , Shine Chung , Wen-Kuan Fang
发明人： Fu-Lung Hsueh , Shine Chung , Wen-Kuan Fang
IPC分类号： G11C11/00 , G11C5/06 , G11C7/10
CPC分类号： G11C11/419 , G11C11/412
摘要： A static random access memory (SRAM) cell is disclosed which comprises a cross-couple inverter latch coupled between a positive supply voltage and ground, and having at least a first storage node, and a first and second switching device serially connected between the first storage node and a predetermined voltage source, wherein the first switching device is controlled by a word select signal, and the second switching device is controlled by a first bit select signal, wherein either the word select signal or the first bit select signal is only activated during a write operation.
摘要翻译：公开了一种静态随机存取存储器（SRAM）单元，其包括耦合在正电源电压和地之间并具有至少第一存储节点的交叉耦合逆变器锁存器，以及串联连接在第一存储器节点和预定电压源，其中第一开关装置由字选择信号控制，第二开关装置由第一位选择信号控制，其中字选择信号或第一位选择信号仅在一个写操作。

27. 发明申请

US20100123483A1 Circuit and Method for a Digital Process Monitor 有权
标题翻译：数字过程监视器的电路和方法
公开(公告)号：US20100123483A1
公开(公告)日：2010-05-20
申请号：US12495024
申请日：2009-06-30
申请人： Shine Chung , Fu-Lung Hsueh
发明人： Shine Chung , Fu-Lung Hsueh
IPC分类号： H03K5/22
CPC分类号： G01R31/3004 , G01R31/31703
摘要： A circuit and method for a digital process monitor is disclosed. Circuits for comparing a current or voltage to a current or voltage corresponding to a device having process dependent circuit characteristics are disclosed, having converters for converting current or voltage measurements proportional to the process dependent circuit characteristic to a digital signal and outputting the digital signal for monitoring. The process dependent circuit characteristics may be selected from transistor threshold voltage, transistor saturation current, and temperature dependent quantities. Calibration is performed using digital techniques such as digital filtering and digital signal processing. The digital process monitor circuit may be formed as a scribe line circuit for wafer characterization or placed in an integrated circuit die as a macro. The process monitor circuit may be accessed using probe pads or scan test circuitry. Methods for monitoring process dependent characteristics using digital outputs are disclosed.
摘要翻译：公开了一种用于数字处理监视器的电路和方法。公开了用于将电流或电压与对应于具有过程相关电路特性的器件相对应的电流或电压进行比较的电路，具有用于将与过程相关的电路特性成比例的电流或电压测量值转换为数字信号的转换器，并输出用于监测的数字信号。处理相关电路特性可以选自晶体管阈值电压，晶体管饱和电流和温度依赖量。使用数字滤波和数字信号处理等数字技术进行校准。数字处理监视电路可以形成为用于晶片表征的划线电路或者作为宏放置在集成电路管芯中。可以使用探针焊盘或扫描测试电路来访问过程监控电路。公开了使用数字输出来监视与过程有关的特性的方法。

28. 发明申请

US20100020590A1 SRAM WITH IMPROVED READ/WRITE STABILITY 有权
标题翻译： SRAM具有改进的读/写稳定性
公开(公告)号：US20100020590A1
公开(公告)日：2010-01-28
申请号：US12178420
申请日：2008-07-23
申请人： Fu-Lung Hsueh , Shine Chung , Wen-Kuan Fang
发明人： Fu-Lung Hsueh , Shine Chung , Wen-Kuan Fang
IPC分类号： G11C7/00
CPC分类号： G11C11/419 , G11C11/412
摘要： A static random access memory (SRAM) cell is disclosed which comprises a cross-couple inverter latch coupled between a positive supply voltage and ground, and having at least a first storage node, and a first and second switching device serially connected between the first storage node and a predetermined voltage source, wherein the first switching device is controlled by a word select signal, and the second switching device is controlled by a first bit select signal, wherein either the word select signal or the first bit select signal is only activated during a write operation.
摘要翻译：公开了一种静态随机存取存储器（SRAM）单元，其包括耦合在正电源电压和地之间并具有至少第一存储节点的交叉耦合逆变器锁存器，以及串联连接在第一存储器节点和预定电压源，其中第一开关装置由字选择信号控制，第二开关装置由第一位选择信号控制，其中字选择信号或第一位选择信号仅在一个写操作。

29. 发明授权

US07633415B2 System and method for calibrating digital-to-analog convertors 有权
标题翻译：用于校准数模转换器的系统和方法
公开(公告)号：US07633415B2
公开(公告)日：2009-12-15
申请号：US11691872
申请日：2007-03-27
申请人： Shine Chung , Fu-Lung Hsueh
发明人： Shine Chung , Fu-Lung Hsueh
IPC分类号： H03M1/10
CPC分类号： H03M1/1042 , H03M1/687
摘要： A system and method for calibrating a digital-to-analog converter (DAC) is disclosed, the method comprises providing a plurality of spare bits to each of a group of DAC bits that are designated for calibration, calibrating a first DAC bit of the group of DAC bits using its corresponding plurality of spare bits, and keeping a second DAC bit of the group of DAC bits unchanged while calibrating the first DAC bit.
摘要翻译：公开了一种用于校准数模转换器（DAC）的系统和方法，该方法包括向被指定用于校准的一组DAC位中的每一个提供多个备用位，校准该组的第一DAC位的DAC位使用其对应的多个备用位，并且在校准第一DAC位的同时保持DAC位组的第二DAC位不变。

30. 发明授权

US07577020B2 System and method for reading multiple magnetic tunnel junctions with a single select transistor 有权
标题翻译：用单个选择晶体管读取多个磁隧道结的系统和方法
公开(公告)号：US07577020B2
公开(公告)日：2009-08-18
申请号：US11865481
申请日：2007-10-01
申请人： Shine Chung , Denny Tang , Fu-Lung Hsueh
发明人： Shine Chung , Denny Tang , Fu-Lung Hsueh
IPC分类号： G11C11/00 , G11C11/15 , G11C15/00
CPC分类号： G11C13/003 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C2213/75 , G11C2213/78
摘要： A method for reading two or more magnetic tunnel junctions (MTJs) which are serially connected with a select transistor to form a memory string, the method comprises turning on the select transistor, measuring a first resistance of the memory string, storing the first resistance, toggling a predetermined one of the MTJs, measuring a second resistance of the memory string after the toggling, toggling back the predetermined one of the MTJs and comparing the first and second resistances with a plurality of predetermined resistance values, wherein the comparison result leads to a determination of the data stored in the MTJs.
摘要翻译：一种用于读取与选择晶体管串联连接以形成存储器串的两个或多个磁隧道结（MTJ）的方法，所述方法包括接通选择晶体管，测量存储器串的第一电阻，存储第一电阻，切换MTJ中的预定的一个，在切换之后测量存储器串的第二电阻，反转预定的一个MTJ，并用多个预定电阻值比较第一和第二电阻，其中比较结果导致确定存储在MTJ中的数据。

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