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21. 发明申请

US20050272190A1 Methods of fabricating fin field-effect transistors having silicide gate electrodes and related devices 审中-公开
标题翻译：制造具有硅化物栅电极和相关器件的鳍式场效应晶体管的方法
公开(公告)号：US20050272190A1
公开(公告)日：2005-12-08
申请号：US11143561
申请日：2005-06-02
申请人： Deok-Hyung Lee , Yu-Gyun Shin , Jong-Wook Lee
发明人： Deok-Hyung Lee , Yu-Gyun Shin , Jong-Wook Lee
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L21/338 , H01L29/49 , H01L29/76 , H01L29/786
CPC分类号： H01L29/7851 , H01L21/28052 , H01L29/4908 , H01L29/66795
摘要： A method of fabricating a fin field-effect transistor includes forming a fin-shaped active region having first and second source/drain regions therein and a channel region therebetween vertically protruding from a semiconductor substrate, and forming a polysilicon gate electrode on sidewalls of the channel region. Opposing sidewalls of the polysilicon gate electrode are silicided towards a central region thereof to form a silicide gate electrode. Related devices are also discussed.
摘要翻译：制造鳍状场效应晶体管的方法包括：形成其中具有第一和第二源极/漏极区的鳍状有源区和在半导体衬底之间垂直突出的沟道区，以及在沟道的侧壁上形成多晶硅栅电极地区。将多晶硅栅极的相对侧壁朝向其中心区域硅化以形成硅化物栅电极。还讨论了相关设备。

22. 发明授权

US07320908B2 Methods of forming semiconductor devices having buried oxide patterns 有权
标题翻译：形成具有掩埋氧化物图案的半导体器件的方法
公开(公告)号：US07320908B2
公开(公告)日：2008-01-22
申请号：US11072103
申请日：2005-03-04
申请人： Yong-Hoon Son , Si-Young Choi , Byeong-Chan Lee , Jong-Wook Lee , In-Soo Jung , Deok-Hyung Lee
发明人： Yong-Hoon Son , Si-Young Choi , Byeong-Chan Lee , Jong-Wook Lee , In-Soo Jung , Deok-Hyung Lee
IPC分类号： H01L21/338
CPC分类号： H01L29/7851 , H01L21/823481 , H01L29/0653 , H01L29/66545 , H01L29/66621
摘要： Methods for forming semiconductor devices are provided. A semiconductor substrate is etched such that the semiconductor substrate defines a trench and a preliminary active pattern. The trench has a floor and a sidewall. An insulating layer is provided on the floor and the sidewall of the trench and a spacer is formed on the insulating layer such that the spacer is on the sidewall of the trench and on a portion of the floor of the trench. The insulating layer is removed on the floor of the trench and beneath the spacer such that a portion of the floor of the trench is at least partially exposed, the spacer is spaced apart from the floor of the trench and a portion of the preliminary active pattern is partially exposed. A portion of the exposed portion of the preliminary active pattern is partially removed to provide an active pattern that defines a recessed portion beneath the spacer. A buried insulating layer is formed in the recessed portion of the active pattern. Related devices are also provided.
摘要翻译：提供了形成半导体器件的方法。蚀刻半导体衬底，使得半导体衬底限定沟槽和初步活性图案。沟槽具有地板和侧壁。绝缘层设置在地板上，并且沟槽的侧壁和间隔件形成在绝缘层上，使得间隔件位于沟槽的侧壁和沟槽底部的一部分上。绝缘层在沟槽的地板上移除并且在间隔物的下面被移除，使得沟槽的底部的一部分至少部分地露出，间隔物与沟槽的底部间隔开，并且预活性图案的一部分部分暴露。部分地去除预活性图案的暴露部分的一部分以提供在间隔物下方限定凹陷部分的活性图案。在活性图案的凹部中形成掩埋绝缘层。还提供了相关设备。

23. 发明申请

US20050218395A1 Heterogeneous group IV semiconductor substrates, integrated circuits formed on such substrates, and related methods 有权
标题翻译：异质IV族半导体衬底，形成在这种衬底上的集成电路及相关方法
公开(公告)号：US20050218395A1
公开(公告)日：2005-10-06
申请号：US11080737
申请日：2005-03-15
申请人： Sung-Min Kim , Kyoung-Hwan Yeo , In-Soo Jung , Si-Young Choi , Dong-Won Kim , Yong-Hoon Son , Young-Eun Lee , Byeong-Chan Lee , Jong-Wook Lee
发明人： Sung-Min Kim , Kyoung-Hwan Yeo , In-Soo Jung , Si-Young Choi , Dong-Won Kim , Yong-Hoon Son , Young-Eun Lee , Byeong-Chan Lee , Jong-Wook Lee
IPC分类号： H01L21/20 , H01L29/06 , H01L29/78
CPC分类号： H01L29/0653 , H01L29/78
摘要： Embodiments of the present invention include heterogeneous substrates, integrated circuits formed on such heterogeneous substrates, and methods of forming such substrates and integrated circuits. The heterogeneous substrates according to certain embodiments of the present invention include a first Group IV semiconductor layer (e.g., silicon), a second Group IV pattern (e.g., a silicon-germanium pattern) that includes a plurality of individual elements on the first Group IV semiconductor layer, and a third Group IV semiconductor layer (e.g., a silicon epitaxial layer) on the second Group IV pattern and on a plurality of exposed portions of the first Group IV semiconductor layer. The second Group IV pattern may be removed in embodiments of the present invention. In these and other embodiments of the present invention, the third Group IV semiconductor layer may be planarized.
摘要翻译：本发明的实施例包括异质衬底，在这种异质衬底上形成的集成电路，以及形成这种衬底和集成电路的方法。根据本发明的某些实施方案的异质衬底包括第一组IV半导体层（例如，硅），第二组IV图案（例如硅 - 锗图案），其包括第一组IV上的多个单独元件半导体层和第二组IV模式上的第三组IV半导体层（例如，硅外延层）和第一组IV半导体层的多个暴露部分上。在本发明的实施例中可以去除第二组IV图案。在本发明的这些和其它实施例中，第三组IV半导体层可以被平坦化。

24. 发明申请

US20080308845A1 Heterogeneous Group IV Semiconductor Substrates 审中-公开
标题翻译：异质IV族半导体基片
公开(公告)号：US20080308845A1
公开(公告)日：2008-12-18
申请号：US12195790
申请日：2008-08-21
申请人： Sung-Min Kim , Kyoung-Hwan Yeo , In-Soo Jung , Si-Young Choi , Dong-Won Kim , Yong-Hoon Son , Young-Eun Lee , Byeong-Chan Lee , Jong-Wook Lee
发明人： Sung-Min Kim , Kyoung-Hwan Yeo , In-Soo Jung , Si-Young Choi , Dong-Won Kim , Yong-Hoon Son , Young-Eun Lee , Byeong-Chan Lee , Jong-Wook Lee
IPC分类号： H01L29/00
CPC分类号： H01L29/0653 , H01L29/78
摘要： Embodiments of the present invention include heterogeneous substrates, integrated circuits formed on such heterogeneous substrates. The heterogeneous substrates according to certain embodiments of the present invention include a first Group IV semiconductor layer (e.g., silicon), a second Group IV pattern (e.g., a silicon-germanium pattern) that includes a plurality of individual elements on the first Group IV semiconductor layer, and a third Group IV semiconductor layer (e.g., a silicon epitaxial layer) on the second Group IV pattern and on a plurality of exposed portions of the first Group IV semiconductor layer. The second Group IV pattern may be removed in embodiments of the present invention. In these and other embodiments of the present invention, the third Group IV semiconductor layer may be planarized.
摘要翻译：本发明的实施例包括异质衬底，在这种异质衬底上形成的集成电路。根据本发明的某些实施方案的异质衬底包括第一组IV半导体层（例如，硅），第二组IV图案（例如硅 - 锗图案），其包括第一组IV上的多个单独元件半导体层和第二组IV模式上的第三组IV半导体层（例如，硅外延层）和第一组IV半导体层的多个暴露部分上。在本发明的实施例中可以去除第二组IV图案。在本发明的这些和其它实施例中，第三组IV半导体层可以被平坦化。

25. 发明授权

US07429504B2 Heterogeneous group IV semiconductor substrates, integrated circuits formed on such substrates, and related methods 有权
标题翻译：异质IV族半导体衬底，形成在这种衬底上的集成电路及相关方法
公开(公告)号：US07429504B2
公开(公告)日：2008-09-30
申请号：US11080737
申请日：2005-03-15
申请人： Sung-Min Kim , Kyoung-Hwan Yeo , In-Soo Jung , Si-Young Choi , Dong-Won Kim , Yong-Hoon Son , Young-Eun Lee , Byeong-Chan Lee , Jong-Wook Lee
发明人： Sung-Min Kim , Kyoung-Hwan Yeo , In-Soo Jung , Si-Young Choi , Dong-Won Kim , Yong-Hoon Son , Young-Eun Lee , Byeong-Chan Lee , Jong-Wook Lee
IPC分类号： H01L21/764 , H01L31/0336
CPC分类号： H01L29/0653 , H01L29/78
摘要： Embodiments of the present invention include heterogeneous substrates, integrated circuits formed on such heterogeneous substrates, and methods of forming such substrates and integrated circuits. The heterogeneous substrates according to certain embodiments of the present invention include a first Group IV semiconductor layer (e.g., silicon), a second Group IV pattern (e.g., a silicon-germanium pattern) that includes a plurality of individual elements on the first Group IV semiconductor layer, and a third Group IV semiconductor layer (e.g., a silicon epitaxial layer) on the second Group IV pattern and on a plurality of exposed portions of the first Group IV semiconductor layer. The second Group IV pattern may be removed in embodiments of the present invention. In these and other embodiments of the present invention, the third Group IV semiconductor layer may be planarized.
摘要翻译：本发明的实施例包括异质衬底，在这种异质衬底上形成的集成电路，以及形成这种衬底和集成电路的方法。根据本发明的某些实施方案的异质衬底包括第一组IV半导体层（例如，硅），第二组IV图案（例如硅 - 锗图案），其包括第一组IV上的多个单独元件半导体层和第二组IV模式上的第三组IV半导体层（例如，硅外延层）和第一组IV半导体层的多个暴露部分上。在本发明的实施例中可以去除第二组IV图案。在本发明的这些和其它实施例中，第三组IV半导体层可以被平坦化。

26. 发明授权

US07553742B2 Method(s) of forming a thin layer 有权
标题翻译：形成薄层的方法
公开(公告)号：US07553742B2
公开(公告)日：2009-06-30
申请号：US11329158
申请日：2006-01-11
申请人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee
发明人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee
IPC分类号： H01L21/76
CPC分类号： C30B25/04 , C30B29/06 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02639
摘要： A method of forming a thin layer including providing a first single-crystalline silicon layer partially exposed through an opening in an insulation pattern and forming an epitaxial layer on the first single-crystalline silicon layer and forming an amorphous silicon layer on the insulation pattern, the amorphous silicon layer having a first portion adjacent the epitaxial layer and a second portion spaced apart from the first portion, wherein the amorphous silicon layer is formed on the insulation pattern at substantially the same rate at the first portion and at a second portion. The amorphous silicon layer may be formed to a uniform thickness without a thinning defect.
摘要翻译：一种形成薄层的方法，包括提供通过绝缘图案中的开口局部暴露的第一单晶硅层，并在第一单晶硅层上形成外延层，并在绝缘图案上形成非晶硅层，非晶硅层，其具有与外延层相邻的第一部分和与第一部分间隔开的第二部分，其中非晶硅层在第一部分和第二部分以基本上相同的速率形成在绝缘图案上。可以将非晶硅层形成为均匀的厚度而没有变薄的缺陷。

27. 发明授权

US07396761B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07396761B2
公开(公告)日：2008-07-08
申请号：US11605092
申请日：2006-11-28
申请人： Sung-Kwan Kang , Jong-Wook Lee , Yong-Hoon Son , Yu-Gyun Shin , Jun-Ho Lee
发明人： Sung-Kwan Kang , Jong-Wook Lee , Yong-Hoon Son , Yu-Gyun Shin , Jun-Ho Lee
IPC分类号： H01L21/336 , H01L21/4763 , H01L21/44
CPC分类号： H01L29/66795 , H01L29/7851
摘要： In a semiconductor device and a method of manufacturing the semiconductor device, a plug and a channel structure are formed. The plug fills an opening and the channel structure extends upwardly from the plug. The channel structure has a substantially vertical sidewall. The opening is formed through an insulation structure located on a substrate. The plug and the channel structure comprise a material in a single crystalline state that is changed from an amorphous state by an irradiation of a laser beam. The channel structure is doped with impurities such as boron, phosphorus or arsenic.
摘要翻译：在半导体器件和半导体器件的制造方法中，形成插头和沟道结构。塞子填充开口并且通道结构从插头向上延伸。通道结构具有基本垂直的侧壁。开口通过位于基板上的绝缘结构形成。塞子和通道结构包括通过激光束的照射从非晶状态改变的单晶状态的材料。通道结构掺杂有杂质如硼，磷或砷。

28. 发明申请

US20070231976A1 Method for fabricating a semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20070231976A1
公开(公告)日：2007-10-04
申请号：US11730262
申请日：2007-03-30
申请人： Sung-Kwan Kang , Yu-Gyun Shin , Jong-Wook Lee , Yong-Hoon Son
发明人： Sung-Kwan Kang , Yu-Gyun Shin , Jong-Wook Lee , Yong-Hoon Son
IPC分类号： H01L21/84
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/84
摘要： A method of fabricating a semiconductor device includes forming an insulation layer structure on a single-crystalline silicon substrate, forming a first insulation layer structure pattern comprising a first opening by etching a portion of the insulation layer structure, filling the first opening with a non-single-crystalline silicon layer, and forming a single-crystalline silicon pattern by irradiating a first laser beam onto the non-single-crystalline silicon layer. The method also includes forming a second insulation layer structure pattern comprising a second opening by etching a portion of the first insulation layer structure, filling the second opening with a non-single-crystalline silicon-germanium layer, and forming a single-crystalline silicon-germanium pattern by irradiating a second laser beam onto the non-single-crystalline silicon-germanium layer.
摘要翻译：一种制造半导体器件的方法包括在单晶硅衬底上形成绝缘层结构，通过蚀刻绝缘层结构的一部分形成包括第一开口的第一绝缘层结构图案，单晶硅层，并且通过将第一激光束照射到非单晶硅层上而形成单晶硅图案。该方法还包括通过蚀刻第一绝缘层结构的一部分来形成包括第二开口的第二绝缘层结构图案，用非单晶硅锗层填充第二开口，以及形成单晶硅 - 锗图案，通过将第二激光束照射到非单晶硅 - 锗层上。

29. 发明申请

US20070132022A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070132022A1
公开(公告)日：2007-06-14
申请号：US11301029
申请日：2005-12-13
申请人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee
发明人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee
IPC分类号： H01L27/12
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/02647
摘要： First and second preliminary epitaxial layers are grown from single-crystalline seeds in openings in an insulation layer until the first and second epitaxial layers are connected to each other. While the first and second preliminary epitaxial layers are being grown, a connection structure of a material having an amorphous state is formed on a portion of the insulation layer located between the first and second preliminary epitaxial layers. The material having an amorphous state is then changed into material having a single-crystalline state. Thus, portions of the first and second epitaxial layers are connected to each other through the connection structure so that the epitaxial layers and the connection structure constitute a single-crystalline structure layer that is free of voids for use as a channel layer or the like of a semiconductor device.
摘要翻译：第一和第二初步外延层从绝缘层的开口中的单晶种子生长直到第一和第二外延层彼此连接。当正在生长第一和第二初步外延层时，在位于第一和第二初步外延层之间的绝缘层的一部分上形成具有非晶状态的材料的连接结构。然后将具有非晶状态的材料变成具有单晶态的材料。因此，第一外延层和第二外延层的部分通过连接结构彼此连接，使得外延层和连接结构构成无空隙的单晶结构层，用作沟道层等半导体器件。

30. 发明申请

US20070007532A1 Stacked semiconductor device and related method 审中-公开
标题翻译：叠层半导体器件及相关方法
公开(公告)号：US20070007532A1
公开(公告)日：2007-01-11
申请号：US11474384
申请日：2006-06-26
申请人： Sung-Kwan Kang , Yu-Gyun Shin , Jong-Wook Lee , Yong-Hoon Son
发明人： Sung-Kwan Kang , Yu-Gyun Shin , Jong-Wook Lee , Yong-Hoon Son
IPC分类号： H01L29/10
CPC分类号： H01L21/8221 , H01L27/0688 , H01L27/11 , H01L27/1104
摘要： A stacked semiconductor device and a method for manufacturing the stacked semiconductor device are disclosed. The stacked semiconductor device comprises a seed layer doped with first impurities, a multilayer insulation pattern disposed on the seed layer comprising at least two insulation interlayer patterns stacked vertically on the seed layer and an opening. The stacked semiconductor device further comprises at least one active thin layer, wherein each of the at least one active thin layers is disposed on one of the at least two insulation interlayer patterns of the multilayer insulation pattern, and wherein the opening exposes a side surface of each of the at least one active thin layers. The stacked semiconductor device still further comprises and a first plug disposed on the seed layer and doped with second impurities substantially the same as the first impurities, wherein the opening exposes a top surface of the first plug.
摘要翻译：公开了层叠半导体器件及其制造方法。堆叠的半导体器件包括掺杂有第一杂质的种子层，设置在种子层上的多层绝缘图案，其包括在种子层上垂直堆叠的至少两个绝缘层间图案和开口。所述叠层半导体器件还包括至少一个有源薄层，其中所述至少一个有源薄层中的每一个设置在所述多层绝缘图案的所述至少两个绝缘夹层图案中的一个上，并且其中所述开口暴露所述多层绝缘图案的侧表面每个至少一个活性薄层。堆叠的半导体器件还包括第一插头，其设置在种子层上并掺杂有与第一杂质基本相同的第二杂质，其中开口暴露第一插塞的顶表面。

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