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1. 发明申请

US20070123062A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070123062A1
公开(公告)日：2007-05-31
申请号：US11605092
申请日：2006-11-28
申请人： Sung-Kwan Kang , Jong-Wook Lee , Yong-Hoon Son , Yu-Gyun Shin , Jun-Ho Lee
发明人： Sung-Kwan Kang , Jong-Wook Lee , Yong-Hoon Son , Yu-Gyun Shin , Jun-Ho Lee
IPC分类号： H01L21/336 , H01L29/76 , H01L21/00
CPC分类号： H01L29/66795 , H01L29/7851
摘要： In a semiconductor device and a method of manufacturing the semiconductor device, a plug and a channel structure are formed. The plug fills an opening and the channel structure extends upwardly from the plug. The channel structure has a substantially vertical sidewall. The opening is formed through an insulation structure located on a substrate. The plug and the channel structure comprise a material in a single crystalline state that is changed from an amorphous state by an irradiation of a laser beam. The channel structure is doped with impurities such as boron, phosphorus or arsenic.
摘要翻译：在半导体器件和半导体器件的制造方法中，形成插头和沟道结构。塞子填充开口并且通道结构从插头向上延伸。通道结构具有基本垂直的侧壁。开口通过位于基板上的绝缘结构形成。塞子和通道结构包括通过激光束的照射从非晶状态改变的单晶状态的材料。通道结构掺杂有杂质如硼，磷或砷。

2. 发明授权

US07560319B2 Method for fabricating a semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US07560319B2
公开(公告)日：2009-07-14
申请号：US11730262
申请日：2007-03-30
申请人： Sung-Kwan Kang , Yu-Gyun Shin , Jong-Wook Lee , Yong-Hoon Son
发明人： Sung-Kwan Kang , Yu-Gyun Shin , Jong-Wook Lee , Yong-Hoon Son
IPC分类号： H01L21/84
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/84
摘要： A method of fabricating a semiconductor device includes forming an insulation layer structure on a single-crystalline silicon substrate, forming a first insulation layer structure pattern comprising a first opening by etching a portion of the insulation layer structure, filling the first opening with a non-single-crystalline silicon layer, and forming a single-crystalline silicon pattern by irradiating a first laser beam onto the non-single-crystalline silicon layer. The method also includes forming a second insulation layer structure pattern comprising a second opening by etching a portion of the first insulation layer structure, filling the second opening with a non-single-crystalline silicon-germanium layer, and forming a single-crystalline silicon-germanium pattern by irradiating a second laser beam onto the non-single-crystalline silicon-germanium layer.
摘要翻译：一种制造半导体器件的方法包括在单晶硅衬底上形成绝缘层结构，通过蚀刻绝缘层结构的一部分形成包括第一开口的第一绝缘层结构图案，单晶硅层，并且通过将第一激光束照射到非单晶硅层上而形成单晶硅图案。该方法还包括通过蚀刻第一绝缘层结构的一部分来形成包括第二开口的第二绝缘层结构图案，用非单晶硅锗层填充第二开口，以及形成单晶硅 - 锗图案，通过将第二激光束照射到非单晶硅 - 锗层上。

3. 发明申请

US20070044706A1 Method of forming a crystalline structure and a method of manufacturing a semiconductor device 审中-公开
标题翻译：形成晶体结构的方法和半导体器件的制造方法
公开(公告)号：US20070044706A1
公开(公告)日：2007-03-01
申请号：US11509735
申请日：2006-08-25
申请人： Sung-Kwan Kang , Yu-Gyun Shin , Jong-Wook Lee , Yong-Hoon Son
发明人： Sung-Kwan Kang , Yu-Gyun Shin , Jong-Wook Lee , Yong-Hoon Son
IPC分类号： C30B1/00 , C30B28/02 , C30B3/00 , C30B5/00
CPC分类号： C30B23/02 , C30B23/025 , C30B25/18 , C30B29/06 , C30B29/08 , H01L21/02381 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/02658 , H01L21/28525
摘要： In a method of forming a single crystalline structure and a method of manufacturing a semiconductor device by using the method of forming the single crystalline structure, a single crystalline seed having elements combining with oxygen to form a network former capable of being easily connected to a network of oxide glass is formed. The single crystalline seed is epitaxially grown to form a single crystalline structure.
摘要翻译：在通过使用形成单晶结构的方法形成单晶结构的方法和制造半导体器件的方法中，具有与氧结合的元件以形成能够容易地连接到网络的网络形成器的单晶种子形成氧化物玻璃。将单晶种子外延生长以形成单晶结构。

4. 发明授权

US07396761B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07396761B2
公开(公告)日：2008-07-08
申请号：US11605092
申请日：2006-11-28
申请人： Sung-Kwan Kang , Jong-Wook Lee , Yong-Hoon Son , Yu-Gyun Shin , Jun-Ho Lee
发明人： Sung-Kwan Kang , Jong-Wook Lee , Yong-Hoon Son , Yu-Gyun Shin , Jun-Ho Lee
IPC分类号： H01L21/336 , H01L21/4763 , H01L21/44
CPC分类号： H01L29/66795 , H01L29/7851
摘要： In a semiconductor device and a method of manufacturing the semiconductor device, a plug and a channel structure are formed. The plug fills an opening and the channel structure extends upwardly from the plug. The channel structure has a substantially vertical sidewall. The opening is formed through an insulation structure located on a substrate. The plug and the channel structure comprise a material in a single crystalline state that is changed from an amorphous state by an irradiation of a laser beam. The channel structure is doped with impurities such as boron, phosphorus or arsenic.
摘要翻译：在半导体器件和半导体器件的制造方法中，形成插头和沟道结构。塞子填充开口并且通道结构从插头向上延伸。通道结构具有基本垂直的侧壁。开口通过位于基板上的绝缘结构形成。塞子和通道结构包括通过激光束的照射从非晶状态改变的单晶状态的材料。通道结构掺杂有杂质如硼，磷或砷。

5. 发明申请

US20070231976A1 Method for fabricating a semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20070231976A1
公开(公告)日：2007-10-04
申请号：US11730262
申请日：2007-03-30
申请人： Sung-Kwan Kang , Yu-Gyun Shin , Jong-Wook Lee , Yong-Hoon Son
发明人： Sung-Kwan Kang , Yu-Gyun Shin , Jong-Wook Lee , Yong-Hoon Son
IPC分类号： H01L21/84
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/84
摘要： A method of fabricating a semiconductor device includes forming an insulation layer structure on a single-crystalline silicon substrate, forming a first insulation layer structure pattern comprising a first opening by etching a portion of the insulation layer structure, filling the first opening with a non-single-crystalline silicon layer, and forming a single-crystalline silicon pattern by irradiating a first laser beam onto the non-single-crystalline silicon layer. The method also includes forming a second insulation layer structure pattern comprising a second opening by etching a portion of the first insulation layer structure, filling the second opening with a non-single-crystalline silicon-germanium layer, and forming a single-crystalline silicon-germanium pattern by irradiating a second laser beam onto the non-single-crystalline silicon-germanium layer.
摘要翻译：一种制造半导体器件的方法包括在单晶硅衬底上形成绝缘层结构，通过蚀刻绝缘层结构的一部分形成包括第一开口的第一绝缘层结构图案，单晶硅层，并且通过将第一激光束照射到非单晶硅层上而形成单晶硅图案。该方法还包括通过蚀刻第一绝缘层结构的一部分来形成包括第二开口的第二绝缘层结构图案，用非单晶硅锗层填充第二开口，以及形成单晶硅 - 锗图案，通过将第二激光束照射到非单晶硅 - 锗层上。

6. 发明申请

US20070007532A1 Stacked semiconductor device and related method 审中-公开
标题翻译：叠层半导体器件及相关方法
公开(公告)号：US20070007532A1
公开(公告)日：2007-01-11
申请号：US11474384
申请日：2006-06-26
申请人： Sung-Kwan Kang , Yu-Gyun Shin , Jong-Wook Lee , Yong-Hoon Son
发明人： Sung-Kwan Kang , Yu-Gyun Shin , Jong-Wook Lee , Yong-Hoon Son
IPC分类号： H01L29/10
CPC分类号： H01L21/8221 , H01L27/0688 , H01L27/11 , H01L27/1104
摘要： A stacked semiconductor device and a method for manufacturing the stacked semiconductor device are disclosed. The stacked semiconductor device comprises a seed layer doped with first impurities, a multilayer insulation pattern disposed on the seed layer comprising at least two insulation interlayer patterns stacked vertically on the seed layer and an opening. The stacked semiconductor device further comprises at least one active thin layer, wherein each of the at least one active thin layers is disposed on one of the at least two insulation interlayer patterns of the multilayer insulation pattern, and wherein the opening exposes a side surface of each of the at least one active thin layers. The stacked semiconductor device still further comprises and a first plug disposed on the seed layer and doped with second impurities substantially the same as the first impurities, wherein the opening exposes a top surface of the first plug.
摘要翻译：公开了层叠半导体器件及其制造方法。堆叠的半导体器件包括掺杂有第一杂质的种子层，设置在种子层上的多层绝缘图案，其包括在种子层上垂直堆叠的至少两个绝缘层间图案和开口。所述叠层半导体器件还包括至少一个有源薄层，其中所述至少一个有源薄层中的每一个设置在所述多层绝缘图案的所述至少两个绝缘夹层图案中的一个上，并且其中所述开口暴露所述多层绝缘图案的侧表面每个至少一个活性薄层。堆叠的半导体器件还包括第一插头，其设置在种子层上并掺杂有与第一杂质基本相同的第二杂质，其中开口暴露第一插塞的顶表面。

7. 发明授权

US07422965B2 Methods of fabricating p-type transistors including germanium channel regions 有权
标题翻译：制造包括锗通道区域的p型晶体管的方法
公开(公告)号：US07422965B2
公开(公告)日：2008-09-09
申请号：US11447436
申请日：2006-06-06
申请人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee
发明人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L29/1054 , H01L21/02532 , H01L21/02675 , H01L21/8221 , H01L27/0688 , H01L27/11 , H01L27/1104 , H01L29/16
摘要： A method of fabricating a transistor device includes forming a non-crystalline germanium layer on a seed layer. The non-crystalline germanium layer is selectively locally heated to about a melting point thereof to form a single-crystalline germanium layer on the seed layer. The non-crystalline germanium layer may be selectively locally heated, for example, by applying a laser to a portion of the non-crystalline germanium layer. Related devices are also discussed.
摘要翻译：制造晶体管器件的方法包括在种子层上形成非结晶锗层。选择性地将非结晶锗层局部加热至其熔点，以在籽晶层上形成单晶锗层。可以例如通过对非晶锗层的一部分施加激光来选择性地局部加热非晶锗层。还讨论了相关设备。

8. 发明申请

US20070048913A1 Method of manufacturing a stacked semiconductor device 有权
标题翻译：叠层半导体器件的制造方法
公开(公告)号：US20070048913A1
公开(公告)日：2007-03-01
申请号：US11510622
申请日：2006-08-28
申请人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee
发明人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee
IPC分类号： H01L21/84
CPC分类号： H01L21/76879 , H01L21/02381 , H01L21/0245 , H01L21/02502 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02675 , H01L21/28525 , H01L21/76898 , H01L21/8221 , H01L21/84 , H01L23/481 , H01L23/535 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： In a method of manufacturing a stacked semiconductor device, a seed layer including impurity regions may be prepared. A first insulation interlayer pattern having a first opening may be formed on the seed layer. A first SEG process may be carried out to form a first plug partially filling the first opening. A second SEG process may be performed to form a second plug filling the first opening. A third SEG process may be carried out to form a first channel layer on the first insulation interlayer pattern. A second insulation interlayer may be formed on the first channel layer. The second insulation interlayer, the first channel layer and the second plug arranged on the first plug may be removed to expose the first plug. The first plug may be removed to form a serial opening. The serial opening may be filled with a metal wiring.
摘要翻译：在制造叠层半导体器件的方法中，可以制备包括杂质区的晶种层。可以在种子层上形成具有第一开口的第一绝缘层间图案。可以执行第一SEG过程以形成部分填充第一开口的第一插塞。可以执行第二SEG过程以形成填充第一开口的第二塞子。可以执行第三SEG处理以在第一绝缘夹层图案上形成第一沟道层。可以在第一沟道层上形成第二绝缘中间层。布置在第一插头上的第二绝缘中间层，第一沟道层和第二插塞可以被去除以暴露第一插塞。可以移除第一个插头以形成串行开口。串行开口可以用金属布线填充。

9. 发明申请

US20060154453A1 Method(s) of forming a thin layer 有权
公开(公告)号：US20060154453A1
公开(公告)日：2006-07-13
申请号：US11329158
申请日：2006-01-11
申请人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee
发明人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee
IPC分类号： H01L21/20 , H01L21/205 , H01L21/36
CPC分类号： C30B25/04 , C30B29/06 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02639
摘要： A method of forming a thin layer including providing a first single-crystalline silicon layer partially exposed through an opening in an insulation pattern and forming an epitaxial layer on the first single-crystalline silicon layer and forming an amorphous silicon layer on the insulation pattern, the amorphous silicon layer having a first portion adjacent the epitaxial layer and a second portion spaced apart from the first portion, wherein the amorphous silicon layer is formed on the insulation pattern at substantially the same rate at the first portion and at a second portion. The amorphous silicon layer may be formed to a uniform thickness without a thinning defect.

10. 发明授权

US08481416B2 Semiconductor devices having contact plugs with stress buffer spacers and methods of fabricating the same 有权
标题翻译：具有接触插塞和应力缓冲垫片的半导体器件及其制造方法
公开(公告)号：US08481416B2
公开(公告)日：2013-07-09
申请号：US13205461
申请日：2011-08-08
申请人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee , Sun-Ghil Lee , In-Soo Jung , Young-Eun Lee , Deok-Hyung Lee
发明人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee , Sun-Ghil Lee , In-Soo Jung , Young-Eun Lee , Deok-Hyung Lee
IPC分类号： H01L21/20
CPC分类号： H01L29/7842 , H01L21/823425 , H01L21/823475 , H01L27/0688
摘要： A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate.
摘要翻译：半导体器件包括半导体衬底上的无机绝缘层，延伸穿过无机绝缘层以接触半导体衬底的接触插塞和设置在节点接触插塞和无机绝缘层之间的应力缓冲间隔件。该器件还包括设置在无机绝缘层上并具有沿着无机绝缘层延伸以接触接触插塞的源极/漏极区域的薄膜晶体管（TFT）。该器件还可以包括插入无机绝缘层和半导体衬底之间的蚀刻停止层。

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