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21. 发明申请

US20150008452A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150008452A1
公开(公告)日：2015-01-08
申请号：US14492628
申请日：2014-09-22
申请人： Heung-Kyu Park , Woo-Bin Song , Nam-Kyu Kim , Su-Jin Jung , Byeong-Chan Lee , Young-Pil Kim , Sun-Ghil Lee
发明人： Heung-Kyu Park , Woo-Bin Song , Nam-Kyu Kim , Su-Jin Jung , Byeong-Chan Lee , Young-Pil Kim , Sun-Ghil Lee
IPC分类号： H01L29/78 , H01L29/16 , H01L29/165
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L29/1608 , H01L29/165 , H01L29/66545 , H01L29/66621 , H01L29/66651 , H01L29/78
摘要： A semiconductor device comprises a substrate and first and second stress-generating epitaxial regions on the substrate and spaced apart from each other. A channel region is on the substrate and positioned between the first and second stress-generating epitaxial regions. A gate electrode is on the channel region. The channel region is an epitaxial layer, and the first and second stress-generating epitaxial regions impart a stress on the channel region.
摘要翻译：半导体器件包括衬底和在衬底上彼此间隔开的第一和第二应力产生外延区域。沟道区位于衬底上并位于第一和第二应力产生外延区之间。栅电极在沟道区上。沟道区域是外延层，并且第一和第二应力产生外延区域对沟道区域施加应力。

22. 发明授权

US08877583B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08877583B2
公开(公告)日：2014-11-04
申请号：US13728622
申请日：2012-12-27
申请人： Jin-Bum Kim , Young-Pil Kim , Kwan-Heum Lee , Sun-Ghil Lee
发明人： Jin-Bum Kim , Young-Pil Kim , Kwan-Heum Lee , Sun-Ghil Lee
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/285 , H01L21/768 , H01L49/02
CPC分类号： H01L21/285 , H01L21/76843 , H01L21/76849 , H01L21/76889 , H01L27/10855 , H01L28/91
摘要： In a method of forming an ohmic layer of a DRAM device, the metal silicide layer between the storage node contact plug and the lower electrode of a capacitor is formed as the ohmic layer by a first heat treatment under a first temperature and an instantaneous second heat treatment under a second temperature higher than the first temperature. Thus, the metal silicide layer has a thermo-stable crystal structure and little or no agglomeration occurs on the metal silicide layer in the high temperature process. Accordingly, the sheet resistance of the ohmic layer may not increase in spite of the subsequent high temperature process.
摘要翻译：在形成DRAM器件的欧姆层的方法中，通过在第一温度和瞬时第二次加热下的第一次热处理将存储节点接触插塞和电容器的下部电极之间的金属硅化物层形成为欧姆层在比第一温度高的第二温度下进行处理。因此，金属硅化物层具有热稳定的晶体结构，并且在高温工艺中在金属硅化物层上几乎或不发生聚集。因此，尽管随后的高温处理，欧姆层的薄层电阻也可能不增加。

23. 发明申请

US20130005096A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
公开(公告)号：US20130005096A1
公开(公告)日：2013-01-03
申请号：US13368584
申请日：2012-02-08
申请人： Heung-Kyu Park , Woo-Bin Song , Nam-Kyu Kim , Su-Jin Jung , Byeong-Chan Lee , Young-Pil Kim , Sun-Ghil Lee
发明人： Heung-Kyu Park , Woo-Bin Song , Nam-Kyu Kim , Su-Jin Jung , Byeong-Chan Lee , Young-Pil Kim , Sun-Ghil Lee
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L29/1608 , H01L29/165 , H01L29/66545 , H01L29/66621 , H01L29/66651 , H01L29/78
摘要： A semiconductor device comprises a substrate and first and second stress-generating epitaxial regions on the substrate and spaced apart from each other. A channel region is on the substrate and positioned between the first and second stress-generating epitaxial regions. A gate electrode is on the channel region. The channel region is an epitaxial layer, and the first and second stress-generating epitaxial regions impart a stress on the channel region.

24. 发明授权

US08853010B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08853010B2
公开(公告)日：2014-10-07
申请号：US13368584
申请日：2012-02-08
申请人： Heung-Kyu Park , Woo-Bin Song , Nam-Kyu Kim , Su-Jin Jung , Byeong-Chan Lee , Young-Pil Kim , Sun-Ghil Lee
发明人： Heung-Kyu Park , Woo-Bin Song , Nam-Kyu Kim , Su-Jin Jung , Byeong-Chan Lee , Young-Pil Kim , Sun-Ghil Lee
IPC分类号： H01L21/00 , H01L21/84 , H01L21/336 , H01L21/337 , H01L21/338 , H01L21/339 , H01L29/165 , H01L29/78 , H01L29/66 , H01L21/8238
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L29/1608 , H01L29/165 , H01L29/66545 , H01L29/66621 , H01L29/66651 , H01L29/78
摘要： A semiconductor device comprises a substrate and first and second stress-generating epitaxial regions on the substrate and spaced apart from each other. A channel region is on the substrate and positioned between the first and second stress-generating epitaxial regions. A gate electrode is on the channel region. The channel region is an epitaxial layer, and the first and second stress-generating epitaxial regions impart a stress on the channel region.
摘要翻译：半导体器件包括衬底和在衬底上彼此间隔开的第一和第二应力产生外延区域。沟道区位于衬底上并位于第一和第二应力产生外延区之间。栅电极在沟道区上。沟道区域是外延层，并且第一和第二应力产生外延区域对沟道区域施加应力。

25. 发明申请

US20120184079A1 METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120184079A1
公开(公告)日：2012-07-19
申请号：US13428900
申请日：2012-03-23
申请人： Jin-Bum Kim , Kwan-Heum Lee , Seung-Hun Lee , Byeong-Chan Lee , Sun-Ghil Lee
发明人： Jin-Bum Kim , Kwan-Heum Lee , Seung-Hun Lee , Byeong-Chan Lee , Sun-Ghil Lee
IPC分类号： H01L21/336
CPC分类号： H01L21/823425 , H01L21/28273 , H01L21/823418 , H01L27/11521 , H01L27/11524 , H01L29/66825
摘要： A semiconductor device can include a first gate electrode including a gate insulating pattern, a gate conductive pattern and a capping pattern that are sequentially stacked on a semiconductor substrate, and a first spacer of a low dielectric constant disposed on a lower sidewall of the first gate electrode. A second spacer of a high dielectric constant, that is greater than the low dielectric constant, is disposed on an upper sidewall of the first gate electrode above the first spacer.
摘要翻译：半导体器件可以包括第一栅电极，其包括依次层叠在半导体衬底上的栅极绝缘图案，栅极导电图案和覆盖图案，以及布置在第一栅极的下侧壁上的低介电常数的第一间隔物电极。高介电常数的第二间隔物大于低介电常数，设置在第一间隔物上方的第一栅电极的上侧壁上。

26. 发明授权

US08759182B2 Manufacturing method for semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US08759182B2
公开(公告)日：2014-06-24
申请号：US13459740
申请日：2012-04-30
申请人： Hyun-Jun Sim , Jae-Young Park , Hyun-Seung Kim , Sang-Bom Kang , Sun-Ghil Lee , Hyun-Deok Yang , Kang-Hun Moon , Han-Ki Lee , Sang-Mi Choi
发明人： Hyun-Jun Sim , Jae-Young Park , Hyun-Seung Kim , Sang-Bom Kang , Sun-Ghil Lee , Hyun-Deok Yang , Kang-Hun Moon , Han-Ki Lee , Sang-Mi Choi
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L21/28185 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/7833
摘要： A semiconductor device having an improved negative bias temperature instability lifetime characteristic is manufactured by forming a first insulating layer on a substrate, performing a first nitridation on the first insulating layer to form a second insulating layer, and sequentially performing a first and second anneal on the second insulating layer to form a third insulating layer, wherein the second anneal is performed at a higher temperature and with a different gas than the first anneal. A second nitridation is performed on the third insulating layer to form a fourth insulating layer, and a sequential third and fourth anneal on the fourth insulating layer forms a fifth insulating layer. The third anneal is performed at a higher temperature than the first anneal, and the fourth anneal is performed at a higher temperature than the second anneal and with a different gas than the third anneal.
摘要翻译：通过在基板上形成第一绝缘层，在第一绝缘层上进行第一次氮化，形成第二绝缘层，依次进行第一和第二退火，制造具有改善的负偏压温度不稳定寿命特性的半导体器件第二绝缘层以形成第三绝缘层，其中所述第二退火在比所述第一退火更高的温度和不同的气体下进行。在第三绝缘层上进行第二次氮化，以形成第四绝缘层，并且在第四绝缘层上顺序的第三和第四退火形成第五绝缘层。第三退火在比第一退火更高的温度下进行，第四退火在比第二退火更高的温度下进行，并且具有比第三退火不同的气体。

27. 发明授权

US07683421B2 NAND-type flash memory devices including selection transistors with an anti-punchthrough impurity region and methods of fabricating the same 有权
标题翻译：包括具有抗穿透杂质区域的选择晶体管的NAND型闪存器件及其制造方法
公开(公告)号：US07683421B2
公开(公告)日：2010-03-23
申请号：US11849533
申请日：2007-09-04
申请人： Gyoung-Ho Buh , Sun-Ghil Lee , Jong-Ryeol Yoo , Deok-Hyung Lee , Guk-Hyon Yon
发明人： Gyoung-Ho Buh , Sun-Ghil Lee , Jong-Ryeol Yoo , Deok-Hyung Lee , Guk-Hyon Yon
IPC分类号： H01L29/10
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/12 , H01L29/1083 , H01L29/78
摘要： A NAND-type flash memory device including selection transistors is provided. The device includes first and second impurity regions formed in a semiconductor substrate, and first and second selection gate patterns disposed on the semiconductor substrate between the first and second impurity regions. The first and second selection gate patterns are disposed adjacent to the first and second impurity regions, respectively. A plurality of cell gate patterns are disposed between the first and second selection gate patterns. A first anti-punchthrough impurity region that surrounds the first impurity region is provided in the semiconductor substrate. The first anti-punchthrough impurity region overlaps with a first edge of the first selection gate pattern adjacent to the first impurity region. A second anti-punchthrough impurity region that surrounds the second impurity region is provided in the semiconductor substrate. The second anti-punchthrough impurity region overlaps with a first edge of the second selection gate pattern adjacent to the second impurity region.
摘要翻译：提供了包括选择晶体管的NAND型闪速存储器件。该器件包括形成在半导体衬底中的第一和第二杂质区，以及设置在第一和第二杂质区之间的半导体衬底上的第一和第二选择栅极图案。第一和第二选择栅极图案分别与第一和第二杂质区相邻设置。多个单元栅极图案设置在第一和第二选择栅极图案之间。在半导体衬底中设置围绕第一杂质区的第一抗穿透杂质区。第一抗穿透杂质区域与第一选择栅极图案的与第一杂质区域相邻的第一边缘重叠。在半导体衬底中设置有围绕第二杂质区的第二抗穿透杂质区。第二抗穿透杂质区域与第二选择栅极图案的与第二杂质区域相邻的第一边缘重叠。

28. 发明申请

US20080135888A1 FinFET and method of manufacturing the same 有权
标题翻译： FinFET及其制造方法
公开(公告)号：US20080135888A1
公开(公告)日：2008-06-12
申请号：US12000071
申请日：2007-12-07
申请人： Deok-Hyung Lee , Sun-Ghil Lee , Jong-Ryeol Yoo , Si-Young Choi
发明人： Deok-Hyung Lee , Sun-Ghil Lee , Jong-Ryeol Yoo , Si-Young Choi
IPC分类号： H01L29/04 , H01L21/336
CPC分类号： H01L29/785 , H01L29/045 , H01L29/66795
摘要： A FinFET may include a semiconductor fin having a top surface and a sidewall having different crystal planes. A gate dielectric layer on the top surface and on the sidewall has different thicknesses. A gate electrode is formed on the gate dielectric layer across the top surface and sidewall of the semiconductor fin.
摘要翻译： FinFET可以包括具有顶表面和具有不同晶面的侧壁的半导体鳍片。顶表面和侧壁上的栅介电层具有不同的厚度。栅电极跨过半导体鳍片的顶表面和侧壁形成在栅介质层上。

29. 发明申请

US20100001349A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20100001349A1
公开(公告)日：2010-01-07
申请号：US12495501
申请日：2009-06-30
申请人： Jin-Bum Kim , Kwan-Heum Lee , Seung-Hun Lee , Byeong-Chan Lee , Sun-Ghil Lee
发明人： Jin-Bum Kim , Kwan-Heum Lee , Seung-Hun Lee , Byeong-Chan Lee , Sun-Ghil Lee
IPC分类号： H01L27/088
CPC分类号： H01L21/823425 , H01L21/823418 , H01L27/11521 , H01L27/11524 , H01L29/40114 , H01L29/66825
摘要： A semiconductor device can include a first gate electrode including a gate insulating pattern, a gate conductive pattern and a capping pattern that are sequentially stacked on a semiconductor substrate, and a first spacer of a low dielectric constant disposed on a lower sidewall of the first gate electrode. A second spacer of a high dielectric constant, that is greater than the low dielectric constant, is disposed on an upper sidewall of the first gate electrode above the first spacer.
摘要翻译：半导体器件可以包括第一栅电极，其包括依次层叠在半导体衬底上的栅极绝缘图案，栅极导电图案和覆盖图案，以及布置在第一栅极的下侧壁上的低介电常数的第一间隔物电极。高介电常数的第二间隔物大于低介电常数，设置在第一间隔物上方的第一栅电极的上侧壁上。

30. 发明申请

US20080048262A1 Fin field effect transistor and method of forming the same 审中-公开
标题翻译： Fin场效应晶体管及其形成方法
公开(公告)号：US20080048262A1
公开(公告)日：2008-02-28
申请号：US11892320
申请日：2007-08-22
申请人： Deok-Hyung Lee , Sun-Ghil Lee , Gyeong-Ho Buh , Jong-Ryeol Yoo , Si-Young Choi , Tai-Su Park
发明人： Deok-Hyung Lee , Sun-Ghil Lee , Gyeong-Ho Buh , Jong-Ryeol Yoo , Si-Young Choi , Tai-Su Park
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/7851 , H01L29/41791 , H01L29/66636 , H01L29/66795 , H01L2029/7858
摘要： Provided are a fin field effect transistor (FinFET) with recess source/drain regions, and a method of forming the same. One example embodiment may provide a semiconductor device including a fin provided on a substrate and extending in a first direction, the fin including a stepped portion, and a gate electrode extending in a second direction crossing the first direction, and provided on a top surface and side surfaces of the stepped portion of the fin.
摘要翻译：提供具有凹陷源极/漏极区域的鳍式场效应晶体管（FinFET）及其形成方法。一个示例性实施例可以提供一种半导体器件，其包括设置在基板上并沿第一方向延伸的鳍，所述鳍包括台阶部分，以及沿与第一方向交叉的第二方向延伸的栅电极，并且设置在顶表面上翅片的台阶部分的侧表面。

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