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1. 发明授权

US07842566B2 FinFET and method of manufacturing the same 有权
标题翻译： FinFET及其制造方法
公开(公告)号：US07842566B2
公开(公告)日：2010-11-30
申请号：US12000071
申请日：2007-12-07
申请人： Deok-Hyung Lee , Sun-Ghil Lee , Jong-Ryeol Yoo , Si-Young Choi
发明人： Deok-Hyung Lee , Sun-Ghil Lee , Jong-Ryeol Yoo , Si-Young Choi
IPC分类号： H01L21/8234
CPC分类号： H01L29/785 , H01L29/045 , H01L29/66795
摘要： A FinFET may include a semiconductor fin having a top surface and a sidewall having different crystal planes. A gate dielectric layer on the top surface and on the sidewall has different thicknesses. A gate electrode is formed on the gate dielectric layer across the top surface and sidewall of the semiconductor fin.
摘要翻译： FinFET可以包括具有顶表面和具有不同晶面的侧壁的半导体鳍片。顶表面和侧壁上的栅介电层具有不同的厚度。栅电极跨过半导体鳍片的顶表面和侧壁形成在栅介质层上。

2. 发明申请

US20080048262A1 Fin field effect transistor and method of forming the same 审中-公开
标题翻译： Fin场效应晶体管及其形成方法
公开(公告)号：US20080048262A1
公开(公告)日：2008-02-28
申请号：US11892320
申请日：2007-08-22
申请人： Deok-Hyung Lee , Sun-Ghil Lee , Gyeong-Ho Buh , Jong-Ryeol Yoo , Si-Young Choi , Tai-Su Park
发明人： Deok-Hyung Lee , Sun-Ghil Lee , Gyeong-Ho Buh , Jong-Ryeol Yoo , Si-Young Choi , Tai-Su Park
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/7851 , H01L29/41791 , H01L29/66636 , H01L29/66795 , H01L2029/7858
摘要： Provided are a fin field effect transistor (FinFET) with recess source/drain regions, and a method of forming the same. One example embodiment may provide a semiconductor device including a fin provided on a substrate and extending in a first direction, the fin including a stepped portion, and a gate electrode extending in a second direction crossing the first direction, and provided on a top surface and side surfaces of the stepped portion of the fin.
摘要翻译：提供具有凹陷源极/漏极区域的鳍式场效应晶体管（FinFET）及其形成方法。一个示例性实施例可以提供一种半导体器件，其包括设置在基板上并沿第一方向延伸的鳍，所述鳍包括台阶部分，以及沿与第一方向交叉的第二方向延伸的栅电极，并且设置在顶表面上翅片的台阶部分的侧表面。

3. 发明申请

US20080135888A1 FinFET and method of manufacturing the same 有权
标题翻译： FinFET及其制造方法
公开(公告)号：US20080135888A1
公开(公告)日：2008-06-12
申请号：US12000071
申请日：2007-12-07
申请人： Deok-Hyung Lee , Sun-Ghil Lee , Jong-Ryeol Yoo , Si-Young Choi
发明人： Deok-Hyung Lee , Sun-Ghil Lee , Jong-Ryeol Yoo , Si-Young Choi
IPC分类号： H01L29/04 , H01L21/336
CPC分类号： H01L29/785 , H01L29/045 , H01L29/66795
摘要： A FinFET may include a semiconductor fin having a top surface and a sidewall having different crystal planes. A gate dielectric layer on the top surface and on the sidewall has different thicknesses. A gate electrode is formed on the gate dielectric layer across the top surface and sidewall of the semiconductor fin.
摘要翻译： FinFET可以包括具有顶表面和具有不同晶面的侧壁的半导体鳍片。顶表面和侧壁上的栅介电层具有不同的厚度。栅电极跨过半导体鳍片的顶表面和侧壁形成在栅介质层上。

4. 发明授权

US07683421B2 NAND-type flash memory devices including selection transistors with an anti-punchthrough impurity region and methods of fabricating the same 有权
标题翻译：包括具有抗穿透杂质区域的选择晶体管的NAND型闪存器件及其制造方法
公开(公告)号：US07683421B2
公开(公告)日：2010-03-23
申请号：US11849533
申请日：2007-09-04
申请人： Gyoung-Ho Buh , Sun-Ghil Lee , Jong-Ryeol Yoo , Deok-Hyung Lee , Guk-Hyon Yon
发明人： Gyoung-Ho Buh , Sun-Ghil Lee , Jong-Ryeol Yoo , Deok-Hyung Lee , Guk-Hyon Yon
IPC分类号： H01L29/10
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/12 , H01L29/1083 , H01L29/78
摘要： A NAND-type flash memory device including selection transistors is provided. The device includes first and second impurity regions formed in a semiconductor substrate, and first and second selection gate patterns disposed on the semiconductor substrate between the first and second impurity regions. The first and second selection gate patterns are disposed adjacent to the first and second impurity regions, respectively. A plurality of cell gate patterns are disposed between the first and second selection gate patterns. A first anti-punchthrough impurity region that surrounds the first impurity region is provided in the semiconductor substrate. The first anti-punchthrough impurity region overlaps with a first edge of the first selection gate pattern adjacent to the first impurity region. A second anti-punchthrough impurity region that surrounds the second impurity region is provided in the semiconductor substrate. The second anti-punchthrough impurity region overlaps with a first edge of the second selection gate pattern adjacent to the second impurity region.
摘要翻译：提供了包括选择晶体管的NAND型闪速存储器件。该器件包括形成在半导体衬底中的第一和第二杂质区，以及设置在第一和第二杂质区之间的半导体衬底上的第一和第二选择栅极图案。第一和第二选择栅极图案分别与第一和第二杂质区相邻设置。多个单元栅极图案设置在第一和第二选择栅极图案之间。在半导体衬底中设置围绕第一杂质区的第一抗穿透杂质区。第一抗穿透杂质区域与第一选择栅极图案的与第一杂质区域相邻的第一边缘重叠。在半导体衬底中设置有围绕第二杂质区的第二抗穿透杂质区。第二抗穿透杂质区域与第二选择栅极图案的与第二杂质区域相邻的第一边缘重叠。

5. 发明申请

US20080083944A1 NAND-TYPE FLASH MEMORY DEVICES INCLUDING SELECTION TRANSISTORS WITH AN ANTI-PUNCHTHROUGH IMPURITY REGION AND METHODS OF FABRICATING THE SAME 有权
标题翻译： NAND型闪存存储器件，其中包括具有防伪突变区域的选择晶体管及其制造方法
公开(公告)号：US20080083944A1
公开(公告)日：2008-04-10
申请号：US11849533
申请日：2007-09-04
申请人： Gyoung-Ho Buh , Sun-Ghil Lee , Jong-Ryeol Yoo , Deok-Hyung Lee , Guk-Hyon Yon
发明人： Gyoung-Ho Buh , Sun-Ghil Lee , Jong-Ryeol Yoo , Deok-Hyung Lee , Guk-Hyon Yon
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/12 , H01L29/1083 , H01L29/78
摘要： A NAND-type flash memory device including selection transistors is provided. The device includes first and second impurity regions formed in a semiconductor substrate, and first and second selection gate patterns disposed on the semiconductor substrate between the first and second impurity regions. The first and second selection gate patterns are disposed adjacent to the first and second impurity regions, respectively. A plurality of cell gate patterns are disposed between the first and second selection gate patterns. A first anti-punchthrough impurity region that surrounds the first impurity region is provided in the semiconductor substrate. The first anti-punchthrough impurity region overlaps with a first edge of the first selection gate pattern adjacent to the first impurity region. A second anti-punchthrough impurity region that surrounds the second impurity region is provided in the semiconductor substrate. The second anti-punchthrough impurity region overlaps with a first edge of the second selection gate pattern adjacent to the second impurity region.
摘要翻译：提供了包括选择晶体管的NAND型闪速存储器件。该器件包括形成在半导体衬底中的第一和第二杂质区，以及设置在第一和第二杂质区之间的半导体衬底上的第一和第二选择栅极图案。第一和第二选择栅极图案分别与第一和第二杂质区相邻设置。多个单元栅极图案设置在第一和第二选择栅极图案之间。在半导体衬底中设置围绕第一杂质区的第一抗穿透杂质区。第一抗穿透杂质区域与第一选择栅极图案的与第一杂质区域相邻的第一边缘重叠。在半导体衬底中设置有围绕第二杂质区的第二抗穿透杂质区。第二抗穿透杂质区域与第二选择栅极图案的与第二杂质区域相邻的第一边缘重叠。

6. 发明申请

US20080073730A1 Semiconductor device and method for formimg the same 审中-公开
标题翻译：半导体器件和方法相同
公开(公告)号：US20080073730A1
公开(公告)日：2008-03-27
申请号：US11902404
申请日：2007-09-21
申请人： Deok-Hyung Lee , Sun-Ghil Lee , Jong-Ryeol Yoo , Byeong-Chan Lee , In-Soo Jung
发明人： Deok-Hyung Lee , Sun-Ghil Lee , Jong-Ryeol Yoo , Byeong-Chan Lee , In-Soo Jung
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7851 , H01L21/823431 , H01L29/66795
摘要： A method for forming a semiconductor device includes forming at least one gate electrode having a bent structure along a first direction on a semiconductor substrate, the gate electrode having first and second vertical portions, forming at least one semiconductor fin along a second direction on the semiconductor substrate, the semiconductor fin positioned between the first and second vertical portions of the gate electrode, forming a first epitaxial layer on the semiconductor fin, the first epitaxial layer including a source/drain impurity region, and forming a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including a contact impurity region.
摘要翻译：一种形成半导体器件的方法包括：在半导体衬底上沿着第一方向形成具有弯曲结构的至少一个栅电极，所述栅极具有第一和第二垂直部分，在半导体上沿着第二方向形成至少一个半导体鳍片衬底，所述半导体鳍片位于所述栅电极的所述第一和第二垂直部分之间，在所述半导体鳍片上形成第一外延层，所述第一外延层包括源/漏杂质区，以及在所述第一外延层上形成第二外延层层，第二外延层包括接触杂质区。

7. 发明授权

US06963094B2 Metal oxide semiconductor transistors having a drain punch through blocking region and methods for fabricating metal oxide semiconductor transistors having a drain punch through blocking region 有权
标题翻译：具有漏极穿通阻挡区域的金属氧化物半导体晶体管和用于制造具有漏极穿通阻挡区域的金属氧化物半导体晶体管的方法
公开(公告)号：US06963094B2
公开(公告)日：2005-11-08
申请号：US10394338
申请日：2003-03-21
申请人： Byeong-Chan Lee , Si-Young Choi , Chul-Sung Kim , Jong-Ryeol Yoo , Deok-Hyung Lee
发明人： Byeong-Chan Lee , Si-Young Choi , Chul-Sung Kim , Jong-Ryeol Yoo , Deok-Hyung Lee
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8242 , H01L27/108 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/417 , H01L29/76
CPC分类号： H01L29/0847 , H01L21/823425 , H01L27/10817 , H01L27/10873 , H01L27/10885 , H01L29/0653 , H01L29/1054 , H01L29/41766 , H01L29/66636 , H01L29/66651 , H01L29/66659
摘要： Metal oxide semiconductor transistors and devices with such transistors and methods of fabricating such transistors and devices are provided. Such transistors may have a silicon well region having a first surface and having spaced apart source and drain regions therein. A gate insulator is provided on the first surface of the silicon well region and disposed between the source and drain regions and a gate electrode is provided on the gate insulator. A region of insulating material is disposed between a first surface of the drain region and the silicon well region. The region of insulating material extends toward but not to the source region. A source electrode is provided that contacts the source region. A drain electrode contacts the drain region and the region of insulating material.
摘要翻译：提供了具有这种晶体管的金属氧化物半导体晶体管和器件以及制造这种晶体管和器件的方法。这种晶体管可以具有硅阱区，其具有第一表面并且在其中具有间隔开的源极和漏极区。栅极绝缘体设置在硅阱区的第一表面上并且设置在源极和漏极区之间，并且栅极被设置在栅极绝缘体上。绝缘材料的区域设置在漏极区域的第一表面和硅阱区域之间。绝缘材料的区域朝向但不延伸到源极区域。提供接触源区的源电极。漏电极接触漏极区域和绝缘材料区域。

8. 发明授权

US07511340B2 Semiconductor devices having gate structures and contact pads that are lower than the gate structures 失效
标题翻译：具有栅极结构的半导体器件和低于栅极结构的接触焊盘
公开(公告)号：US07511340B2
公开(公告)日：2009-03-31
申请号：US11779477
申请日：2007-07-18
申请人： Deok-Hyung Lee , Si-Young Choi , Byeong-Chan Lee , Chul-Sung Kim , In-Soo Jung , Jong-Ryeol Yoo
发明人： Deok-Hyung Lee , Si-Young Choi , Byeong-Chan Lee , Chul-Sung Kim , In-Soo Jung , Jong-Ryeol Yoo
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/10888 , H01L21/28525 , H01L21/76829 , H01L21/76832 , H01L21/76895 , H01L23/485 , H01L27/10894 , H01L2924/0002 , Y10S257/90 , H01L2924/00
摘要： Semiconductor devices have gate structures on a semiconductor substrate with first spacers on sidewalls of the respective gate structures. First contact pads are positioned between the gate structures and have heights lower than the heights of the gate structures. Second spacers are disposed on sidewalls of the first spacers and on exposed sidewalls of the first contact pads. Second contact pads are disposed on the first contact pads.
摘要翻译：半导体器件在半导体衬底上具有栅极结构，在相应栅极结构的侧壁上具有第一间隔物。第一接触垫位于栅极结构之间并且具有低于栅极结构的高度的高度。第二间隔件设置在第一间隔件的侧壁和第一接触垫的暴露的侧壁上。第二接触垫设置在第一接触垫上。

9. 发明授权

US07338867B2 Semiconductor device having contact pads and method for manufacturing the same 失效
标题翻译：具有接触垫的半导体器件及其制造方法
公开(公告)号：US07338867B2
公开(公告)日：2008-03-04
申请号：US10747925
申请日：2003-12-30
申请人： Deok-Hyung Lee , Si-Young Choi , Byeong-Chan Lee , Chul-Sung Kim , In-Soo Jung , Jong-Ryeol Yoo
发明人： Deok-Hyung Lee , Si-Young Choi , Byeong-Chan Lee , Chul-Sung Kim , In-Soo Jung , Jong-Ryeol Yoo
IPC分类号： H01L21/336 , H01L21/4763
CPC分类号： H01L27/10888 , H01L21/28525 , H01L21/76829 , H01L21/76832 , H01L21/76895 , H01L23/485 , H01L27/10894 , H01L2924/0002 , Y10S257/90 , H01L2924/00
摘要： Semiconductor devices have gate structures on a semiconductor substrate with first spacers on sidewalls of the respective gate structures. First contact pads are positioned between the gate structures and have heights lower than the heights of the gate structures. Second spacers are disposed on sidewalls of the first spacers and on exposed sidewalls of the first contact pads. Second contact pads are disposed on the first contact pads.
摘要翻译：半导体器件在半导体衬底上具有栅极结构，在相应栅极结构的侧壁上具有第一间隔物。第一接触垫位于栅极结构之间并且具有低于栅极结构的高度的高度。第二间隔件设置在第一间隔件的侧壁和第一接触垫的暴露的侧壁上。第二接触垫设置在第一接触垫上。

10. 发明申请

US20070257324A1 Semiconductor Devices Having Gate Structures and Contact Pads that are Lower than the Gate Structures 失效
标题翻译：具有栅极结构和低于栅极结构的接触焊盘的半导体器件
公开(公告)号：US20070257324A1
公开(公告)日：2007-11-08
申请号：US11779477
申请日：2007-07-18
申请人： Deok-Hyung Lee , Si-Young Choi , Byeong-Chan Lee , Chul-Sung Kim , In-Soo Jung , Jong-Ryeol Yoo
发明人： Deok-Hyung Lee , Si-Young Choi , Byeong-Chan Lee , Chul-Sung Kim , In-Soo Jung , Jong-Ryeol Yoo
IPC分类号： H01L27/088
CPC分类号： H01L27/10888 , H01L21/28525 , H01L21/76829 , H01L21/76832 , H01L21/76895 , H01L23/485 , H01L27/10894 , H01L2924/0002 , Y10S257/90 , H01L2924/00
摘要： Semiconductor devices have gate structures on a semiconductor substrate with first spacers on sidewalls of the respective gate structures. First contact pads are positioned between the gate structures and have heights lower than the heights of the gate structures. Second spacers are disposed on sidewalls of the first spacers and on exposed sidewalls of the first contact pads. Second contact pads are disposed on the first contact pads.
摘要翻译：半导体器件在半导体衬底上具有栅极结构，在相应栅极结构的侧壁上具有第一间隔物。第一接触垫位于栅极结构之间并且具有低于栅极结构的高度的高度。第二间隔件设置在第一间隔件的侧壁和第一接触垫的暴露的侧壁上。第二接触垫设置在第一接触垫上。

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