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21. 发明授权

US07330798B2 Operating voltage determination for an integrated circuit 有权
公开(公告)号：US07330798B2
公开(公告)日：2008-02-12
申请号：US11405432
申请日：2006-04-18
申请人： Dipesh Ishwerbhai Patel , Krisztian Flautner
发明人： Dipesh Ishwerbhai Patel , Krisztian Flautner
IPC分类号： G01R31/36 , G06F19/00
CPC分类号： G06F1/26 , G01R31/3004 , G01R31/31718 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Voltage-binning of individual integrated circuits is achieved by operating those integrated circuits at a plurality of required clock frequencies and for each of those frequencies determining the minimum supply voltage level which produces a pass result for a series of applied test vectors.

22. 发明授权

US07310755B2 Data retention latch provision within integrated circuits 有权
标题翻译：集成电路内的数据保持锁存器提供
公开(公告)号：US07310755B2
公开(公告)日：2007-12-18
申请号：US10779817
申请日：2004-02-18
申请人： Trevor Nigel Mudge , Todd Michael Austin , David Theodore Blaauw , Krisztian Flautner
发明人： Trevor Nigel Mudge , Todd Michael Austin , David Theodore Blaauw , Krisztian Flautner
IPC分类号： G01R31/28 , H03K3/00
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/3287 , G11C2207/2281 , Y02D10/126 , Y02D10/128 , Y02D10/171
摘要： An integrated circuit having a plurality of processing stages includes a low power mode controller operable to control the integrated circuit to switch between an operational mode and a standby mode. At least one of the processing stages has a non-delayed latch to capture a non-delayed value of an output signal from that processing stage and a delayed latch operable during the operational mode to capture a delayed value of the same signal. A difference between these two captured signals is indicative of the processing operation not being completed at the time the non-delayed signal was captured. The delayed latch is operable during the standby mode to retain the signal it captured whilst the non-delayed latch is powered down and loses its value. The delayed latch is formed to have a lower power consumption than the non-delayed latch.
摘要翻译：具有多个处理级的集成电路包括可操作以控制集成电路在操作模式和待机模式之间切换的低功率模式控制器。处理级中的至少一个具有非延迟锁存器，以捕获来自该处理级的输出信号的非延迟值，以及在操作模式期间可操作以捕获相同信号的延迟值的延迟锁存器。这两个捕获信号之间的差异表示在捕获非延迟信号时处理操作未完成。延迟锁存器在待机模式期间可操作以保持其捕获的信号，同时非延迟锁存器断电并失去其值。延迟锁存器形成为具有比非延迟锁存器更低的功耗。

23. 发明申请

US20070255516A1 Operating voltage determination for and integrated circuit 审中-公开
标题翻译：和集成电路的工作电压测定
公开(公告)号：US20070255516A1
公开(公告)日：2007-11-01
申请号：US11822062
申请日：2007-07-02
申请人： Dipesh Patel , Krisztian Flautner
发明人： Dipesh Patel , Krisztian Flautner
IPC分类号： G01R19/00
CPC分类号： G06F1/26 , G01R31/3004 , G01R31/31718 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Voltage-binning of individual integrated circuits is achieved by operating those integrated circuits at a plurality of required clock frequencies and for each of those frequencies determining the minimum supply voltage level which produces a pass result for a series of applied test vectors.
摘要翻译：通过以多个所需的时钟频率操作那些集成电路，并且为确定最小供电电压的那些频率中的每个频率来实现各个集成电路的电压分级，其产生一系列应用的测试向量的通过结果。

24. 发明申请

US20070022260A1 Data processor memory circuit 有权
公开(公告)号：US20070022260A1
公开(公告)日：2007-01-25
申请号：US11526687
申请日：2006-09-26
申请人： Krisztian Flautner , Trevor Mudge
发明人： Krisztian Flautner , Trevor Mudge
IPC分类号： G06F13/00
CPC分类号： G11C7/20 , G06F12/0893 , G06F2212/1028 , G11C5/14 , G11C5/143 , G11C5/144 , G11C7/22 , G11C8/10 , G11C8/12 , G11C11/417 , G11C2207/2227 , Y02D10/13
摘要： A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first voltage level corresponding to a first supply line and a second voltage level corresponding to a second supply line. The memory circuit comprises a readable state in which information stored in a memory cell is readable and an unreadable state in which information stored in said memory cell is reliably retained but unreadable. Changing the first voltage level but keeping the second voltage level substantially constant effects a transition between the readable state and the unreadable state. In use, the static power consumption of the memory cell in the unreadable state is less than static power consumption of the memory cell in the readable state.

25. 发明申请

US20070011476A1 Performance level selection in a data processing system 有权
标题翻译：数据处理系统中的性能等级选择
公开(公告)号：US20070011476A1
公开(公告)日：2007-01-11
申请号：US11520007
申请日：2006-09-13
申请人： Krisztian Flautner , Trevor Mudge
发明人： Krisztian Flautner , Trevor Mudge
IPC分类号： G06F1/00
CPC分类号： G06F1/324 , G06F1/3203 , Y02D10/126
摘要： Performance level selection is carried out by calculating a plurality of performance requests using a plurality of performance request calculating algorithms, combining those different performance requests to form a global performance request and then selecting a performance level in dependence upon the global performance level request. The performance request calculating algorithms can be arranged in a hierarchy with their performance requests evaluated in a sequence starting from the least dominant position in the hierarchy and moving through to the most dominant position in the hierarchy. Commands may accompany each performance level request to specify how it should be combined with other performance level requests.
摘要翻译：通过使用多个性能请求计算算法来计算多个性能请求来执行性能级别选择，组合那些不同的性能请求以形成全局性能请求，然后根据全局性能级别请求选择性能级别。可以将性能请求计算算法排列成层次结构，其性能请求以从层次结构中的最低主导位置开始的序列进行评估，并且移动到层次结构中最主要的位置。命令可以伴随每个性能级别请求来指定如何与其他性能级别请求组合。

26. 发明授权

US07131015B2 Performance level selection in a data processing system using a plurality of performance request calculating algorithms 有权
标题翻译：使用多个性能请求计算算法的数据处理系统中的性能级别选择
公开(公告)号：US07131015B2
公开(公告)日：2006-10-31
申请号：US10687972
申请日：2003-10-20
申请人： Krisztian Flautner , Trevor Nigel Mudge
发明人： Krisztian Flautner , Trevor Nigel Mudge
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3203 , Y02D10/126
摘要： Performance level selection is carried out by calculating a plurality of performance requests using a plurality of performance request calculating algorithms, combining those different performance requests to form a global performance request and then selecting a performance level in dependence upon the global performance level request. The performance request calculating algorithms can be arranged in a hierarchy with their performance requests evaluated in a sequence starting from the least dominant position in the hierarchy and moving through to the most dominant position in the hierarchy. Commands may accompany each performance level request to specify how it should be combined with other performance level requests.
摘要翻译：通过使用多个性能请求计算算法来计算多个性能请求来执行性能级别选择，组合那些不同的性能请求以形成全局性能请求，然后根据全局性能级别请求选择性能级别。可以将性能请求计算算法排列成层次结构，其性能请求以从层次结构中的最低主导位置开始的序列进行评估，并且移动到层次结构中最主要的位置。命令可以伴随每个性能级别请求来指定如何与其他性能级别请求组合。

27. 发明申请

US20050022094A1 Systematic and random error detection and recovery within processing stages of an integrated circuit 有权
标题翻译：在集成电路的处理阶段内的系统和随机的错误检测和恢复
公开(公告)号：US20050022094A1
公开(公告)日：2005-01-27
申请号：US10896997
申请日：2004-07-23
申请人： Trevor Mudge , Todd Austin , David Blaauw , Krisztian Flautner
发明人： Trevor Mudge , Todd Austin , David Blaauw , Krisztian Flautner
IPC分类号： G06F11/10 , G06F11/16 , G06F9/30 , G06F9/40 , G06F15/00 , H03M13/00
CPC分类号： G06F11/1695 , G06F9/3861 , G06F9/3869 , G06F11/0721 , G06F11/0793 , G06F11/104 , G06F11/1608 , G06F11/167 , G06F11/183
摘要： An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.
摘要翻译：集成电路包括多个处理级，每个处理级包括处理逻辑1014，非延迟信号捕获元件1016，延迟信号捕获元件1018和比较器1024.非延迟信号捕获元件1016捕获来自处理逻辑1014处于非延迟捕获时间。在稍后延迟的捕获时间，延迟信号捕获元件1018还从处理逻辑1014捕获一个值。错误检测电路1026和纠错电路1028检测并校正延迟值中的随机误差并提供错误检查的延迟比较器1024比较错误检查的延迟值和非延迟值，并且如果它们不相等，则这表示非延迟值被太早捕获，并且应该被错误检查的延迟值替换值。非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播在重新启动时钟之前通过后续的处理逻辑。调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。

28. 发明授权

US08650470B2 Error recovery within integrated circuit 有权
标题翻译：集成电路内的错误恢复
公开(公告)号：US08650470B2
公开(公告)日：2014-02-11
申请号：US12926084
申请日：2010-10-25
申请人： Krisztian Flautner , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge , David Bull
发明人： Krisztian Flautner , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge , David Bull
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/00 , G06F11/0706 , G06F11/0736 , G06F11/0754 , G06F11/0757 , G06F11/079 , G06F11/1402 , G06F11/1604
摘要： An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.
摘要翻译：集成电路包括具有错误检测和误差校正电路的一个或多个部分，并且其操作参数给出有限的非零误码率以及形成和操作以提供零错误率的一个或多个部分。

29. 发明授权

US08407537B2 Error recover within processing stages of an integrated circuit 有权
标题翻译：在集成电路的处理阶段内发生错误恢复
公开(公告)号：US08407537B2
公开(公告)日：2013-03-26
申请号：US12923908
申请日：2010-10-13
申请人： Krisztian Flautner , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge
发明人： Krisztian Flautner , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge
IPC分类号： G06F1/08 , G06F11/30
CPC分类号： G06F11/1695 , G06F11/0721 , G06F11/0793 , G06F11/104 , G06F11/1608 , G06F11/167 , G06F11/183
摘要： An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.
摘要翻译：集成电路包括多个处理级，每个处理级包括处理逻辑1014，非延迟信号捕获元件1016，延迟信号捕获元件1018和比较器1024.非延迟信号捕获元件1016捕获来自处理逻辑1014处于非延迟捕获时间。在稍后延迟的捕获时间，延迟信号捕获元件1018还从处理逻辑1014捕获一个值。错误检测电路1026和纠错电路1028检测并校正延迟值中的随机误差并提供错误检查的延迟比较器1024比较错误检查的延迟值和非延迟值，并且如果它们不相等，则这表示非延迟值被太早捕获，并且应该被错误检查的延迟值替换值。非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播在重新启动时钟之前通过后续的处理逻辑。调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。

30. 发明申请

US20110126051A1 Error recover within processing stages of an integrated circuit 有权
标题翻译：在集成电路的处理阶段内发生错误恢复
公开(公告)号：US20110126051A1
公开(公告)日：2011-05-26
申请号：US12923908
申请日：2010-10-13
申请人： Krisztian Flautner , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge
发明人： Krisztian Flautner , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge
IPC分类号： G06F11/267
CPC分类号： G06F11/1695 , G06F11/0721 , G06F11/0793 , G06F11/104 , G06F11/1608 , G06F11/167 , G06F11/183
摘要： An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.
摘要翻译：集成电路包括多个处理级，每个处理级包括处理逻辑1014，非延迟信号捕获元件1016，延迟信号捕获元件1018和比较器1024.非延迟信号捕获元件1016捕获来自处理逻辑1014处于非延迟捕获时间。在稍后延迟的捕获时间，延迟信号捕获元件1018还从处理逻辑1014捕获一个值。错误检测电路1026和纠错电路1028检测并校正延迟值中的随机误差并提供错误检查的延迟比较器1024比较错误检查的延迟值和非延迟值，并且如果它们不相等，则这表示非延迟值被太早捕获，并且应该被错误检查的延迟值替换值。非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播在重新启动时钟之前通过后续的处理逻辑。调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。

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