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1. 发明授权

US07598766B2 Customized silicon chips produced using dynamically configurable polymorphic network 有权
标题翻译：使用动态配置的多态网络生产的定制硅芯片
公开(公告)号：US07598766B2
公开(公告)日：2009-10-06
申请号：US11971349
申请日：2008-01-09
申请人： Martha Mercaldi-Kim , Mark Oskin , John Davis , Todd Austin , Mojtaba Mehrara
发明人： Martha Mercaldi-Kim , Mark Oskin , John Davis , Todd Austin , Mojtaba Mehrara
IPC分类号： H03K19/173
CPC分类号： H03K19/177
摘要： A fabrication technique called “component and polymorphic network,” in which semiconductor chips are made from small prefabricated bare electronic component dies, e.g., application specific integrated circuits (ASICs), that are assembled according to designer specifications, and bonded to a semiconductor substrate comprising the polymorphic network. The component and polymorphic network assembly has a low overhead for producing custom chips. In another exemplary embodiment, the polymorphic network can be combined with functional components in a single die. The interconnect scheme for ports on the polymorphic network can be configured or reconfigured with configuration data prior to the runtime of an application, to achieve different interconnect schemes.
摘要翻译：称为“组件和多态网络”的制造技术，其中半导体芯片由根据设计者规范组装的小型预制裸电子元件芯片（例如专用集成电路（ASIC））制成，并且结合到半导体衬底，该半导体衬底包括多态网络。组件和多态网络组件具有用于生产定制芯片的低开销。在另一个示例性实施例中，多晶型网络可以与单个管芯中的功能部件组合。多态网络上的端口的互连方案可以在应用程序的运行时间之前用配置数据配置或重新配置，以实现不同的互连方案。

2. 发明申请

US20070288798A1 Error detection and recovery within processing stages of an integrated circuit 有权
标题翻译：集成电路处理阶段内的错误检测和恢复
公开(公告)号：US20070288798A1
公开(公告)日：2007-12-13
申请号：US11889759
申请日：2007-08-16
申请人： Krisztian Flautner , Todd Austin , David Blaauw , Trevor Mudge
发明人： Krisztian Flautner , Todd Austin , David Blaauw , Trevor Mudge
IPC分类号： H02H3/05
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/3287 , G11C2207/2281 , Y02D10/126 , Y02D10/128 , Y02D10/171
摘要： An integrated circuit includes a plurality of processing stages each including processing logic 2, a non-delayed latch 4, a delayed latch 8 and a comparator 6. The non-delayed latch 4 captures an output from the processing logic 2 at a non-delayed capture time. At a later delayed capture time, the delayed latch 8 also captures a value from the processing logic 2. The comparator 6 compares these values and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.
摘要翻译：集成电路包括多个处理级，每个处理级包括处理逻辑2，非延迟锁存器4，延迟锁存器8和比较器6。非延迟锁存器4在非延迟捕获时间捕获来自处理逻辑2的输出。在稍后的延迟捕获时间，延迟锁存器8也捕获来自处理逻辑2的值。比较器6比较这些值，如果它们不相等，则表示非延迟值被捕获得太早，应该被延迟值代替。非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播在重新启动时钟之前通过后续的处理逻辑。调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。

3. 发明申请

US20060200699A1 Integrated circuit with error correction mechanisms to offset narrow tolerancing 有权
标题翻译：具有纠错机制的集成电路，以抵消窄公差
公开(公告)号：US20060200699A1
公开(公告)日：2006-09-07
申请号：US11301240
申请日：2005-12-13
申请人： Krisztian Flautner , David Bull , Todd Austin , David Blaauw , Trevor Mudge
发明人： Krisztian Flautner , David Bull , Todd Austin , David Blaauw , Trevor Mudge
IPC分类号： G06F11/00
CPC分类号： G06F11/24
摘要： An integrated circuit 2 has a specified range of runtime-variable operating parameters. Data processing circuits 4 within the integrated circuit 2 have associated error detection and error repair mechanisms 6. When operating within a narrow typical-case range of runtime-variable operating parameters the data processing circuits 4 operate correctly and substantially without error. When operating outside of this typical-case range but inside the specified range of permitted values for the run-time variable operating parameters, then the error detection and error repair circuit 6 operate to repair the errors which occur.
摘要翻译：集成电路2具有指定范围的运行时变量运行参数。集成电路2内的数据处理电路4具有相关联的错误检测和错误修复机制6。当数据处理电路4在运行时间可变运行参数的窄典型范围内运行时，数据处理电路4运行正确且基本无误。当在这种典型情况范围之外运行，但在运行时变量运行参数的允许值的指定范围内时，错误检测和错误修复电路6操作以修复发生的错误。

4. 发明申请

US20050207521A1 Recovery from errors in a data processing apparatus 有权
标题翻译：从数据处理装置的错误中恢复
公开(公告)号：US20050207521A1
公开(公告)日：2005-09-22
申请号：US11050446
申请日：2005-02-04
申请人： Seokwoo Lee , Todd Austin
发明人： Seokwoo Lee , Todd Austin
IPC分类号： G06F1/32 , H04L7/00
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/3287 , G11C2207/2281 , Y02D10/126 , Y02D10/128 , Y02D10/171
摘要： A data processing apparatus and method are provided for recovering from errors in the data processing apparatus. The data processing apparatus comprises processing logic operable to perform a data processing operation, and a plurality of sampling circuits, each sampling circuit being located at a predetermined point in the processing logic and operable to sample a value of an associated digital signal generated by the processing logic at that predetermined point. Each of the sampling circuits includes a backup latch for storing a backup copy of the associated digital signal value, and at least one of the sampling circuits is operable to temporally sample the value of the associated digital signal at a first time and at at least one later time, and to store as a backup copy a selected one of the sampled values representing a correct value. The value of the associated digital signal sampled at the first time is initially output from that sampling circuit, and that sampling circuit is operable to determine an occurrence of an error in the value of the associated digital signal sampled at the first time, and to issue an error signal upon determination of that error. The data processing apparatus further comprises error recovery logic operable in response to the error signal to implement a recovery procedure during which selected sampling circuits output as their sampled associated digital signal value the value stored in their backup latch.
摘要翻译：提供了一种用于从数据处理装置中的错误中恢复的数据处理装置和方法。数据处理装置包括可操作以执行数据处理操作的处理逻辑和多个采样电路，每个采样电路位于处理逻辑中的预定点处，并且可操作以对通过处理产生的相关数字信号的值进行采样在该预定点的逻辑。每个采样电路包括用于存储相关联的数字信号值的备份副本的备用锁存器，并且至少一个采样电路可用于在第一时间和至少一个时刻对相关联的数字信号的值进行时间采样以及将作为备份副本存储的代表正确值的所选取样值之一。首次从第一次采样的相关联的数字信号的值初始从该采样电路输出，并且该采样电路可用于确定在第一次采样的相关数字信号的值中出现的误差，并发出确定该错误时的错误信号。数据处理装置还包括可响应于误差信号操作的误差恢复逻辑，以实现恢复过程，在该恢复过程期间，所选择的采样电路作为其采样的相关数字信号输出值，存储在其备用锁存器中的值。

5. 发明申请

US20050125777A1 System and method of analyzing interpreted programs 有权
标题翻译：解析程序的系统和方法
公开(公告)号：US20050125777A1
公开(公告)日：2005-06-09
申请号：US10729100
申请日：2003-12-05
申请人： Brad Calder , Todd Austin , Don Yang , Timothy Sherwood
发明人： Brad Calder , Todd Austin , Don Yang , Timothy Sherwood
IPC分类号： G06F9/44 , G06F11/34
CPC分类号： G06F11/3457 , G06F11/3604 , G06F2201/865
摘要： A method for analyzing the performance of a program when running in an interpreted environment. An interpreter is a program that translates and executes another program. To analyze a binary in an interpreted environment, a mechanism is used to indicate points in the program at source, intermediate, or binary showing where information about the system is to be tracked/profiled/analyzed. Once these analysis points are determined, triggers are created in a separate file or inserted via program instrumentation into the binary to indicate to the interpreter when the analysis triggers need to be processed. The system being analyzed is then run via an interpreter. When one of these triggers occurs during execution, the interpreter calls analysis code passing it the appropriate information so that it may track statistics, metrics, and information about the program corresponding to the trigger.
摘要翻译：用于在解释的环境中运行时分析程序的性能的方法。解释器是一个翻译和执行另一个程序的程序。为了在解释环境中分析二进制文件，使用一种机制来表示程序中源，中间或二进制的点，显示系统信息的跟踪/分析/分析。一旦确定了这些分析点，触发器将在单独的文件中创建或通过程序工具插入到二进制文件中，以便在需要处理分析触发器时向解释器指示。被分析的系统然后通过解释器运行。当执行这些触发器之一时，解释器调用分析代码传递适当的信息，以便它可以跟踪与触发相对应的程序的统计信息，度量和信息。

6. 发明申请

US20050022094A1 Systematic and random error detection and recovery within processing stages of an integrated circuit 有权
标题翻译：在集成电路的处理阶段内的系统和随机的错误检测和恢复
公开(公告)号：US20050022094A1
公开(公告)日：2005-01-27
申请号：US10896997
申请日：2004-07-23
申请人： Trevor Mudge , Todd Austin , David Blaauw , Krisztian Flautner
发明人： Trevor Mudge , Todd Austin , David Blaauw , Krisztian Flautner
IPC分类号： G06F11/10 , G06F11/16 , G06F9/30 , G06F9/40 , G06F15/00 , H03M13/00
CPC分类号： G06F11/1695 , G06F9/3861 , G06F9/3869 , G06F11/0721 , G06F11/0793 , G06F11/104 , G06F11/1608 , G06F11/167 , G06F11/183
摘要： An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.
摘要翻译：集成电路包括多个处理级，每个处理级包括处理逻辑1014，非延迟信号捕获元件1016，延迟信号捕获元件1018和比较器1024.非延迟信号捕获元件1016捕获来自处理逻辑1014处于非延迟捕获时间。在稍后延迟的捕获时间，延迟信号捕获元件1018还从处理逻辑1014捕获一个值。错误检测电路1026和纠错电路1028检测并校正延迟值中的随机误差并提供错误检查的延迟比较器1024比较错误检查的延迟值和非延迟值，并且如果它们不相等，则这表示非延迟值被太早捕获，并且应该被错误检查的延迟值替换值。非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播在重新启动时钟之前通过后续的处理逻辑。调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。

7. 发明申请

US20200254582A1 JIG FOR SHARPENING MOWER BLADES 审中-公开
公开(公告)号：US20200254582A1
公开(公告)日：2020-08-13
申请号：US16347393
申请日：2018-03-02
申请人： TODD AUSTIN
发明人： TODD AUSTIN
IPC分类号： B24B41/06 , B24B3/36 , B24B23/00
摘要： A jig assembly is disclosed herein for holding a mower blade and a grinding tool during a sharpening operation on the mower blade. The jig assembly includes a mast, a fixture portion, and a jig portion. The fixture portion and jog portion can be mounted to the mast. The jig portion can include an arm and a tool-seat. The arm can include at least a first link and a second link movable relative to one another. The first link can be pivotally connected to the mast with a first pin defining an arm pivot axis. The first link and the second link can be interconnected whereby the second link is prevented from rotating in any plane that contains the arm pivot axis. The tool-seat can be disposed on the second link.

8. 发明申请

US20120262484A1 Motion Capture and Analysis at a Portable Computing Device 审中-公开
标题翻译：便携式计算设备的运动捕捉与分析
公开(公告)号：US20120262484A1
公开(公告)日：2012-10-18
申请号：US13419924
申请日：2012-03-14
申请人： David William Gottfeld , Robert Douglas Harris , Todd Austin Wright
发明人： David William Gottfeld , Robert Douglas Harris , Todd Austin Wright
IPC分类号： G09G5/377 , G06F3/041
CPC分类号： G09B5/065
摘要： Embodiments of the present invention are generally directed to devices, methods and instructions encoded on computer readable media for capturing motion and analyzing the captured motion at a portable computing device. In one exemplary embodiment, a motion capture and analysis application is provided. The application, when executed on a portable computing device, is configured to capture video of a subject (i.e., person) while the subject performs a selected action. The motion capture and analysis application provides various tools that allow an application user (e.g., trainer) to evaluate the motion of the subject during performance of the action.
摘要翻译：本发明的实施例通常涉及在计算机可读介质上编码的用于捕获运动并分析在便携式计算设备处的捕获的运动的装置，方法和指令。在一个示例性实施例中，提供了运动捕获和分析应用。当应用程序在便携式计算设备上执行时，被配置为在对象执行选择的动作时捕获被摄体（即，人）的视频。运动捕捉和分析应用程序提供各种工具，允许应用程序用户（例如，培训者）在执行动作期间评估对象的运动。

9. 发明授权

US07475394B2 System and method of analyzing interpreted programs 有权
标题翻译：解析程序的系统和方法
公开(公告)号：US07475394B2
公开(公告)日：2009-01-06
申请号：US10729100
申请日：2003-12-05
申请人： Brad Calder , Todd Austin , Don Yang , Timothy Sherwood
发明人： Brad Calder , Todd Austin , Don Yang , Timothy Sherwood
IPC分类号： G06F9/45
CPC分类号： G06F11/3457 , G06F11/3604 , G06F2201/865
摘要： A method for analyzing the performance of a program when running in an interpreted environment. An interpreter is a program that translates and executes another program. To analyze a binary in an interpreted environment, a mechanism is used to indicate points in the program at source, intermediate, or binary showing where information about the system is to be tracked/profiled/analyzed. Once these analysis points are determined, triggers are created in a separate file or inserted via program instrumentation into the binary to indicate to the interpreter when the analysis triggers need to be processed. The system being analyzed is then run via an interpreter. When one of these triggers occurs during execution, the interpreter calls analysis code passing it the appropriate information so that it may track statistics, metrics, and information about the program corresponding to the trigger.
摘要翻译：用于在解释的环境中运行时分析程序的性能的方法。解释器是一个翻译和执行另一个程序的程序。为了在解释环境中分析二进制文件，使用一种机制来表示程序中源，中间或二进制的点，显示系统信息的跟踪/分析/分析。一旦确定了这些分析点，触发器将在单独的文件中创建或通过程序工具插入到二进制文件中，以便在需要处理分析触发器时向解释器指示。被分析的系统然后通过解释器运行。当执行这些触发器之一时，解释器调用分析代码传递适当的信息，以便它可以跟踪与触发相对应的程序的统计信息，度量和信息。

10. 发明申请

US20080164907A1 CUSTOMIZED SILICON CHIPS PRODUCED USING DYNAMICALLY CONFIGURABLE POLYMORPHIC NETWORK 有权
标题翻译：使用动态可配置多晶网络生产的定制硅胶
公开(公告)号：US20080164907A1
公开(公告)日：2008-07-10
申请号：US11971349
申请日：2008-01-09
申请人： Martha Mercaldi-Kim , Mark Oskin , John Davis , Todd Austin , Mojtaba Mehrara
发明人： Martha Mercaldi-Kim , Mark Oskin , John Davis , Todd Austin , Mojtaba Mehrara
IPC分类号： H03K19/177
CPC分类号： H03K19/177
摘要： A fabrication technique called “component and polymorphic network,” in which semiconductor chips are made from small prefabricated bare electronic component dies, e.g., application specific integrated circuits (ASICs), that are assembled according to designer specifications, and bonded to a semiconductor substrate comprising the polymorphic network. The component and polymorphic network assembly has a low overhead for producing custom chips. In another exemplary embodiment, the polymorphic network can be combined with functional components in a single die. The interconnect scheme for ports on the polymorphic network can be configured or reconfigured with configuration data prior to the runtime of an application, to achieve different interconnect schemes.
摘要翻译：称为“组件和多态网络”的制造技术，其中半导体芯片由根据设计者规范组装的小型预制裸电子元件芯片（例如专用集成电路（ASIC））制成，并且结合到半导体衬底，该半导体衬底包括多态网络。组件和多态网络组件具有用于生产定制芯片的低开销。在另一个示例性实施例中，多晶型网络可以与单个管芯中的功能部件组合。多态网络上的端口的互连方案可以在应用程序的运行时间之前用配置数据配置或重新配置，以实现不同的互连方案。

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