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1. 发明申请

US20060018171A1 Memory system having fast and slow data reading mechanisms 有权
公开(公告)号：US20060018171A1
公开(公告)日：2006-01-26
申请号：US11150585
申请日：2005-06-13
申请人： Todd Austin , David Blaauw , Trevor Mudge , Dennis Sylvester , Krisztian Flautner
发明人： Todd Austin , David Blaauw , Trevor Mudge , Dennis Sylvester , Krisztian Flautner
IPC分类号： G11C7/00
CPC分类号： G06F9/3869 , G06F9/3861 , G06F11/141 , G11C7/04 , G11C7/1006 , G11C7/1039 , G11C7/1045 , G11C7/22 , G11C29/028 , G11C29/50 , G11C29/50012 , G11C2207/2281
摘要： There is provided a memory for storing data comprising: a fast data reading mechanism operable to read a data value from said memory to generate a fast read result that is output from said memory for further processing; a slow data reading mechanism operable to read said data value from said memory to generate a slow read result available after said fast read result has been output for further processing, said slow data reading mechanism being less prone to error in reading said data value than said fast data reading mechanism; a comparator operable to compare said fast read result and said slow read result to detect if said fast read result differs from said slow read result; and error repair logic operable if said comparator detects that said fast read result differs from said slow read result to suppress said further processing using said fast read result, to output said slow read result in place of said fast read result and to restart said further processing based upon said slow read result.

2. 发明申请

US20050022094A1 Systematic and random error detection and recovery within processing stages of an integrated circuit 有权
标题翻译：在集成电路的处理阶段内的系统和随机的错误检测和恢复
公开(公告)号：US20050022094A1
公开(公告)日：2005-01-27
申请号：US10896997
申请日：2004-07-23
申请人： Trevor Mudge , Todd Austin , David Blaauw , Krisztian Flautner
发明人： Trevor Mudge , Todd Austin , David Blaauw , Krisztian Flautner
IPC分类号： G06F11/10 , G06F11/16 , G06F9/30 , G06F9/40 , G06F15/00 , H03M13/00
CPC分类号： G06F11/1695 , G06F9/3861 , G06F9/3869 , G06F11/0721 , G06F11/0793 , G06F11/104 , G06F11/1608 , G06F11/167 , G06F11/183
摘要： An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.
摘要翻译：集成电路包括多个处理级，每个处理级包括处理逻辑1014，非延迟信号捕获元件1016，延迟信号捕获元件1018和比较器1024.非延迟信号捕获元件1016捕获来自处理逻辑1014处于非延迟捕获时间。在稍后延迟的捕获时间，延迟信号捕获元件1018还从处理逻辑1014捕获一个值。错误检测电路1026和纠错电路1028检测并校正延迟值中的随机误差并提供错误检查的延迟比较器1024比较错误检查的延迟值和非延迟值，并且如果它们不相等，则这表示非延迟值被太早捕获，并且应该被错误检查的延迟值替换值。非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播在重新启动时钟之前通过后续的处理逻辑。调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。

3. 发明申请

US20070288798A1 Error detection and recovery within processing stages of an integrated circuit 有权
标题翻译：集成电路处理阶段内的错误检测和恢复
公开(公告)号：US20070288798A1
公开(公告)日：2007-12-13
申请号：US11889759
申请日：2007-08-16
申请人： Krisztian Flautner , Todd Austin , David Blaauw , Trevor Mudge
发明人： Krisztian Flautner , Todd Austin , David Blaauw , Trevor Mudge
IPC分类号： H02H3/05
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/3287 , G11C2207/2281 , Y02D10/126 , Y02D10/128 , Y02D10/171
摘要： An integrated circuit includes a plurality of processing stages each including processing logic 2, a non-delayed latch 4, a delayed latch 8 and a comparator 6. The non-delayed latch 4 captures an output from the processing logic 2 at a non-delayed capture time. At a later delayed capture time, the delayed latch 8 also captures a value from the processing logic 2. The comparator 6 compares these values and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.
摘要翻译：集成电路包括多个处理级，每个处理级包括处理逻辑2，非延迟锁存器4，延迟锁存器8和比较器6。非延迟锁存器4在非延迟捕获时间捕获来自处理逻辑2的输出。在稍后的延迟捕获时间，延迟锁存器8也捕获来自处理逻辑2的值。比较器6比较这些值，如果它们不相等，则表示非延迟值被捕获得太早，应该被延迟值代替。非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播在重新启动时钟之前通过后续的处理逻辑。调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。

4. 发明申请

US20060200699A1 Integrated circuit with error correction mechanisms to offset narrow tolerancing 有权
标题翻译：具有纠错机制的集成电路，以抵消窄公差
公开(公告)号：US20060200699A1
公开(公告)日：2006-09-07
申请号：US11301240
申请日：2005-12-13
申请人： Krisztian Flautner , David Bull , Todd Austin , David Blaauw , Trevor Mudge
发明人： Krisztian Flautner , David Bull , Todd Austin , David Blaauw , Trevor Mudge
IPC分类号： G06F11/00
CPC分类号： G06F11/24
摘要： An integrated circuit 2 has a specified range of runtime-variable operating parameters. Data processing circuits 4 within the integrated circuit 2 have associated error detection and error repair mechanisms 6. When operating within a narrow typical-case range of runtime-variable operating parameters the data processing circuits 4 operate correctly and substantially without error. When operating outside of this typical-case range but inside the specified range of permitted values for the run-time variable operating parameters, then the error detection and error repair circuit 6 operate to repair the errors which occur.
摘要翻译：集成电路2具有指定范围的运行时变量运行参数。集成电路2内的数据处理电路4具有相关联的错误检测和错误修复机制6。当数据处理电路4在运行时间可变运行参数的窄典型范围内运行时，数据处理电路4运行正确且基本无误。当在这种典型情况范围之外运行，但在运行时变量运行参数的允许值的指定范围内时，错误检测和错误修复电路6操作以修复发生的错误。

5. 发明申请

US20060253666A1 Data processor memory circuit 有权
公开(公告)号：US20060253666A1
公开(公告)日：2006-11-09
申请号：US11353024
申请日：2006-02-14
申请人： Krisztian Flautner , David Blaauw , Trevor Mudge , Nam Kim , Steven Martin
发明人： Krisztian Flautner , David Blaauw , Trevor Mudge , Nam Kim , Steven Martin
IPC分类号： G06F12/00
CPC分类号： G11C7/20 , G06F12/0893 , G06F2212/1028 , G11C5/14 , G11C5/143 , G11C5/144 , G11C7/22 , G11C8/10 , G11C8/12 , G11C11/417 , G11C2207/2227 , Y02D10/13
摘要： A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first voltage level corresponding to a first supply line and a second voltage level corresponding to a second supply line. The memory circuit comprises a readable state in which information stored in a memory cell is readable and an unreadable state in which information stored in said memory cell is reliably retained but unreadable. Changing the first voltage level but keeping the second voltage level substantially constant effects a transition between the readable state and the unreadable state. In use, the static power consumption of the memory cell in the unreadable state is less than static power consumption of the memory cell in the readable state.

6. 发明申请

US20050097228A1 Data processing system performance counter 有权
标题翻译：数据处理系统性能计数器
公开(公告)号：US20050097228A1
公开(公告)日：2005-05-05
申请号：US10687924
申请日：2003-10-20
申请人： Krisztian Flautner , Trevor Mudge , David Flynn
发明人： Krisztian Flautner , Trevor Mudge , David Flynn
IPC分类号： G06F1/04 , G06F1/32 , G06F3/00
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A performance counter accumulates a value by periodically adding a variable increment value representing the amount of work performed. The increment value can be varied in dependence upon the processor clock frequency and may be adjusted under hardware and/or software control.
摘要翻译：性能计数器通过周期性地添加表示所执行的工作量的可变增量值累加值。增量值可以根据处理器时钟频率而变化，并且可以在硬件和/或软件控制下进行调整。

7. 发明申请

US20070022260A1 Data processor memory circuit 有权
公开(公告)号：US20070022260A1
公开(公告)日：2007-01-25
申请号：US11526687
申请日：2006-09-26
申请人： Krisztian Flautner , Trevor Mudge
发明人： Krisztian Flautner , Trevor Mudge
IPC分类号： G06F13/00
CPC分类号： G11C7/20 , G06F12/0893 , G06F2212/1028 , G11C5/14 , G11C5/143 , G11C5/144 , G11C7/22 , G11C8/10 , G11C8/12 , G11C11/417 , G11C2207/2227 , Y02D10/13
摘要： A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first voltage level corresponding to a first supply line and a second voltage level corresponding to a second supply line. The memory circuit comprises a readable state in which information stored in a memory cell is readable and an unreadable state in which information stored in said memory cell is reliably retained but unreadable. Changing the first voltage level but keeping the second voltage level substantially constant effects a transition between the readable state and the unreadable state. In use, the static power consumption of the memory cell in the unreadable state is less than static power consumption of the memory cell in the readable state.

8. 发明申请

US20070011476A1 Performance level selection in a data processing system 有权
标题翻译：数据处理系统中的性能等级选择
公开(公告)号：US20070011476A1
公开(公告)日：2007-01-11
申请号：US11520007
申请日：2006-09-13
申请人： Krisztian Flautner , Trevor Mudge
发明人： Krisztian Flautner , Trevor Mudge
IPC分类号： G06F1/00
CPC分类号： G06F1/324 , G06F1/3203 , Y02D10/126
摘要： Performance level selection is carried out by calculating a plurality of performance requests using a plurality of performance request calculating algorithms, combining those different performance requests to form a global performance request and then selecting a performance level in dependence upon the global performance level request. The performance request calculating algorithms can be arranged in a hierarchy with their performance requests evaluated in a sequence starting from the least dominant position in the hierarchy and moving through to the most dominant position in the hierarchy. Commands may accompany each performance level request to specify how it should be combined with other performance level requests.
摘要翻译：通过使用多个性能请求计算算法来计算多个性能请求来执行性能级别选择，组合那些不同的性能请求以形成全局性能请求，然后根据全局性能级别请求选择性能级别。可以将性能请求计算算法排列成层次结构，其性能请求以从层次结构中的最低主导位置开始的序列进行评估，并且移动到层次结构中最主要的位置。命令可以伴随每个性能级别请求来指定如何与其他性能级别请求组合。

9. 发明申请

US20080077824A1 Storage of data in data stores having some faulty storage locations 有权
标题翻译：将数据存储在具有一些故障存储位置的数据存储中
公开(公告)号：US20080077824A1
公开(公告)日：2008-03-27
申请号：US11822150
申请日：2007-07-02
申请人： Trevor Mudge , Ganesh Dasika , David Roberts
发明人： Trevor Mudge , Ganesh Dasika , David Roberts
IPC分类号： G06F11/07 , G06F11/14 , G06F17/30
CPC分类号： G06F11/1064
摘要： There is disclosed data storage control circuitry for controlling storage and retrieval of data in a data store in which data is stored in data blocks, each of said data blocks comprising a plurality of bits, said data store comprising at least one faulty bit within at least some of said data blocks. The data storage control circuitry comprising: a group data store related to said data store for storing data grouping together data blocks from said data store that have at least one faulty bit, into groups of at least two of said data blocks, said data blocks being grouped such that for each group at least one of said data blocks has a non-faulty bit for each of said plurality of bit locations in said data blocks; and a selector data store for storing indicators for each of said groups of data blocks, said indicators indicating which bits of said data blocks within a group are said non-faulty bits; data storage logic for controlling storage of data in said data store, said data storage logic being responsive to an instruction to store data in a data block that is present in one of said groups of data blocks, to store said data in each of said data blocks within said group of data blocks; and data access logic for controlling retrieval of data from said data store, said data access logic being responsive to an instruction to read data from a data block that is present in one of said groups of data blocks, to read each of said plurality of bits from one of said data blocks within said group said one of said data blocks being selected for each bit in dependence upon said stored indicators for said group such that no faulty bits are read.
摘要翻译：公开了用于控制数据存储中数据的存储和检索的数据存储控制电路，其中数据被存储在数据块中，每个所述数据块包括多个位，所述数据存储器至少包括一个至少一个故障位一些所述数据块。所述数据存储控制电路包括：与所述数据存储相关的组数据存储，用于存储从具有至少一个故障位的所述数据存储器将数据块分组在一起的数据到成为至少两个所述数据块的组中的数据块，所述数据块是分组，使得对于每个组，所述数据块中的至少一个数据块对于所述数据块中的所述多个位位置中的每一个具有非故障位; 以及选择器数据存储器，用于存储每个所述数据块组的指示符，所述指示符指示组内的所述数据块的哪些位是所述非故障位; 用于控制所述数据存储器中的数据存储的数据存储逻辑，所述数据存储逻辑响应于在存在于所述数据块组之一中的数据块中存储数据的指令，以将所述数据存储在每个所述数据中所述数据块组内的块; 以及用于控制从所述数据存储器检索数据的数据访问逻辑，所述数据访问逻辑响应于从存在于所述数据块之一中的数据块读取数据的指令，以读取所述多个位中的每一个根据所述组的所述存储的指示符，从所述组中的所述数据块中的一个所述数据块中的一个被选择用于每个位，使得不读取故障位。

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