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21. 发明申请

US20130339673A1 INTRA-INSTRUCTIONAL TRANSACTION ABORT HANDLING 有权
公开(公告)号：US20130339673A1
公开(公告)日：2013-12-19
申请号：US13524370
申请日：2012-06-15
申请人： Brenton F. Belmar , Mark S. Farrell , Christian Jacobi , Timothy J. Slegel
发明人： Brenton F. Belmar , Mark S. Farrell , Christian Jacobi , Timothy J. Slegel
IPC分类号： G06F9/30
CPC分类号： G06F9/3857 , G06F9/30 , G06F9/30043 , G06F9/30087 , G06F9/3834 , G06F9/3859 , G06F9/466 , G06F9/467
摘要： Embodiments relate to intra-instructional transaction abort handling. An aspect includes using an emulation routine to execute an instruction within a transaction. The instruction includes at least one unit of operation. The transaction effectively delays committing stores to memory until the transaction has completed successfully. After receiving an abort indication, emulation of the instruction is terminated prior to completing the execution of the instruction. The instruction is terminated after the emulation routine completes any previously initiated unit of operation of the instruction.

22. 发明申请

US20130339629A1 TRACKING TRANSACTIONAL EXECUTION FOOTPRINT 有权
标题翻译：跟踪交易执行功能
公开(公告)号：US20130339629A1
公开(公告)日：2013-12-19
申请号：US13524355
申请日：2012-06-15
申请人： Khary J. Alexander , Jonathan T. Hsieh , Christian Jacobi , Patrick M. West
发明人： Khary J. Alexander , Jonathan T. Hsieh , Christian Jacobi , Patrick M. West
IPC分类号： G06F12/08
CPC分类号： G06F12/08 , G06F9/30 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3013 , G06F9/3834 , G06F9/3859 , G06F9/466 , G06F9/467 , G06F12/0815 , G06F12/084
摘要： Embodiments relate to tracking a transactional execution footprint. An aspect includes receiving a store instruction which includes store data. It is determined if the store instruction is executing within a transaction that effectively delays committing stores to a shared cache until the transaction has completed. The store data is stored to a cache line in a local cache. The cache line is marked as dirty if the transaction is active. The stored data that was marked as dirty in the local cache is invalidated if the transaction has terminated abnormally. The stored data is un-marked if it is determined that the transaction has successfully ended.
摘要翻译：实施例涉及跟踪事务执行足迹。一方面包括接收包括存储数据的存储指令。确定存储指令是否在事务内执行，以有效地将提交存储延迟到共享高速缓存，直到事务完成。存储数据被存储到本地高速缓存中的高速缓存行。如果事务处于活动状态，则缓存行被标记为脏。如果事务异常终止，则在本地缓存中标记为脏的存储数据将无效。如果确定交易已成功结束，则存储的数据将被取消标记。

23. 发明申请

US20130339627A1 MONITORING A VALUE IN STORAGE WITHOUT REPEATED STORAGE ACCESS 有权
标题翻译：在没有重复存储访问的情况下监控存储的价值
公开(公告)号：US20130339627A1
公开(公告)日：2013-12-19
申请号：US13524063
申请日：2012-06-15
申请人： Khary J. Alexander , Ute Gaertner , Jonathan T. Hsieh , Christian Jacobi , Timothy J. Slegel
发明人： Khary J. Alexander , Ute Gaertner , Jonathan T. Hsieh , Christian Jacobi , Timothy J. Slegel
IPC分类号： G06F12/08
CPC分类号： G06F12/0808 , G06F3/0653 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F12/0891
摘要： A technique is provided for monitoring a value without repeated storage access. A processing circuit processes an instruction of a program that specifies a memory address of a memory location to be monitored. The processing circuit configures a monitor station for monitoring the memory location. The memory location includes a state descriptor for the program. The processing circuit receives a cross-invalidate request from a memory controller. The cross-invalidate request indicates to the monitor station that content of the memory location has been changed by another processing circuit.
摘要翻译：提供了一种用于监视值而不重复存储访问的技术。处理电路处理指定要监视的存储器位置的存储器地址的程序的指令。处理电路配置用于监视存储器位置的监视站。存储器位置包括程序的状态描述符。处理电路从存储器控制器接收到交叉无效请求。交叉无效请求向监视台指示存储器位置的内容已被另一处理电路改变。

24. 发明申请

US20130339618A1 AVOIDING ABORTS DUE TO ASSOCIATIVITY CONFLICTS IN A TRANSACTIONAL ENVIRONMENT 有权
标题翻译：避免交易环境中的相关冲突
公开(公告)号：US20130339618A1
公开(公告)日：2013-12-19
申请号：US13524378
申请日：2012-06-15
申请人： Khary J. Alexander , Jonathan T. Hsieh , Christian Jacobi
发明人： Khary J. Alexander , Jonathan T. Hsieh , Christian Jacobi
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3859 , G06F9/467
摘要： Embodiments relate to a transactional read footprint after a cache line eviction. An aspect includes executing one or more read instructions in an active transaction. A cross invalidate (XI) request for a target cache line is received, and it is determined if the target cache line is part of a congruence class in a local cache. It is further determined whether an extension flag associated with the congruence class is set. The extension flag is used to indicate that cache lines of the congruence class associated with the active transaction have been replaced based only on being least recently used and that the target cache line is not in the cache. Execution of the active transaction continues based on determining that the extension flag is not set. Execution of the active transaction is aborted based on determining that the extension flag is set.
摘要翻译：实施例涉及缓存线驱逐之后的事务读取占用空间。一个方面包括在活动事务中执行一个或多个读取指令。接收对目标高速缓存行的交叉无效（XI）请求，并且确定目标高速缓存行是否是本地高速缓存中的同余类的一部分。进一步确定是否设置与同余类相关联的扩展标志。扩展标志用于指示仅基于最近最少使用的并且目标高速缓存行不在高速缓存中，与活动事务相关联的一致类的高速缓存行已被替换。基于确定扩展标志未设置，继续执行活动事务。基于确定扩展标志被设置，中止活动事务的执行。

25. 发明授权

US08495341B2 Instruction length based cracking for instruction of variable length storage operands 有权
标题翻译：指令长度为可变长度存储操作数指令的破解
公开(公告)号：US08495341B2
公开(公告)日：2013-07-23
申请号：US12707163
申请日：2010-02-17
申请人： Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi , Wen Li
发明人： Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi , Wen Li
IPC分类号： G06F9/30
CPC分类号： G06F9/30032 , G06F9/30149 , G06F9/3016 , G06F9/3017
摘要： A method, information processing system, and computer program product manage variable operand length instructions. At least one variable operand length instruction is received. The at least one variable operand length instruction is analyzed. A length of at least one operand in the variable operand length instruction is identified based on the analyzing. The at least one variable operand length instruction is organized into a set of unit of operations. The set of unit of operations are executed. The executing increases one or more performance metrics of the at least one variable operand length instruction.
摘要翻译：一种方法，信息处理系统和计算机程序产品管理可变操作数长度指令。接收至少一个可变操作数长度指令。分析至少一个可变操作数长度指令。基于分析来识别可变操作数长度指令中的至少一个操作数的长度。所述至少一个可变操作数长度指令被组织成一组操作单元。执行操作单元的集合。所述执行增加所述至少一个可变操作数长度指令的一个或多个性能度量。

26. 发明授权

US08468325B2 Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors 有权
公开(公告)号：US08468325B2
公开(公告)日：2013-06-18
申请号：US12644923
申请日：2009-12-22
申请人： Gregory W. Alexander , Khary J. Alexander , Brian Curran , Jonathan T. Hsieh , Christian Jacobi , James R. Mitchell , Brian R. Prasky , Brian W. Thompto
发明人： Gregory W. Alexander , Khary J. Alexander , Brian Curran , Jonathan T. Hsieh , Christian Jacobi , James R. Mitchell , Brian R. Prasky , Brian W. Thompto
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3834
摘要： A method and information processing system manage load and store operations executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard prediction table is created based on the determination. The entry includes at least an instruction address of the instruction that has been executed and a hazard indicating flag associated with the instruction. The hazard indicating flag indicates that the instruction has encountered the operand store compare hazard. When a load instruction is associated with the hazard indicating flag the load instruction becomes dependent upon all store instructions associated with a substantially similar flag.

27. 发明授权

US08302043B2 Verification of logic circuit designs using dynamic clock gating 有权
标题翻译：使用动态时钟门控验证逻辑电路设计
公开(公告)号：US08302043B2
公开(公告)日：2012-10-30
申请号：US12876319
申请日：2010-09-07
申请人： Christian Habermann , Christian Jacobi , Matthias Pflanz , Hans-Werner Tast , Ralf Winkelmann
发明人： Christian Habermann , Christian Jacobi , Matthias Pflanz , Hans-Werner Tast , Ralf Winkelmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/78
摘要： A method and system for verifying a logic circuit design using dynamic clock gating is disclosed. The method comprises choosing at least one master seed to determine initial values as initialization for said logic circuit and/or stimuli data for at least one interface of said logic circuit, choosing at least two different dynamic clock gating configurations for every chosen master seed, executing a functional simulation with said logic circuit for every chosen dynamic clock gating configuration by using said determined initialization and/or stimuli data based on a corresponding master seed, comparing simulation results of functional simulations against each other executed with said logic circuit for at least two different chosen dynamic clock gating configurations, and reporting an error if said at least two simulation results are not identical.
摘要翻译：公开了一种使用动态时钟门控验证逻辑电路设计的方法和系统。所述方法包括：选择至少一个主粒子以将初始值确定为所述逻辑电路的初始化和/或所述逻辑电路的至少一个接口的刺激数据，为每个所选择的主子选择至少两个不同的动态时钟选通配置，执行通过使用基于对应的主子种的所述确定的初始化和/或刺激数据，针对每个所选择的动态时钟门控配置，利用所述逻辑电路进行功能仿真，将与所述逻辑电路执行的功能模拟的仿真结果相互比较，用于至少两个不同的所选择的动态时钟门控配置，并且如果至少两个模拟结果不相同，则报告错误。

28. 发明申请

US20110296114A1 ATOMIC EXECUTION OVER ACCESSES TO MULTIPLE MEMORY LOCATIONS IN A MULTIPROCESSOR SYSTEM 有权
标题翻译：在多处理器系统中访问多个存储器位置的原子执行
公开(公告)号：US20110296114A1
公开(公告)日：2011-12-01
申请号：US12786787
申请日：2010-05-25
申请人： Mark S. Farrell , Jonathan T. Hsieh , Christian Jacobi , Timothy J. Slegel
发明人： Mark S. Farrell , Jonathan T. Hsieh , Christian Jacobi , Timothy J. Slegel
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F9/30043 , G06F9/30072 , G06F9/3834 , G06F9/528 , G06F12/0815 , G06F2212/62
摘要： A method and central processing unit supporting atomic access of shared data by a sequence of memory access operations. A processor status flag is reset. A processor executes, subsequent to the setting of the processor status flag, a sequence of program instructions with instructions accessing a subset of shared data contained within its local cache. During execution of the sequence of program instructions and in response to a modification by another processor of the subset of shared data, the processor status flag is set. Subsequent to the executing the sequence of program instructions and based upon the state of the processor status flag, either a first program processing or a second program processing is executed. In some examples the first program processing includes storing results data into the local cache and the second program processing includes discarding the results data.
摘要翻译：一种通过一系列存储器访问操作支持共享数据的原子访问的方法和中央处理单元。处理器状态标志被复位。在处理器状态标志的设置之后，处理器执行具有访问包含在其本地高速缓存中的共享数据的子集的指令的程序指令序列。在程序指令序列的执行期间，并且响应于另一个处理器对共享数据子集的修改，处理器状态标志被置位。在执行程序指令序列之后，并且基于处理器状态标志的状态，执行第一程序处理或第二程序处理。在一些示例中，第一程序处理包括将结果数据存储到本地高速缓存中，并且第二程序处理包括丢弃结果数据。

29. 发明授权

US08015362B2 Method and system for handling cache coherency for self-modifying code 有权
标题翻译：用于处理缓存一致性的自修改代码的方法和系统
公开(公告)号：US08015362B2
公开(公告)日：2011-09-06
申请号：US12031923
申请日：2008-02-15
申请人： Gregory W. Alexander , Christian Jacobi , Barry W. Krumm , Chung-Lung Kevin Shum , Aaron Tsai
发明人： Gregory W. Alexander , Christian Jacobi , Barry W. Krumm , Chung-Lung Kevin Shum , Aaron Tsai
IPC分类号： G06F12/00
CPC分类号： G06F12/0848 , G06F9/3812
摘要： A method for handling cache coherency includes allocating a tag when a cache line is not exclusive in a data cache for a store operation, and sending the tag and an exclusive fetch for the line to coherency logic. An invalidation request is sent within a minimum amount of time to an I-cache, preferably only if it has fetched to the line and has not been invalidated since, which request includes an address to be invalidated, the tag, and an indicator specifying the line is for a PSC operation. The method further includes comparing the request address against stored addresses of prefetched instructions, and in response to a match, sending a match indicator and the tag to an LSU, within a maximum amount of time. The match indicator is timed, relative to exclusive data return, such that the LSU can discard prefetched instructions following execution of the store operation that stores to a line subject to an exclusive data return, and for which the match is indicated.
摘要翻译：一种用于处理高速缓存一致性的方法包括当高速缓存行在存储操作的数据高速缓存中不排斥时分配标签，以及将该标签和该行的独占提取发送到一致性逻辑。无效请求在最小时间内被发送到I缓存，优选地只有当它已经被取出到该行并且没有被无效时，因为哪个请求包括要被无效的地址，该标签和一个指示线路用于PSC操作。该方法还包括将请求地址与预取指令的存储地址进行比较，并且响应于匹配，在最大时间量内向LSU发送匹配指示符和标签。匹配指示符相对于独占数据返回是定时的，使得LSU可以执行存储操作之后丢弃预取指令，存储到受独占数据返回的行，并且指示匹配。

30. 发明申请

US20110185158A1 HISTORY AND ALIGNMENT BASED CRACKING FOR STORE MULTIPLE INSTRUCTIONS FOR OPTIMIZING OPERAND STORE COMPARE PENALTIES 有权
标题翻译：用于存储多项指令的历史和对齐基础打破优化操作存储比较罚款
公开(公告)号：US20110185158A1
公开(公告)日：2011-07-28
申请号：US12695687
申请日：2010-01-28
申请人： KHARY J. ALEXANDER , Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi , James R. Mitchell
发明人： KHARY J. ALEXANDER , Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi , James R. Mitchell
IPC分类号： G06F9/40
CPC分类号： G06F9/30043 , G06F9/3017 , G06F9/3824 , G06F9/3838
摘要： Store multiple instructions are managed based on previous execution history and their alignment. At least one store multiple instruction is detected. A flag is determined to be associated with the at least one store multiple instruction. The flag indicates that the at least one store multiple instruction has previously encountered an operand store compare hazard. The at least one store multiple instruction is organized into a set of unit of operations. The set of unit of operations is executed. The executing avoids the operand store compare hazard previously encountered by the at least one store multiple instruction.
摘要翻译：存储多个指令是根据以前的执行历史及其对齐方式进行管理的。检测到至少一个存储多重指令。确定标志与至少一个存储多重指令相关联。该标志指示至少一个存储多指令先前已经遇到操作数存储比较危险。将至少一个存储多个指令组织成一组操作单元。执行一组操作单元。该执行避免了由至少一个存储多个指令先前遇到的操作数存储比较危险。

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