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21. 发明申请

US20080144379A1 IMPLEMENTATION OF COLUMN REDUNDANCY FOR A FLASH MEMORY WITH A HIGH WRITE PARALLELISM 有权
标题翻译：实现具有高写并发性的闪存存储器的冗余冗余
公开(公告)号：US20080144379A1
公开(公告)日：2008-06-19
申请号：US11611452
申请日：2006-12-15
申请人： Simone Bartoli , Stefano Surico , Andrea Sacco , Maria Mostola
发明人： Simone Bartoli , Stefano Surico , Andrea Sacco , Maria Mostola
IPC分类号： G11C16/06
CPC分类号： G11C29/82 , G11C29/806 , G11C29/846
摘要： A redundant memory array has r columns of redundant memory cells, r redundant senses, and a redundant column decoder. Redundant address registers store addresses of defective regular memory cells. Redundant latches are provided in n groups of r latches. Redundancy comparison logic compares addresses of defective regular memory cells with an external input address. If the comparison is true, what is provided is: a DISABLE_LOAD signal to disable the regular senses for one of the n groups of m columns, an ENABLE_LATCH signal to one of the n groups of m columns to disables corresponding regular senses, and one or r REDO signals to a respective one of the r redundant latches in one of the n groups that is disabled. The selected one of the redundant latches activates one of the r redundant senses to access a redundant column.
摘要翻译：冗余存储器阵列具有r列的冗余存储器单元，r冗余感测器和冗余列解码器。冗余地址寄存器存储有缺陷的常规存储单元的地址。在n组r个锁存器中提供冗余锁存器。冗余比较逻辑将缺陷常规存储单元的地址与外部输入地址进行比较。如果比较是真的，提供的是：DISABLE_LOAD信号，用于禁用n列m列中的一个的常规感测，将一个ENABLE_LATCH信号分配给m列的n组中的一组，以禁用相应的常规感官，以及其中之一 r REDO信号到禁用的n个组之一的r个冗余锁存器中的相应一个。所选的一个冗余锁存器激活r个冗余感测之一以访问冗余列。

22. 发明授权

US07283396B2 System and method for matching resistance in a non-volatile memory 有权
标题翻译：用于在非易失性存储器中匹配电阻的系统和方法
公开(公告)号：US07283396B2
公开(公告)日：2007-10-16
申请号：US11193924
申请日：2005-07-28
申请人： Lorenzo Bedarida , Andrea Sacco , Giorgio Oddone , Simone Bartoli
发明人： Lorenzo Bedarida , Andrea Sacco , Giorgio Oddone , Simone Bartoli
IPC分类号： G11C16/06
CPC分类号： G11C16/26
摘要： A method and system for approximating resistance in a non-volatile memory has a memory matrix. The memory matrix has a plurality of memory cells and a plurality of memory source lines that are coupled to the plurality of memory cells. A reference matrix is coupled to the memory matrix and has a reference cell. A logic generator is coupled to the reference matrix and is configured to generate an approximation, at the reference cell, of a resistance between a selected one of the plurality of memory cells and at least one of the plurality of memory source lines.
摘要翻译：用于近似非易失性存储器中的电阻的方法和系统具有存储器矩阵。存储矩阵具有耦合到多个存储单元的多个存储器单元和多个存储器源极线。参考矩阵耦合到存储器矩阵并具有参考单元。逻辑发生器耦合到参考矩阵，并被配置为在参考单元处产生多个存储器单元中的所选择的一个与多个存储器源极线中的至少一个之间的电阻的近似。

23. 发明申请

US20070076476A1 Method and system for regulating a program voltage value during multilevel memory device programming 有权
标题翻译：用于在多级存储器件编程期间调节编程电压值的方法和系统
公开(公告)号：US20070076476A1
公开(公告)日：2007-04-05
申请号：US11635160
申请日：2006-12-07
申请人： Massimiliano Frulio , Simone Bartoli , Davide Manfre' , Andrea Sacco
发明人： Massimiliano Frulio , Simone Bartoli , Davide Manfre' , Andrea Sacco
IPC分类号： G11C16/04
CPC分类号： G11C16/12 , G11C5/145 , G11C11/5628 , G11C16/04 , G11C16/30 , G11C16/3459 , G11C29/02 , G11C29/021 , G11C29/028
摘要： Regulating a program voltage value during multilevel memory device programming includes utilizing a program path duplicate in an output pump regulator circuit. Further, the output pump regulator circuit is utilized to provide a regulated program voltage for memory cell programming, the regulated program voltage correcting for a program path voltage drop.
摘要翻译：在多级存储器件编程期间调节编程电压值包括在输出泵调节器电路中使用程序路径副本。此外，输出泵调节器电路用于为存储器单元编程提供调节的编程电压，用于编程路径电压降的调节的编程电压。

24. 发明申请

US20070047325A1 Method and apparatus for discharging a memory cell in a memory device after an erase operation 有权
标题翻译：在擦除操作之后，用于在存储器件中放电存储单元的方法和装置
公开(公告)号：US20070047325A1
公开(公告)日：2007-03-01
申请号：US11583625
申请日：2006-10-18
申请人： Lorenzo Bedarida , Simone Bartoli , Giorgio Oddone , Davide Manfre
发明人： Lorenzo Bedarida , Simone Bartoli , Giorgio Oddone , Davide Manfre
IPC分类号： G11C16/06
CPC分类号： G11C16/12 , G11C16/10 , G11C16/22
摘要： A method and apparatus for discharging a memory cell in a memory device. In one implementation, the memory cell includes a capacitor having a first plate and a second plate, and the method includes initially discharging the first plate of the capacitor through a first discharge circuit and discharging the second plate of the capacitor through a second discharge circuit. After the initial discharge, the method further includes completely discharging the first plate of the capacitor and the second plate of the capacitor by coupling both the first plate of the capacitor and the second plate of the capacitor to ground.
摘要翻译：一种用于对存储器件中的存储单元进行放电的方法和装置。在一个实施方式中，存储单元包括具有第一板和第二板的电容器，并且该方法包括首先通过第一放电电路对电容器的第一板进行放电，并通过第二放电电路对电容器的第二板进行放电。在初始放电之后，该方法还包括通过将电容器的第一板和电容器的第二板耦合到地将电容器的第一板和电容器的第二板完全放电。

25. 发明授权

US07184311B2 Method and system for regulating a program voltage value during multilevel memory device programming 有权
标题翻译：用于在多级存储器件编程期间调节编程电压值的方法和系统
公开(公告)号：US07184311B2
公开(公告)日：2007-02-27
申请号：US11123754
申请日：2005-05-05
申请人： Massimiliano Frulio , Simone Bartoli , Davide Manfre′ , Andrea Sacco
发明人： Massimiliano Frulio , Simone Bartoli , Davide Manfre′ , Andrea Sacco
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C11/5628 , G11C7/04 , G11C16/04 , G11C16/12 , G11C16/30 , G11C29/021 , G11C29/028
摘要： Regulating a program voltage value during multilevel memory device programming includes utilizing a program path duplicate in an output pump regulator circuit. Further, the output pump regulator circuit is utilized to provide a regulated program voltage for memory cell programming, the regulated program voltage correcting for a program path voltage drop and compensating for temperature variation.
摘要翻译：在多级存储器件编程期间调节编程电压值包括在输出泵调节器电路中使用程序路径副本。此外，输出泵调节器电路用于提供用于存储器单元编程的调节编程电压，用于编程路径电压降的校准编程电压并补偿温度变化。

26. 发明申请

US20060077714A1 Method and system for a programming approach for a nonvolatile electronic device 有权
标题翻译：用于非易失性电子设备的编程方法的方法和系统
公开(公告)号：US20060077714A1
公开(公告)日：2006-04-13
申请号：US11128939
申请日：2005-05-12
申请人： Stefano Surico , Simone Bartoli , Fabio Tassan Caser , Monica Marziani
发明人： Stefano Surico , Simone Bartoli , Fabio Tassan Caser , Monica Marziani
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C16/3468 , G11C16/3481 , G11C2211/5621 , G11C2211/5634
摘要： Aspects for programming a nonvolatile electronic device include performing an initial verify step of a programming algorithm with an initial type of reference voltage value, and performing one or more subsequent verify steps in the programming algorithm with a second type of reference voltage value. Further included is utilizing a read reference voltage for the initial verify step, wherein desired programming is ensured for a cell that falls out of ideal distribution.
摘要翻译：用于编程非易失性电子设备的方面包括使用初始类型的参考电压值执行编程算法的初始验证步骤，以及使用第二类型的参考电压值来执行编程算法中的一个或多个后续验证步骤。进一步包括利用读取参考电压进行初始验证步骤，其中为理想分布的单元确保期望的编程。

27. 发明授权

US06401164B1 Sectored semiconductor memory device with configurable memory sector addresses 有权
标题翻译：具有可配置存储器扇区地址的扇区半导体存储器件
公开(公告)号：US06401164B1
公开(公告)日：2002-06-04
申请号：US09159322
申请日：1998-09-23
申请人： Simone Bartoli , Vincenzo Dima , Mauro Luigi Sali
发明人： Simone Bartoli , Vincenzo Dima , Mauro Luigi Sali
IPC分类号： G06F1206
CPC分类号： G11C8/12 , G11C16/08
摘要： A memory device comprises a plurality of independent memory sectors, external address signal inputs for receiving external address signals that address individual memory locations of the memory device, the external address signals including external memory sector address signals allowing for individually addressing each memory sector, and a memory sector selection circuit for selecting one of the plurality of memory sectors according to a value of the external memory sector address signals. A first and a second alternative internal memory sector address signal paths are provided for supplying the external memory sector address signals to the memory sector selection circuit, the first path providing no logic inversion and the second path providing logic inversion. A programmable circuit activates either one or the other of the first and second internal memory sector address signal paths, so that a position of each memory sector in a space of values (00000h-3FFFFh) of the external address signals can be changed by activating either one or the other of the first and second internal memory sector address signal paths.
摘要翻译：存储器件包括多个独立存储器扇区，外部地址信号输入用于接收寻址存储器件的各个存储器位置的外部地址信号，外部地址信号包括允许单独寻址每个存储器扇区的外部存储器扇区地址信号，以及存储器扇区选择电路，用于根据外部存储器扇区地址信号的值来选择多个存储器扇区之一。提供第一和第二替代的内部存储器扇区地址信号路径用于将外部存储器扇区地址信号提供给存储器扇区选择电路，第一路径不提供逻辑反转，而第二路径提供逻辑反转。可编程电路激活第一和第二内部存储器扇区地址信号路径中的一个或另一个，使得外部地址信号的值（00000h-3FFFFh）的空间中的每个存储器扇区的位置可以通过激活第一和第二内部存储器扇区地址信号路径中的一个或另一个。

28. 发明授权

US5822247A Device for generating and regulating a gate voltage in a non-volatile memory 失效
标题翻译：用于产生和调节非易失性存储器中的栅极电压的装置
公开(公告)号：US5822247A
公开(公告)日：1998-10-13
申请号：US775111
申请日：1996-12-30
申请人： Fabio Tassan Caser , Corrado Villa , Simone Bartoli
发明人： Fabio Tassan Caser , Corrado Villa , Simone Bartoli
IPC分类号： G11C5/14 , G11C8/08 , G11C16/16 , G11C16/30 , G11C16/34 , G11C16/04
CPC分类号： G11C16/3427 , G11C16/16 , G11C16/30 , G11C16/3418 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C5/147 , G11C8/08
摘要： The present invention relates to a device for generating and regulating a gate voltage in an electrically programmable non-volatile memory with single power supply of the type comprising a voltage booster driven by a clock signal applied to a first input terminal thereof and having an output terminal on which is produced a signal with higher voltage. This device comprises a lower regulator block and a programming switching block inserted in parallel each other between said output terminal of the voltage booster and an output terminal of the gate voltage generating and regulating device with said lower regulator block being driven by a plurality of switching signals to supply on the output terminal of the device a plurality of regulated voltages and feed the control gates of the non-volatile memory cells.
摘要翻译：本发明涉及一种用于在电可编程非易失性存储器中产生和调节栅极电压的装置，该单电源包括由施加到其第一输入端的时钟信号驱动的升压驱动器，并具有输出端在其上产生具有较高电压的信号。该装置包括在升压器的所述输出端子和栅极电压产生和调节装置的输出端子之间并联插入的下调节器块和编程切换块，所述下调节器块由多个开关信号驱动在装置的输出端子上提供多个调节电压并馈送非易失性存储单元的控制栅极。

29. 发明授权

US08644079B2 Method and circuit to discharge bit lines after an erase pulse 有权
标题翻译：擦除脉冲后放电位线的方法和电路
公开(公告)号：US08644079B2
公开(公告)日：2014-02-04
申请号：US13104722
申请日：2011-05-10
申请人： Marco Passerini , Simone Bartoli , Osama Khouri
发明人： Marco Passerini , Simone Bartoli , Osama Khouri
IPC分类号： G11C11/4063
CPC分类号： G11C16/06 , G11C16/14 , G11C16/3418
摘要： Disclosed here in a method that comprises performing an erase operation on multiple cells in a memory device, the performing comprising applying an erase voltage to the multiple cells, bit lines coupled to the multiple cells being thereby charged up; and discharging the bit lines by coupling the bit lines to a discharging line through a DC path.
摘要翻译：这里公开了一种方法，其包括对存储器件中的多个单元执行擦除操作，所述执行包括向所述多个单元施加擦除电压，从而将耦合到所述多个单元的位线充电; 以及通过将位线通过DC路径耦合到放电线来对位线进行放电。

30. 发明授权

US07920436B2 Sense amplifier 有权
标题翻译：感应放大器
公开(公告)号：US07920436B2
公开(公告)日：2011-04-05
申请号：US12336965
申请日：2008-12-17
申请人： Lorenzo Bedarida , Simone Bartoli , Davide Manfre , Alex Pojer
发明人： Lorenzo Bedarida , Simone Bartoli , Davide Manfre , Alex Pojer
IPC分类号： G11C7/00
CPC分类号： G11C7/062
摘要： A sense amplifier includes a first cascode transistor, a second cascode transistor, a first feedback circuit, a second feedback circuit, and a comparator. The drain of the first cascode transistor is connected directly to a first voltage source. The gate of the first cascode transistor is connected to the first feedback circuit and a first input of the comparator, and the source of the first cascode transistor is connected to the first feedback circuit and a first column decoder. The drain of the second cascode transistor is connected directly to a second voltage source. The gate of the second cascode transistor is connected to the second feedback circuit and a second input of the comparator, and the source of the second cascode transistor is connected to the second feedback circuit and a second column decoder.
摘要翻译：读出放大器包括第一共源共栅晶体管，第二共源共栅晶体管，第一反馈电路，第二反馈电路和比较器。第一共源共栅晶体管的漏极直接连接到第一电压源。第一共源共栅晶体管的栅极连接到第一反馈电路和比较器的第一输入端，并且第一共源共栅晶体管的源极连接到第一反馈电路和第一列解码器。第二共源共栅晶体管的漏极直接连接到第二电压源。第二共源共栅晶体管的栅极连接到第二反馈电路和比较器的第二输入端，第二共源共栅晶体管的源极连接到第二反馈电路和第二列解码器。

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