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21. 发明授权

US08429339B2 Storage device utilizing free pages in compressed blocks 失效
标题翻译：存储设备利用压缩块中的免费页面
公开(公告)号：US08429339B2
公开(公告)日：2013-04-23
申请号：US13052361
申请日：2011-03-21
申请人： Kohei Oikawa
发明人： Kohei Oikawa
IPC分类号： G06F12/04
CPC分类号： G06F12/0246 , G06F2212/401 , G06F2212/7201
摘要： According to one embodiment, a storage device comprises a first storage unit having blocks, each including pages, a second storage unit having a free block list, and a free page list, and a control unit. In write data in units of blocks, the control unit generates compressed data blocks by compressing the data in units of blocks, writes the compressed data blocks to the blocks which can be written in accordance with the information held in the free block list, holds, in the free page list, the information about pages existing in free areas which are provided in the blocks holding compressed data blocks and which holds no compressed data blocks. In write data in units of pages, the control unit writes the data in units of pages to pages existing in the free areas, in accordance with the information held in the free page list.
摘要翻译：根据一个实施例，存储设备包括具有块的第一存储单元，每个块包括页面，具有空闲块列表的第二存储单元和免费页面列表以及控制单元。在以块为单位的写入数据中，控制单元通过以块为单位压缩数据来生成压缩数据块，将压缩数据块写入可根据保存在自由块列表中的信息保存的块，在免费页面列表中，关于在保存压缩数据块的块中提供并且不保存压缩数据块的空闲区域中存在的页面的信息。在以页面为单位的写入数据中，控制单元根据保存在自由页面列表中的信息将页面中的数据写入存在于空闲区域中的页面。

22. 发明授权

US07127598B2 Semiconductor device comprising transition detecting circuit and method of activating the same 有权
标题翻译：包括转换检测电路的半导体器件及其激活方法
公开(公告)号：US07127598B2
公开(公告)日：2006-10-24
申请号：US10322587
申请日：2002-12-19
申请人： Kohei Oikawa , Shinichiro Shiratake , Yoshiaki Takeuchi , Daisaburo Takashima , Thomas Roehr
发明人： Kohei Oikawa , Shinichiro Shiratake , Yoshiaki Takeuchi , Daisaburo Takashima , Thomas Roehr
IPC分类号： G06F15/177
CPC分类号： G06F1/24
摘要： A semiconductor device includes an internal power supply, at least one semiconductor circuit block, a delay circuit, and a detecting circuit. The internal power supply outputs an initialization completion signal when initialized. The semiconductor circuit block operates on the basis of a voltage generated by the internal power supply. The delay circuit delays the initialization completion signal. The detecting circuit commands the semiconductor circuit block to start operations in response to the initialization completion signal delayed by the delay circuit and an externally input first input signal.
摘要翻译：半导体器件包括内部电源，至少一个半导体电路块，延迟电路和检测电路。初始化时，内部电源输出初始化完成信号。半导体电路块基于由内部电源产生的电压进行工作。延迟电路延迟初始化完成信号。检测电路响应于由延迟电路延迟的初始化完成信号和外部输入的第一输入信号，命令半导体电路块开始操作。

23. 发明申请

US20060181339A1 Semiconductor device with resistor element 审中-公开
公开(公告)号：US20060181339A1
公开(公告)日：2006-08-17
申请号：US11401303
申请日：2006-04-11
申请人： Shinichiro Shiratake , Kohei Oikawa
发明人： Shinichiro Shiratake , Kohei Oikawa
IPC分类号： G05F1/10
CPC分类号： G05F1/565 , H01L29/8605
摘要： A semiconductor device includes first, second, third and fourth resistor elements. The first to fourth resistor elements have first ends commonly connected to a first node, and operate in one of first and second operation modes which are switchable. The first and second resistor elements have second ends connected to a second node and a third node, respectively. The third and fourth resistor elements have second ends connected to a fourth node and a fifth node via a first switch and a second switch, respectively. The first and second switches are opened in the first operation mode, and are closed in the second operation mode.

24. 发明申请

US20060020836A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20060020836A1
公开(公告)日：2006-01-26
申请号：US10934462
申请日：2004-09-07
申请人： Kohei Oikawa
发明人： Kohei Oikawa
IPC分类号： G06F1/26
CPC分类号： G06F1/10 , G06F1/12 , G06F1/26
摘要： A circuit according to an embodiment of the present invention comprises a first power supply region supplied with a first power supply voltage, and having a first clock distribution network, a second power supply region supplied with a second power supply voltage, and having a second clock distribution network, a PLL circuit which provides a first output signal obtained by making a phase of a reference clock signal for controlling a data input/output coincident with a phase of a clock signal at an end point of the first clock distribution network, to a start point of the first clock distribution network, and a PLL circuit which provides a second output signal obtained by making the phase of the reference clock signal coincident with a phase of a clock signal at an end point of the second clock distribution network, to a start point of the second clock distribution network.
摘要翻译：根据本发明实施例的电路包括提供有第一电源电压的第一电源区域，并具有第一时钟分配网络，提供有第二电源电压的第二电源区域，以及具有第二时钟分配网络，PLL电路，其提供通过使用用于控制与第一时钟分配网络的端点处的时钟信号的相位一致的数据输入/输出的参考时钟信号的相位获得的第一输出信号，第一时钟分配网络的起始点和PLL电路，其提供通过使参考时钟信号的相位与第二时钟分配网络的端点处的时钟信号的相位一致而获得的第二输出信号，第二个时钟分配网络的起点。

25. 发明授权

US06765831B2 Semiconductor integrated circuit device 失效
公开(公告)号：US06765831B2
公开(公告)日：2004-07-20
申请号：US10428763
申请日：2003-05-05
申请人： Kohei Oikawa , Shinichiro Shiratake , Daisaburo Takashima
发明人： Kohei Oikawa , Shinichiro Shiratake , Daisaburo Takashima
IPC分类号： G11C800
CPC分类号： G11C11/22
摘要： A semiconductor integrated circuit device includes a memory array, address buffer, address decoder, and controller. The memory array includes a memory cell array in which destructive read-out memory cells are integrated. The address buffer outputs an internal address signal corresponding to an input external address signal. The address decoder decodes the internal address signal and outputs a memory cell selection signal on the basis of the decode result. The controller parallel-executes wait processing of keeping the address buffer in a wait state until the lapse of a skew time after transition of the external address signal is detected, and decode processing until the memory cell selection signal changes from an invalid state to a valid state in response to output of the internal address signal.

26. 发明授权

US06744305B2 Power supply circuit having value of output voltage adjusted 有权
标题翻译：电源电路的输出电压值调整
公开(公告)号：US06744305B2
公开(公告)日：2004-06-01
申请号：US10233529
申请日：2002-09-04
申请人： Kohei Oikawa , Shinichiro Shiratake
发明人： Kohei Oikawa , Shinichiro Shiratake
IPC分类号： G05F146
CPC分类号： G05F1/56
摘要： A power supply circuit includes a transistor, a variable resistance circuit, a second resistance, and an operational amplifier. The variable resistance circuit includes a plurality of first resistances. The plurality of first resistances are selected in response to control signals. The selected first resistances are connected in series with the transistor, the unselected first resistances are connected to a ground voltage. The second resistance is connected between the variable resistance circuit and the ground voltage. The operational amplifier compares a voltage of the one end of the variable resistance circuit with a reference voltage and feeds a signal indicating a comparison result back to the gate of the transistor.
摘要翻译：电源电路包括晶体管，可变电阻电路，第二电阻和运算放大器。可变电阻电路包括多个第一电阻。响应于控制信号选择多个第一电阻。所选择的第一电阻与晶体管串联连接，未选择的第一电阻连接到接地电压。第二电阻连接在可变电阻电路和接地电压之间。运算放大器将可变电阻电路的一端的电压与参考电压进行比较，并将表示比较结果的信号反馈回晶体管的栅极。

27. 发明授权

US06744302B2 Voltage generator circuit for use in a semiconductor device 有权
标题翻译：用于半导体器件的电压发生器电路
公开(公告)号：US06744302B2
公开(公告)日：2004-06-01
申请号：US10310053
申请日：2002-12-05
申请人： Kohei Oikawa , Shinichiro Shiratake , Daisaburo Takashima
发明人： Kohei Oikawa , Shinichiro Shiratake , Daisaburo Takashima
IPC分类号： G05F110
CPC分类号： G05F3/24
摘要： A voltage generator circuit generates a voltage supplied to an internal circuit. The voltage generator circuit includes first, second, and third switching elements each having first and second terminals. The first terminal of each of the switching elements is connected to the power source terminal supplied with a power source voltage. First, second, and third transistors each have a current path which has first and second ends. The first ends of the first, second, and third transistors are respectively connected to the second terminals of the first, second, and third switching elements. The first, second, and third transistors have respectively first, second, and third driving capabilities. The first, second, and third driving capabilities are different from each other. The second ends of the current paths of the first, second, and third transistors are connected to an output terminal which outputs the voltage supplied to the internal circuit.
摘要翻译：电压发生器电路产生提供给内部电路的电压。电压发生器电路包括具有第一和第二端子的第一，第二和第三开关元件。每个开关元件的第一端子连接到被提供有电源电压的电源端子。第一，第二和第三晶体管各自具有第一和第二端的电流路径。第一，第二和第三晶体管的第一端分别连接到第一，第二和第三开关元件的第二端子。第一，第二和第三晶体管分别具有第一，第二和第三驱动能力。第一，第二和第三驾驶能力彼此不同。第一，第二和第三晶体管的电流路径的第二端连接到输出提供给内部电路的电压的输出端子。

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