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21. 发明申请

US20050186782A1 Dual damascene interconnect structure with improved electro migration lifetimes 有权
标题翻译：双镶嵌互连结构，具有改善的电迁移寿命
公开(公告)号：US20050186782A1
公开(公告)日：2005-08-25
申请号：US11090107
申请日：2005-03-24
申请人： Peter Burke , William Barth , Hongqiang Lu
发明人： Peter Burke , William Barth , Hongqiang Lu
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/768 , H01L23/522
CPC分类号： H01L21/76808 , H01L21/76813 , H01L21/76838 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A dual damascene interconnect structure is formed by patterning a first dielectric to form a metal line. A second dielectric is disposed on the first dielectric and patterned to form a via. The first metal line is patterned in a configuration relative to a via landing so that a cavity is formed when the via etch into the second dielectric is extended into the first dielectric. The cavity is filled with a conductive metal in an integral manner with the formation of the via to form a via projection for improved electrical contact between the via and the metal line.
摘要翻译：通过图案化第一电介质以形成金属线来形成双镶嵌互连结构。第二电介质设置在第一电介质上并被图案化以形成通孔。第一金属线以相对于通孔接合的结构进行图案化，使得当将进入第二电介质的通孔蚀刻延伸到第一电介质中时形成空腔。在形成通孔的情况下，以一体的方式填充导电金属以形成通孔突起，以改善通孔和金属线之间的电接触。

22. 发明申请

US20050176216A1 Ultra low dielectric constant thin film 审中-公开
公开(公告)号：US20050176216A1
公开(公告)日：2005-08-11
申请号：US11106307
申请日：2005-04-14
申请人： Hao Cui , Peter Burke , Wilbur Catabay
发明人： Hao Cui , Peter Burke , Wilbur Catabay
IPC分类号： C23C16/32 , H01L21/00 , H01L21/314 , H01L21/46 , H01L21/768 , H01L29/15
CPC分类号： H01L21/02167 , C23C16/325 , H01L21/022 , H01L21/02274 , H01L21/3148 , H01L21/76801 , H01L21/76807 , H01L21/76826 , H01L21/76828
摘要： A method for forming a substantially oxygen-free silicon carbide layer on a substrate, where the silicon carbide layer has a dielectric constant of less than about four. The substrate is held at a deposition temperature of between about zero centigrade and about one hundred centigrade, and a gas flow of tetramethylsilane is introduced at a rate of no more than about one thousand scientific cubic centimeters per minute. The deposition pressure is held between about one milli Torr and about one hundred Torr, and a radio frequency plasma discharge is produced with a power of no more than about two kilowatts. The plasma discharge is halted when a desired thickness of the silicon carbide layer has been formed.

23. 发明授权

US08961759B2 Device and method for mitochondrial membrane potential assessment 有权
标题翻译：线粒体膜电位评估装置及方法
公开(公告)号：US08961759B2
公开(公告)日：2015-02-24
申请号：US13412515
申请日：2012-03-05
申请人： Peter Burke , Tae-Sun Lim , Antonio Davila , Douglas C. Wallace , Katayoun Zand
发明人： Peter Burke , Tae-Sun Lim , Antonio Davila , Douglas C. Wallace , Katayoun Zand
IPC分类号： G01N27/414 , G01N27/403 , G01N33/483
CPC分类号： G01N27/4035 , G01N33/4833 , Y10S435/82
摘要： A microfluidic sensor device includes a substrate having patterned thereon at least one Ag/AgCl electrode (working electrode) and an inner chamber overlying the at least one Ag/AgCl electrode. The device includes an ion selective permeable membrane permeable to TPP+ disposed on one side of the first chamber and a sensing chamber overlying the ion selective permeable membrane. A separate reference electrode is inserted into the sensing chamber. The working electrode and reference electrode are coupled to a voltmeter to measure voltage. This voltage can then be translated into a TPP+ concentration which is used to determine the mitochondrial membrane potential (ΔΨm).
摘要翻译：微流体传感器装置包括其上具有图案化的至少一个Ag / AgCl电极（工作电极）和覆盖至少一个Ag / AgCl电极的内室的基板。该装置包括设置在第一室的一侧上的可渗透TPP +的离子选择性渗透膜和覆盖离子选择性渗透膜的感测室。单独的参考电极插入感测室。工作电极和参考电极耦合到电压表以测量电压。然后可以将该电压转化为用于确定线粒体膜电位（＆Dgr;Ψm）的TPP +浓度。

24. 发明申请

US20080159270A1 INTEGRATED PHASE LOCK LOOP AND NETWORK PHY OR SWITCH 审中-公开
标题翻译：集成相位锁定环路和网络物理层或开关
公开(公告)号：US20080159270A1
公开(公告)日：2008-07-03
申请号：US11962390
申请日：2007-12-21
申请人： Peter Burke , Louise Gaulin , Silvana Goncala Rodrigues , Daniel Norman Gallant , Maamoun Abou Seido
发明人： Peter Burke , Louise Gaulin , Silvana Goncala Rodrigues , Daniel Norman Gallant , Maamoun Abou Seido
IPC分类号： H04L12/66
CPC分类号： H04J3/0697 , H04J3/0644 , H04J3/0688
摘要： A node in for connection to a synchronous packet network includes a packet switch and a physical interface for connection to the packet network. A phase locked loop arrangement for synchronization is integrated into the physical interface, the packet switch or both.
摘要翻译：用于连接到同步分组网络的节点包括分组交换机和用于连接到分组网络的物理接口。用于同步的锁相环装置被集成到物理接口，分组交换机或两者中。

25. 发明申请

US20070190784A1 DIELECTRIC BARRIER LAYER FOR INCREASING ELECTROMIGRATION LIFETIMES IN COPPER INTERCONNECT STRUCTURES 失效
标题翻译：用于增加铜互连结构中电磁寿命的电介质障碍层
公开(公告)号：US20070190784A1
公开(公告)日：2007-08-16
申请号：US11736402
申请日：2007-04-17
申请人： Hao Cui , Peter Burke , Wilbur Catabay
发明人： Hao Cui , Peter Burke , Wilbur Catabay
IPC分类号： H01L21/44
CPC分类号： H01L21/76832 , H01L21/76825 , H01L21/76826 , H01L21/76834 , H01L21/76883
摘要： Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack.
摘要翻译：本发明的实施例包括具有增加的电迁移寿命的铜互连结构。这种结构可以包括其上形成有铜层的半导体衬底。在铜层上形成介电阻挡层叠体。电介质势垒叠层包括邻近铜层形成的第一部分和形成在第一部分上的第二部分，第一部分具有相对于第二部分具有改进的铜的粘合性，并且两个部分形成为具有耐铜扩散性。本发明还包括用于构造这种结构的几个实施例。可以通过等离子体处理或离子注入电介质阻挡层的选定部分与粘合增强材料来增加电介质阻挡层与铜的附着，以增加堆叠中这种材料的浓度。

26. 发明申请

US20060169287A1 Condom with male genital desensitizer lubricant 审中-公开
公开(公告)号：US20060169287A1
公开(公告)日：2006-08-03
申请号：US11396649
申请日：2006-04-04
申请人： Michael Harrison , Dennis Blum , Gisela McBride , Stephen Coulter , Peter Burke
发明人： Michael Harrison , Dennis Blum , Gisela McBride , Stephen Coulter , Peter Burke
IPC分类号： A61F6/02 , A61F6/04
CPC分类号： A61F6/04 , A61F2006/048 , A61K9/0034 , Y10S128/918
摘要： A condom having a first lubricating composition containing a male genitalia desensitizing agent on the inside surface thereof and a second lubricating composition on the outside surface thereof. The first lubricating composition has a higher viscosity than the second lubricating composition so that the first lubricating composition remains on the inside surface of the condom during packaging, shipping, storage, and use.

27. 发明申请

US20060035457A1 Interconnection capacitance reduction 审中-公开
标题翻译：互连电容降低
公开(公告)号：US20060035457A1
公开(公告)日：2006-02-16
申请号：US10915166
申请日：2004-08-10
申请人： Richard Carter , Peter Burke , Wilbur Catabay , Zhihai Wang , Wei-Jen Hsia
发明人： Richard Carter , Peter Burke , Wilbur Catabay , Zhihai Wang , Wei-Jen Hsia
IPC分类号： H01L21/4763
CPC分类号： H01L21/76885 , H01L21/7682 , H01L21/76834 , H01L21/76837
摘要： An improvement to a method of fabricating an integrated circuit. All dielectric material that is laterally surrounding an electrically conductive interconnect is removed, while leaving the dielectric material that directly underlies the electrically conductive interconnect. The electrically conductive interconnect is back filled with a low k material, where the low k material provides low capacitance between laterally adjacent electrically conductive interconnects, and the remaining dielectric material underlying the electrically conductive interconnects provides structural support to the electrically conductive interconnects.
摘要翻译：对集成电路的制造方法的改进。移除横向围绕导电互连的所有电介质材料，同时留下直接位于导电互连之下的电介质材料。导电互连件用低k材料填充，其中低k材料在横向相邻的导电互连之间提供低电容，并且导电互连件下面的剩余电介质材料为导电互连提供结构支撑。

28. 发明申请

US20050181615A1 Integrated circuit process monitoring and metrology system 有权
公开(公告)号：US20050181615A1
公开(公告)日：2005-08-18
申请号：US11072127
申请日：2005-03-04
申请人： Peter Burke , Eric Kirchner , James Elmer
发明人： Peter Burke , Eric Kirchner , James Elmer
IPC分类号： H01L21/302 , H01L21/3105 , H01L21/66 , H01L21/76 , H01L23/544
CPC分类号： H01L22/34 , H01L21/31053
摘要： A method for monitoring polishing process parameters for an integrated circuit structure on a substrate. A first metrology site is constructed on the substrate. The first metrology site represents a design extreme of a high density integrated circuit structure. The first metrology site is formed by placing a relatively small horizontal surface area trench within a relatively large surface area field of a polish stop material. A second metrology site is also constructed on the substrate. The second metrology site represents a design extreme of a low density integrated circuit structure. The second metrology site is formed by placing a relatively large horizontal surface area trench within a relatively small surface area field of a polish stop material. The substrate is covered with a layer of an insulating material, thereby at least filling the trenches. A target thickness of the insulating material necessary to leave the trenches substantially filled to a top surface of the field of polish stop material is calculated. The substrate is polished until a first thickness of the insulating material in the trench of the first metrology site is no more than the target thickness. A second thickness of the insulating material in the trench of the second metrology site is measured, and values based on the first thickness and the second thickness are monitored as the polishing process parameters for the integrated circuit structure.

29. 发明申请

US20050084415A1 High capacity flash vapor generation systems 审中-公开
标题翻译：大容量闪蒸产生系统
公开(公告)号：US20050084415A1
公开(公告)日：2005-04-21
申请号：US10940495
申请日：2004-09-14
申请人： Iain McVey , Francis Zelina , Aaron Hill , Peter Burke , Thaddeus Mielnik , Matthew Lawes , Gerald McDonnell , Kevin Williams
发明人： Iain McVey , Francis Zelina , Aaron Hill , Peter Burke , Thaddeus Mielnik , Matthew Lawes , Gerald McDonnell , Kevin Williams
IPC分类号： A61L2/18 , A61L2/20 , B65B55/02 , B65B55/10 , B67C7/00
CPC分类号： A61L2/208 , A61L2/186 , A61L9/015 , A61L2202/122 , A61L2202/23 , A61L2202/25 , B65B55/025 , B65B55/10 , B67C7/0073
摘要： A flash vaporizer (34) provides a constant flow of vaporized hydrogen peroxide or other antimicrobial compounds for rapidly sterilizing large enclosures (10), such as rooms or buildings. The vaporizer includes a heated block (50) which defines an interior bore or bores (70, 72, 74). The flowpath created by the bore or bores increases in cross sectional area as the hydrogen peroxide passes through the block to accommodate the increase in volume during the conversion from liquid to gas. The vapor is injected into dry air in a duct that circulates it to the large enclosure.
摘要翻译：闪蒸器（34）提供恒定的蒸发过氧化氢或其它抗微生物化合物的流动，用于快速消毒诸如房间或建筑物的大型封闭物（10）。蒸发器包括限定内孔或孔（70,72,74）的加热块（50）。由于孔或孔产生的流路的横截面积随着过氧化氢通过块而增加，以适应在从液体转化为气体期间的体积增加。将蒸汽注入到将其循环到大外壳的管道中的干燥空气中。

30. 发明申请

US20050020082A1 Polishing pads for chemical mechanical planarization 审中-公开
公开(公告)号：US20050020082A1
公开(公告)日：2005-01-27
申请号：US10922715
申请日：2004-08-20
申请人： Arun Vishwanathan , David James , Lee Cook , Peter Burke , David Shidner
发明人： Arun Vishwanathan , David James , Lee Cook , Peter Burke , David Shidner
IPC分类号： B24B37/04 , B24D3/28 , B24D13/14 , B24B49/00 , B24B51/00 , H01L21/302 , H01L21/461
CPC分类号： B24B37/26 , B24B37/042 , B24D3/28
摘要： An improved pad and process for polishing metal damascene structures on a semiconductor wafer. The process includes the steps of pressing the wafer against the surface of a polymer sheet in combination with an aqueous-based liquid that optionally contains sub-micron particles and providing a means for relative motion of wafer and polishing pad under pressure so that the moving pressurized contact results in planar removal of the surface of said wafer, wherein the polishing pad has a low elastic recovery when said load is removed, so that the mechanical response of the sheet is largely anelastic. The improved pad is characterized by a high energy dissipation coupled with a high pad stiffness. The pad exhibits a stable morphology that can be reproduced easily and consistently. The pad surface resists glazing, thereby requiring less frequent and less aggressive conditioning. The benefits of such a polishing pad are low dishing of metal features, low oxide erosion, reduced pad conditioning, longer pad life, high metal removal rates, good planarization, and lower defectivity (scratches and Light Point Defects).

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