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21. 发明申请

US20120224415A1 TRANSISTOR WITH REDUCED CHARGE CARRIER MOBILITY AND ASSOCIATED METHODS 有权
标题翻译：具有减少充电载波移动性和相关方法的晶体管
公开(公告)号：US20120224415A1
公开(公告)日：2012-09-06
申请号：US13472514
申请日：2012-05-16
申请人： Jörg Berthold , Christian Pacha , Klaus von Arnim
发明人： Jörg Berthold , Christian Pacha , Klaus von Arnim
IPC分类号： G11C11/412 , H01L21/265
CPC分类号： G11C11/412 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1211 , H01L29/04 , H01L29/785
摘要： One or more embodiments of the invention relate to a method comprising: treating a fin of a first n-channel access transistor in a static random access memory cell to have a lower charge carrier mobility than a fin of a first n-channel pull-down transistor in a first inverter in the memory cell, the first n-channel access transistor being coupled between a first bit line and a first node of the first inverter; and treating a fin of a second n-channel access transistor in the memory cell to have a lower charge carrier mobility than a fin of a second n-channel pull-down transistor in a second inverter in the memory cell, the second n-channel access transistor being coupled between a second bit line and a second node of the second inverter.
摘要翻译：本发明的一个或多个实施例涉及一种方法，包括：处理静态随机存取存储器单元中的第一n沟道存取晶体管的鳍以具有比第一n沟道下拉的鳍更低的载流子迁移率晶体管在存储单元中的第一反相器中，第一n沟道存取晶体管耦合在第一反相器的第一位线和第一节点之间; 以及处理所述存储单元中的第二n沟道存取晶体管的鳍以具有比所述存储单元中的第二反相器中的第二n沟道下拉晶体管的鳍更低的电荷载流子迁移率，所述第二n沟道存取晶体管耦合在第二反相器的第二位线和第二节点之间。

22. 发明申请

US20120061777A1 INTEGRALLY FABRICATED MICROMACHINE AND LOGIC ELEMENTS 有权
标题翻译：整体织造的MICROMACHINE和逻辑元素
公开(公告)号：US20120061777A1
公开(公告)日：2012-03-15
申请号：US13218987
申请日：2011-08-26
申请人： Stefan Kolb , Reinhard Mahnkopf , Christian Pacha , Bernhard Winkler , Werner Weber
发明人： Stefan Kolb , Reinhard Mahnkopf , Christian Pacha , Bernhard Winkler , Werner Weber
IPC分类号： H01L29/84 , H01L21/66 , H01L21/00
CPC分类号： G01P15/08 , G01C19/56 , G01P15/097 , G01P15/125 , H01L28/40 , H01L29/785
摘要： Embodiments relate to micromachine structures. In one embodiment, a micromachine structure includes a first electrode, a second electrode, and a sensing element. The sensing element is mechanically movable and is disposed intermediate the first and second electrodes and adapted to oscillate between the first and second electrodes. Further, the sensing element includes a FinFET structure having a height and a width, the height being greater than the width.
摘要翻译：实施例涉及微机械结构。在一个实施例中，微机械结构包括第一电极，第二电极和感测元件。感测元件是机械可移动的并且设置在第一和第二电极之间并且适于在第一和第二电极之间振荡。此外，感测元件包括具有高度和宽度的FinFET结构，高度大于宽度。

23. 发明授权

US08076738B2 Integrally fabricated micromachine and logic elements 有权
标题翻译：整体制造的微机械和逻辑元件
公开(公告)号：US08076738B2
公开(公告)日：2011-12-13
申请号：US11863297
申请日：2007-09-28
申请人： Stefan Kolb , Reinhard Mahnkopf , Christian Pacha , Bernhard Winkler , Werner Weber
发明人： Stefan Kolb , Reinhard Mahnkopf , Christian Pacha , Bernhard Winkler , Werner Weber
IPC分类号： H01L29/84
CPC分类号： G01P15/08 , G01C19/56 , G01P15/097 , G01P15/125 , H01L28/40 , H01L29/785
摘要： Embodiments of the invention are related to micromachine structures. In one embodiment, a micromachine structure comprises a first electrode, a second electrode, and a sensing element. The sensing element is mechanically movable and is disposed intermediate the first and second electrodes and adapted to oscillate between the first and second electrodes. Further, the sensing element comprises a FinFET structure having a height and a width, the height being greater than the width.
摘要翻译：本发明的实施例涉及微机械结构。在一个实施例中，微机械结构包括第一电极，第二电极和感测元件。感测元件是机械可移动的并且设置在第一和第二电极之间并且适于在第一和第二电极之间振荡。此外，感测元件包括具有高度和宽度的FinFET结构，高度大于宽度。

24. 发明授权

US08063448B2 Resistive memory and method 有权
标题翻译：电阻记忆和方法
公开(公告)号：US08063448B2
公开(公告)日：2011-11-22
申请号：US11687365
申请日：2007-03-16
申请人： Christian Pacha , Tim Schönauer , Michael Kund
发明人： Christian Pacha , Tim Schönauer , Michael Kund
IPC分类号： H01L27/11
CPC分类号： G11C13/0011 , G11C13/0004 , G11C13/0007 , G11C2213/32 , H01L27/2436 , H01L29/785 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1273 , H01L45/145
摘要： A memory device includes a multi gate field effect transistor (MuGFET) having a fin with a contact area. A programmable memory element abuts the fin contact area.
摘要翻译：存储器件包括具有接触区域的翅片的多栅极场效应晶体管（MuGFET）。可编程存储元件邻接鳍片接触区域。

25. 发明授权

US07888775B2 Vertical diode using silicon formed by selective epitaxial growth 有权
标题翻译：使用通过选择性外延生长形成的硅的垂直二极管
公开(公告)号：US07888775B2
公开(公告)日：2011-02-15
申请号：US11862964
申请日：2007-09-27
申请人： Christian Russ , Christian Pacha , Snezana Jenei , Klaus Schruefer
发明人： Christian Russ , Christian Pacha , Snezana Jenei , Klaus Schruefer
IPC分类号： H01L27/08
CPC分类号： H01L29/861 , H01L29/6609 , H01L29/66356 , H01L29/7391
摘要： Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus.
摘要翻译：一些实施例涉及在半导体本体和设置在半导体本体的掺杂区域上的外延膜之间出现垂直二极管活性的装置。一些实施例包括引起垂直和横向二极管活动的装置。一些实施例包括用于翅片半导体装置的门控垂直二极管。工艺实施例包括形成垂直二极管装置。

26. 发明授权

US07859421B2 Circuit and method for detecting a voltage change 有权
标题翻译：用于检测电压变化的电路和方法
公开(公告)号：US07859421B2
公开(公告)日：2010-12-28
申请号：US12361259
申请日：2009-01-28
申请人： Joerg Berthold , Christian Pacha , Artur Wroblewski
发明人： Joerg Berthold , Christian Pacha , Artur Wroblewski
IPC分类号： G08B21/00 , H03B1/00 , H03B5/24 , H03K3/03
CPC分类号： G01R19/16552
摘要： A circuit arrangement for detecting voltage changes, comprising supply terminals configured to apply a first potential and a second potential, a first oscillator and a second oscillator, which are operated with the first potential and the second potential, a voltage dependence of the frequency of the first oscillator differing from a voltage dependence of the frequency of the second oscillator, a first evaluation circuit configured to evaluate the frequency of the first oscillator and a second evaluation circuit configured to evaluate the frequency of the second oscillator, and a comparison circuit configured to compare a value based on the evaluated frequencies of the first oscillator and of the second oscillator with a predetermined threshold value, and to output a voltage change signal indicating an impermissible voltage change between the first potential and the second potential depending on the result of the comparison.
摘要翻译：一种用于检测电压变化的电路装置，包括被配置为施加第一电位和第二电位的电源端子，第一振荡器和第二振荡器，其以第一电位和第二电位运行，电压依赖性第一振荡器与第二振荡器的频率的电压依赖性不同，被配置为评估第一振荡器的频率的第一评估电路和被配置为评估第二振荡器的频率的第二评估电路，以及配置为比较第二振荡器的比较电路基于第一振荡器和具有预定阈值的第二振荡器的估计频率的值，并且根据比较结果输出表示第一电位和第二电位之间的不允许电压变化的电压变化信号。

27. 发明申请

US20090101975A1 Integrated Circuit Arrangement Comprising a Field Effect Transistor, Especially a Tunnel Field Effect Transistor 有权
标题翻译：包括场效应晶体管，特别是隧道场效应晶体管的集成电路布置
公开(公告)号：US20090101975A1
公开(公告)日：2009-04-23
申请号：US11816822
申请日：2005-12-09
申请人： Juergen Holz , Ronald Kakoschke , Thomas Nirschl , Christian Pacha , Klaus Schruefer , Thomas Schulz , Doris Schmitt-Landsiedel
发明人： Juergen Holz , Ronald Kakoschke , Thomas Nirschl , Christian Pacha , Klaus Schruefer , Thomas Schulz , Doris Schmitt-Landsiedel
IPC分类号： H01L29/02
CPC分类号： H01L27/0886 , H01L21/823418 , H01L21/823462 , H01L27/1052 , H01L27/1203 , H01L29/66795 , H01L29/7391 , H01L29/7392 , H01L29/78 , H01L29/785 , H01L29/7854 , H01L29/7856
摘要： An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric (GD1) in comparison with other transistors (T2) on the same integrated circuit arrangement (10). As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions (D1, S1) of the tunnel field effect transistor.
摘要翻译：具体地说，具有与同一集成电路装置（10）上的其它晶体管（T2）相比具有较厚栅极电介质（GD1）的隧道场效应晶体管的解释。作为替代或另外，所述隧道场效应晶体管具有在沟道形成区域的相对远侧的栅极区域或隧道场效应晶体管的连接区域（D1，S1）之间的界面。

28. 发明申请

US20080308850A1 TRANSISTOR WITH REDUCED CHARGE CARRIER MOBILITY AND ASSOCIATED METHODS 有权
标题翻译：具有减少充电载波移动性和相关方法的晶体管
公开(公告)号：US20080308850A1
公开(公告)日：2008-12-18
申请号：US11764500
申请日：2007-06-18
申请人： Jorg Berthold , Christian Pacha , Klaus von Arnim
发明人： Jorg Berthold , Christian Pacha , Klaus von Arnim
IPC分类号： H01L29/76 , G11C11/34 , H01L21/425
CPC分类号： G11C11/412 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1211 , H01L29/04 , H01L29/785
摘要： A device includes a first transistor including a fin and a second transistor including a fin, the fin of the first transistor having a lower charge carrier mobility than the fin of the second transistor. In a method, the fin of the first transistor is treated to have a lower charge carrier mobility than the fin of the second transistor.
摘要翻译：一种器件包括：第一晶体管，包括鳍片和包括鳍片的第二晶体管，第一晶体管的鳍片具有比第二晶体管鳍片更低的载流子迁移率。在一种方法中，第一晶体管的鳍被处理为具有比第二晶体管的鳍更低的载流子迁移率。

29. 发明授权

US08338251B2 Method of manufacture transistor with reduced charge carrier mobility 有权
标题翻译：制造具有降低的载流子迁移率的晶体管的方法
公开(公告)号：US08338251B2
公开(公告)日：2012-12-25
申请号：US13472514
申请日：2012-05-16
申请人： Joerg Berthold , Christian Pacha , Klaus von Arnim
发明人： Joerg Berthold , Christian Pacha , Klaus von Arnim
IPC分类号： H01L21/336
CPC分类号： G11C11/412 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1211 , H01L29/04 , H01L29/785
摘要： One or more embodiments of the invention relate to a method comprising: treating a fin of a first n-channel access transistor in a static random access memory cell to have a lower charge carrier mobility than a fin of a first n-channel pull-down transistor in a first inverter in the memory cell, the first n-channel access transistor being coupled between a first bit line and a first node of the first inverter; and treating a fin of a second n-channel access transistor in the memory cell to have a lower charge carrier mobility than a fin of a second n-channel pull-down transistor in a second inverter in the memory cell, the second n-channel access transistor being coupled between a second bit line and a second node of the second inverter.
摘要翻译：本发明的一个或多个实施例涉及一种方法，包括：处理静态随机存取存储器单元中的第一n沟道存取晶体管的鳍以具有比第一n沟道下拉的鳍更低的载流子迁移率晶体管在存储单元中的第一反相器中，第一n沟道存取晶体管耦合在第一反相器的第一位线和第一节点之间; 以及处理所述存储单元中的第二n沟道存取晶体管的鳍以具有比所述存储单元中的第二反相器中的第二n沟道下拉晶体管的鳍更低的电荷载流子迁移率，所述第二n沟道存取晶体管耦合在第二反相器的第二位线和第二节点之间。

30. 发明授权

US08310027B2 Electronic device and manufacturing method thereof 有权
标题翻译：电子装置及其制造方法
公开(公告)号：US08310027B2
公开(公告)日：2012-11-13
申请号：US12138319
申请日：2008-06-12
申请人： Christian Russ , Christian Pacha , Snezana Jenei , Klaus Schruefer
发明人： Christian Russ , Christian Pacha , Snezana Jenei , Klaus Schruefer
IPC分类号： H01L29/73
CPC分类号： H01L29/7317 , H01L21/8228 , H01L21/823814 , H01L21/823821 , H01L21/8249 , H01L27/0623 , H01L27/082 , H01L27/092 , H01L29/66265 , H01L29/74 , H01L29/785
摘要： Embodiments relate to a bipolar transistor that includes a body region having a fin structure. At least one terminal region may be formed over at least a portion of the body region. The at least one terminal region may be formed as an epitaxially grown region. Embodiments also relate to a vertically integrated electronic device that includes a first terminal region, a second terminal region and a third terminal region. The second terminal region may be arranged over at least a portion of the third terminal region, and at least two of the first, second and third terminal regions may be formed as epitaxially grown regions.
摘要翻译：实施例涉及一种双极晶体管，其包括具有翅片结构的主体区域。可以在身体区域的至少一部分上形成至少一个末端区域。至少一个末端区域可以形成为外延生长区域。实施例还涉及一种垂直集成的电子设备，其包括第一端子区域，第二端子区域和第三端子区域。第二端子区域可以布置在第三端子区域的至少一部分上，并且第一，第二和第三端子区域中的至少两个可以形成为外延生长区域。

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