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21. 发明申请

US20080123415A1 LOW VOLTAGE COLUMN DECODER SHARING A MEMORY ARRAY P-WELL 有权
标题翻译：低电压柱解码器共享存储阵列P-WELL
公开(公告)号：US20080123415A1
公开(公告)日：2008-05-29
申请号：US11557627
申请日：2006-11-08
申请人： Massimiliano Frulio , Stefano Surico , Andrea Sacco , Davide Manfre
发明人： Massimiliano Frulio , Stefano Surico , Andrea Sacco , Davide Manfre
IPC分类号： G11C16/14 , G11C16/04
CPC分类号： G11C16/08
摘要： A plurality of memory sub-arrays are formed in a p-well region. Each of the memory sub-arrays has at least one first-level column decoder that includes a plurality of low-voltage MOS selector transistors that are also formed within the p-well. A last-level decoder is formed outside of the p-well region and includes high-voltage MOS transistors to provide an output signal to one of an array of sense amplifiers. During a memory erase mode of operation, a high voltage is provided to bias the p-well region and a plurality of high-voltage switches are activated to provide a high voltage to gate terminals of the selector transistor in the first-level column decoders. One or more intermediate-level column decoders are formed as low-voltage selector transistors in the p-well between the first-level column decoder and the last-level column decoder. Each of the intermediate-level column decoders also has a high-voltage switch that is activated during a memory erase mode of operation to provide a high voltage to gate terminals of the intermediate-level column decoders.
摘要翻译：多个存储器子阵列形成在p阱区域中。每个存储器子阵列具有至少一个第一级列解码器，其包括也形成在p阱内的多个低压MOS选择晶体管。最后一级解码器形成在p阱区域外部，并且包括高电压MOS晶体管，以向读出放大器阵列之一提供输出信号。在存储器擦除操作模式期间，提供高电压以偏置p阱区域，并且激活多个高压开关以向第一级列解码器中的选择器晶体管的栅极端提供高电压。在第一级列解码器和最后一级列解码器之间的p阱中形成一个或多个中间级列解码器作为低电压选择晶体管。每个中间级列解码器还具有在存储器擦除操作模式期间激活的高压开关，以向中级列解码器的栅极端提供高电压。

22. 发明授权

US07283396B2 System and method for matching resistance in a non-volatile memory 有权
标题翻译：用于在非易失性存储器中匹配电阻的系统和方法
公开(公告)号：US07283396B2
公开(公告)日：2007-10-16
申请号：US11193924
申请日：2005-07-28
申请人： Lorenzo Bedarida , Andrea Sacco , Giorgio Oddone , Simone Bartoli
发明人： Lorenzo Bedarida , Andrea Sacco , Giorgio Oddone , Simone Bartoli
IPC分类号： G11C16/06
CPC分类号： G11C16/26
摘要： A method and system for approximating resistance in a non-volatile memory has a memory matrix. The memory matrix has a plurality of memory cells and a plurality of memory source lines that are coupled to the plurality of memory cells. A reference matrix is coupled to the memory matrix and has a reference cell. A logic generator is coupled to the reference matrix and is configured to generate an approximation, at the reference cell, of a resistance between a selected one of the plurality of memory cells and at least one of the plurality of memory source lines.
摘要翻译：用于近似非易失性存储器中的电阻的方法和系统具有存储器矩阵。存储矩阵具有耦合到多个存储单元的多个存储器单元和多个存储器源极线。参考矩阵耦合到存储器矩阵并具有参考单元。逻辑发生器耦合到参考矩阵，并被配置为在参考单元处产生多个存储器单元中的所选择的一个与多个存储器源极线中的至少一个之间的电阻的近似。

23. 发明申请

US20070076476A1 Method and system for regulating a program voltage value during multilevel memory device programming 有权
标题翻译：用于在多级存储器件编程期间调节编程电压值的方法和系统
公开(公告)号：US20070076476A1
公开(公告)日：2007-04-05
申请号：US11635160
申请日：2006-12-07
申请人： Massimiliano Frulio , Simone Bartoli , Davide Manfre' , Andrea Sacco
发明人： Massimiliano Frulio , Simone Bartoli , Davide Manfre' , Andrea Sacco
IPC分类号： G11C16/04
CPC分类号： G11C16/12 , G11C5/145 , G11C11/5628 , G11C16/04 , G11C16/30 , G11C16/3459 , G11C29/02 , G11C29/021 , G11C29/028
摘要： Regulating a program voltage value during multilevel memory device programming includes utilizing a program path duplicate in an output pump regulator circuit. Further, the output pump regulator circuit is utilized to provide a regulated program voltage for memory cell programming, the regulated program voltage correcting for a program path voltage drop.
摘要翻译：在多级存储器件编程期间调节编程电压值包括在输出泵调节器电路中使用程序路径副本。此外，输出泵调节器电路用于为存储器单元编程提供调节的编程电压，用于编程路径电压降的调节的编程电压。

24. 发明授权

US07184311B2 Method and system for regulating a program voltage value during multilevel memory device programming 有权
标题翻译：用于在多级存储器件编程期间调节编程电压值的方法和系统
公开(公告)号：US07184311B2
公开(公告)日：2007-02-27
申请号：US11123754
申请日：2005-05-05
申请人： Massimiliano Frulio , Simone Bartoli , Davide Manfre′ , Andrea Sacco
发明人： Massimiliano Frulio , Simone Bartoli , Davide Manfre′ , Andrea Sacco
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C11/5628 , G11C7/04 , G11C16/04 , G11C16/12 , G11C16/30 , G11C29/021 , G11C29/028
摘要： Regulating a program voltage value during multilevel memory device programming includes utilizing a program path duplicate in an output pump regulator circuit. Further, the output pump regulator circuit is utilized to provide a regulated program voltage for memory cell programming, the regulated program voltage correcting for a program path voltage drop and compensating for temperature variation.
摘要翻译：在多级存储器件编程期间调节编程电压值包括在输出泵调节器电路中使用程序路径副本。此外，输出泵调节器电路用于提供用于存储器单元编程的调节编程电压，用于编程路径电压降的校准编程电压并补偿温度变化。

25. 发明申请

US20060077709A1 System and method for avoiding offset in and reducing the footprint of a non-volatile memory 有权
标题翻译：用于避免偏移和减少非易失性存储器的占用空间的系统和方法
公开(公告)号：US20060077709A1
公开(公告)日：2006-04-13
申请号：US11126473
申请日：2005-05-11
申请人： Massimiliano Frulio , Riccardo Reggiori , Andrea Sacco , Luca Figini
发明人： Massimiliano Frulio , Riccardo Reggiori , Andrea Sacco , Luca Figini
IPC分类号： G11C16/06
CPC分类号： G11C16/28 , G11C16/3436
摘要： A system and method for avoiding offset in and reducing the footprint of a non-volatile memory that has a plurality of memory bank circuits. Each memory bank circuit has memory cells coupled to sense amplifiers, row and column decoders coupled to the memory cells, and bias circuits coupled to the sense amplifiers. The system includes a reference cell matrix coupled to each of the plurality of memory bank circuits. The reference cell matrix is configured to provide reference cell current for each of the plurality of memory bank circuits.
摘要翻译：一种用于避免偏移并减小具有多个存储器组电路的非易失性存储器的占位面积的系统和方法。每个存储体电路具有耦合到读出放大器，耦合到存储器单元的行和列解码器以及耦合到读出放大器的偏置电路的存储单元。该系统包括耦合到多个存储体电路中的每一个的参考单元矩阵。参考单元矩阵被配置为为多个存储体电路中的每一个提供参考单元电流。

26. 发明授权

US07983098B2 Adaptive regulator for idle state in a charge pump circuit of a memory device 有权
标题翻译：用于存储器件的电荷泵电路中的空闲状态的自适应调节器
公开(公告)号：US07983098B2
公开(公告)日：2011-07-19
申请号：US12571085
申请日：2009-09-30
申请人： Marco Passerini , Stefano Sivero , Andrea Sacco , Monica Marziani
发明人： Marco Passerini , Stefano Sivero , Andrea Sacco , Monica Marziani
IPC分类号： G11C7/00
CPC分类号： G11C7/02 , G11C5/145
摘要： An apparatus and method for improving the performance of an electronic device is disclosed. An idle voltage state is introduced by an adaptive voltage generator when providing or removing a high voltage signal from a line or a node in a circuit. The idle state reduces the undesirable effects of switching disturbances caused by sudden voltage changes in a line or node.
摘要翻译：公开了一种改善电子设备性能的装置和方法。当从电路中的线路或节点提供或去除高电压信号时，自适应电压发生器引入空闲电压状态。空闲状态减少了由于线路或节点中突然的电压变化引起的开关扰动的不良影响。

27. 发明申请

US20100074030A1 ADAPTIVE REGULATOR FOR IDLE STATE IN A CHARGE PUMP CIRCUIT OF A MEMORY DEVICE 有权
标题翻译：用于存储器装置的充电泵电路中的空闲状态的自适应调节器
公开(公告)号：US20100074030A1
公开(公告)日：2010-03-25
申请号：US12571085
申请日：2009-09-30
申请人： Marco Passerini , Stefano Sivero , Andrea Sacco , Monica Marziani
发明人： Marco Passerini , Stefano Sivero , Andrea Sacco , Monica Marziani
IPC分类号： G11C7/00 , G11C7/10
CPC分类号： G11C7/02 , G11C5/145
摘要： An apparatus and method for improving the performance of an electronic device is disclosed. An idle voltage state is introduced by an adaptive voltage generator when providing or removing a high voltage signal from a line or a node in a circuit. The idle state reduces the undesirable effects of switching disturbances caused by sudden voltage changes in a line or node.
摘要翻译：公开了一种改善电子设备性能的装置和方法。当从电路中的线路或节点提供或去除高电压信号时，自适应电压发生器引入空闲电压状态。空闲状态减少了由于线路或节点中突然的电压变化引起的开关扰动的不良影响。

28. 发明授权

US07599231B2 Adaptive regulator for idle state in a charge pump circuit of a memory device 有权
标题翻译：用于存储器件的电荷泵电路中的空闲状态的自适应调节器
公开(公告)号：US07599231B2
公开(公告)日：2009-10-06
申请号：US11548319
申请日：2006-10-11
申请人： Marco Passerini , Stefano Sivero , Andrea Sacco , Monica Marziani
发明人： Marco Passerini , Stefano Sivero , Andrea Sacco , Monica Marziani
IPC分类号： G11C7/00
CPC分类号： G11C7/02 , G11C5/145
摘要： An apparatus and method for improving the performance of an electronic device is disclosed. An idle voltage state is introduced by an adaptive voltage generator when providing or removing a high voltage signal from a line or a node in a circuit. The idle state reduces the undesirable effects of switching disturbances caused by sudden voltage changes in a line or node.
摘要翻译：公开了一种改善电子设备性能的装置和方法。当从电路中的线路或节点提供或去除高电压信号时，自适应电压发生器引入空闲电压状态。空闲状态减少了由于线路或节点中突然的电压变化引起的开关扰动的不良影响。

29. 发明授权

US07551498B2 Implementation of column redundancy for a flash memory with a high write parallelism 有权
标题翻译：实现具有高写入并行性的闪存的列冗余
公开(公告)号：US07551498B2
公开(公告)日：2009-06-23
申请号：US11611452
申请日：2006-12-15
申请人： Simone Bartoli , Stefano Surico , Andrea Sacco , Maria Mostola
发明人： Simone Bartoli , Stefano Surico , Andrea Sacco , Maria Mostola
IPC分类号： G11C7/00
CPC分类号： G11C29/82 , G11C29/806 , G11C29/846
摘要： A redundant memory array has r columns of redundant memory cells, r redundant senses, and a redundant column decoder. Redundant address registers store addresses of defective regular memory cells. Redundant latches are provided in n groups of r latches. Redundancy comparison logic compares addresses of defective regular memory cells with an external input address. If the comparison is true, what is provided is: a DISABLE_LOAD signal to disable the regular senses for one of the n groups of m columns, an ENABLE_LATCH signal to one of the n groups of m columns to disables corresponding regular senses, and one or r REDO signals to a respective one of the r redundant latches in one of the n groups that is disabled. The selected one of the redundant latches activates one of the r redundant senses to access a redundant column.
摘要翻译：冗余存储器阵列具有r列的冗余存储器单元，r冗余感测器和冗余列解码器。冗余地址寄存器存储有缺陷的常规存储单元的地址。在n组r个锁存器中提供冗余锁存器。冗余比较逻辑将缺陷常规存储单元的地址与外部输入地址进行比较。如果比较是真的，提供的是：DISABLE_LOAD信号，用于禁用n列m列中的一个的常规感测，将一个ENABLE_LATCH信号分配给m列的n组中的一组，以禁用相应的常规感官，以及其中之一 r REDO信号到禁用的n个组之一的r个冗余锁存器中的相应一个。所选的一个冗余锁存器激活r个冗余感测之一以访问冗余列。

30. 发明授权

US07242242B2 Fast dynamic low-voltage current mirror with compensated error 有权
标题翻译：具有补偿误差的快速动态低压电流镜
公开(公告)号：US07242242B2
公开(公告)日：2007-07-10
申请号：US11393153
申请日：2006-03-29
申请人： Lorenzo Bedarida , Danut Manea , Mirella Marsella , Andrea Sacco
发明人： Lorenzo Bedarida , Danut Manea , Mirella Marsella , Andrea Sacco
IPC分类号： G05F1/10
CPC分类号： G05F3/262
摘要： A current mirror comprising: current source; a first p-channel transistor having a source coupled to operating potential, and a gate and drain coupled to current source; a second p-channel transistor having a source coupled to operating potential, a gate coupled to gate of first p-channel transistor, and a drain; a zero-threshold p-channel transistor having a source coupled to drain of second p-channel transistor, a gate coupled to gate of first p-channel transistor, and a drain; a first n-channel transistor having a source coupled to ground, and a gate and drain coupled to drain of zero-threshold p-channel transistor; a second n-channel transistor having a source coupled to ground, a gate coupled to gate of first n-channel transistor, and a drain; and a zero-threshold n-channel transistor having a source coupled to drain of second n-channel transistor, a gate coupled to gate of first n-channel transistor, and a drain coupled to current-output node.
摘要翻译：电流镜，包括：电流源; 具有耦合到工作电位的源极的第一p沟道晶体管和耦合到电流源的栅极和漏极; 具有耦合到工作电位的源极的第二p沟道晶体管，耦合到第一p沟道晶体管的栅极的栅极和漏极; 零阈值p沟道晶体管，其具有耦合到第二p沟道晶体管的漏极的源极，耦合到第一p沟道晶体管的栅极的栅极和漏极; 第一n沟道晶体管，其具有耦合到地的源极，以及耦合到零阈值p沟道晶体管的漏极的栅极和漏极; 具有耦合到地的源极的第二n沟道晶体管，耦合到第一n沟道晶体管的栅极的栅极和漏极; 以及零阈值n沟道晶体管，其具有耦合到第二n沟道晶体管的漏极的源极，耦合到第一n沟道晶体管的栅极的栅极和耦合到电流输出节点的漏极。

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