专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US4369510A Soft error rewrite control system 失效
标题翻译：软错误重写控制系统
公开(公告)号：US4369510A
公开(公告)日：1983-01-18
申请号：US172485
申请日：1980-07-25
申请人： Robert B. Johnson , Chester M. Nibby, Jr.
发明人： Robert B. Johnson , Chester M. Nibby, Jr.
IPC分类号： G06F12/16 , G06F11/00 , G06F11/10 , G06F11/14 , G06F11/22 , G11C11/401 , G11C11/406 , G11C29/00 , G11C29/42
CPC分类号： G06F11/00 , G06F11/22 , G11C11/406 , G06F11/106
摘要： Refresh and initialize counter circuits included within a dynamic memory system are supplemented with additional counter control circuits for synchronizing them from the same timing source which drives the refresh and initialize counter circuits. The counter control circuits count in accordance with modulus one less than a maximum count so as to generate a sequence of counts over a corresponding number of cycles of operation for selection of row and column addresses which enable the information stored in each location of the memory system to be read out, corrected for single bit errors and rewritten back thereby rendering the system less susceptible to soft errors such as those produced by alpha particles.
摘要翻译：刷新和初始化包含在动态存储器系统中的计数器电路补充有附加的计数器控制电路，用于使驱动刷新和初始化计数器电路的相同定时源同步它们。计数器控制电路按照小于最大计数的模数进行计数，以便产生用于选择行和列地址的相应操作周期数的计数序列，这使得能够存储在存储器系统的每个位置中的信息要读出，纠正单位错误并重新写回，从而使系统不易受到由α粒子产生的软错误的影响。

22. 发明授权

US4366538A Memory controller with queue control apparatus 失效
标题翻译：具有队列控制装置的内存控制器
公开(公告)号：US4366538A
公开(公告)日：1982-12-28
申请号：US202560
申请日：1980-10-31
申请人： Robert B. Johnson , Chester M. Nibby, Jr.
发明人： Robert B. Johnson , Chester M. Nibby, Jr.
IPC分类号： G06F13/18 , G06F13/00
CPC分类号： G06F13/18
摘要： A memory controller couples to a bus and controls a number of memory module units or memory modules. The controller includes a number of queue circuits for processing a variety of different types of memory requests received from a number of command generating units coupled to the bus requiring the controller to operate in a corresponding number of different modes. The controller includes queue timing and control apparatus which couples to the modules and to the queue circuits for minimizing conflicts between the types of requests and the internal operations required to be performed by the controller.
摘要翻译：存储器控制器耦合到总线并控制多个存储器模块单元或存储器模块。控制器包括多个队列电路，用于处理从耦合到总线的多个命令生成单元接收的各种不同类型的存储器请求，要求控制器以相应数量的不同模式操作。控制器包括队列定时和控制装置，它们耦合到模块和队列电路，用于最小化请求类型与由控制器执行的内部操作之间的冲突。

23. 发明授权

US4190901A Printed circuit board apparatus which facilitates fabrication of units comprising a data processing system 失效
标题翻译：有助于制造包括数据处理系统的单元的印刷电路板装置
公开(公告)号：US4190901A
公开(公告)日：1980-02-26
申请号：US856433
申请日：1977-12-01
申请人： Robert B. Johnson , Chester M. Nibby, Jr.
发明人： Robert B. Johnson , Chester M. Nibby, Jr.
IPC分类号： H05K3/00 , G11C5/00 , H05K1/00 , H05K1/11 , G11C5/02 , G11C5/06
CPC分类号： H05K1/116 , H05K1/029 , H05K1/0295 , H05K1/0298 , H05K2201/09954 , H05K2201/10689
摘要： A printed circuit board assembly includes at least two layers which is able to accommodate a subsystem such as a memory subsystem designed to have one or more optional features. The two layers of the printed circuit board when etched include the required number of horizontal and vertical paths to be connected to all of the integrated circuit chips to be positioned and interconnected thereon. The required holes for such integrated circuit chips when drilled include first sets of holes for mounting groups of integrated circuit chips required for implementing a first group of features and which are to be interconnected to the other integrated circuit chips of the subsystem mounted on the different sections of the board. Second sets of holes are included on the board so as to have a predetermined relationship with the first sets of holes for mounting alternative groups of integrated circuit chips to be interconnected in a manner to implement other features. Thereafter, the circuit board is populated with only those integrated circuit chips required for construction of a memory subsystem with one or more selected features.
摘要翻译：印刷电路板组件包括至少两层，其能够容纳诸如设计成具有一个或多个可选特征的存储器子系统的子系统。当蚀刻时，印刷电路板的两层包括要连接到要定位和互连在其上的所有集成电路芯片的所需数量的水平和垂直路径。用于这种集成电路芯片的所需的孔在钻孔时包括用于实现第一组特征所需的集成电路芯片组的第一组孔，并且其将被连接到安装在不同部分上的子系统的其它集成电路芯片的董事会。第二组孔包括在板上，以便与第一组孔相关联，以便以相互连接的替代的集成电路芯片组来实现其他特征。此后，电路板仅填充用于构造具有一个或多个所选特征的存储器子系统所需的那些集成电路芯片。

24. 发明授权

US4185323A Dynamic memory system which includes apparatus for performing refresh operations in parallel with normal memory operations 失效
标题翻译：动态存储器系统，其包括用于与正常存储器操作并行执行刷新操作的装置
公开(公告)号：US4185323A
公开(公告)日：1980-01-22
申请号：US926480
申请日：1978-07-20
申请人： Robert B. Johnson , Chester M. Nibby, Jr.
发明人： Robert B. Johnson , Chester M. Nibby, Jr.
IPC分类号： G06F13/16 , G11C11/406 , G11C13/00
CPC分类号： G11C11/40603 , G06F13/1636 , G11C11/406
摘要： A memory subsystem for processing memory requests includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes arrays of memory elements corresponding to a number of storage locations, separate addressing and data output circuits. The system further includes common timing, refresh and control circuits. When the memory request specifies a predetermined type of memory operation, the control circuits generate signals for refreshing a location within the memory unit from which data is not being fetched. The control circuits, upon the completion of the refresh operation, in response to another predetermined memory request, refreshes the corresponding row within the other unit in parallel with fetching data from first unit. Upon completing refresh operations within both units, the control circuits generate a control signal for inhibiting the refresh circuits from performing a mandatory refresh operation, upon a row of memory elements within the memory units in which access to the memory system is inhibited temporarily, enabling memory operations to continue without interruption.
摘要翻译：用于处理存储器请求的存储器子系统包括至少一对独立可寻址的动态存储器模块单元。每个存储器单元包括对应于多个存储位置的存储器元件阵列，单独的寻址和数据输出电路。该系统还包括通用定时，刷新和控制电路。当存储器请求指定预定类型的存储器操作时，控制电路产生用于刷新存储器单元内未被取出数据的位置的信号。控制电路在完成刷新操作时响应于另一预定存储器请求，与从第一单元获取数据并行地刷新另一单元内的对应行。在完成两个单元中的刷新操作之后，控制电路产生用于禁止刷新电路执行强制刷新操作的控制信号，其中存储器单元中存储单元中的一行存储器单元暂时禁止对存储器系统的访问，使得存储器操作继续不间断。

25. 发明授权

US5345573A High speed burst read address generation with high speed transfer 失效
标题翻译：高速突发读地址生成与高速传输
公开(公告)号：US5345573A
公开(公告)日：1994-09-06
申请号：US771702
申请日：1991-10-04
申请人： Raymond D. Bowden, III , Chester M. Nibby, Jr.
发明人： Raymond D. Bowden, III , Chester M. Nibby, Jr.
IPC分类号： G06F12/08 , G06F13/28 , G11C11/408 , G06F12/00 , G11C11/409
CPC分类号： G06F13/28 , G06F12/0879
摘要： A memory system coupled to a local bus of a microprocessor includes at least a pair of dynamic random access memories (DRAMs) and includes circuits for storing the first address of an address sequence at the beginning of each burst operation and uses predetermined bits to generate any one of a set of address sequences as a function of the states of these bits. A first predetermined address bit is used to select different sequences of addressed readout data words to be transferred by the pair of DRAMs to the user. A second predetermined address bit is complemented to reverse two high order addressed word responses with two low order addressed word responses of specific address sequences. These operations are utilized in all of the required address sequences within different subgroups.
摘要翻译：耦合到微处理器的本地总线的存储器系统包括至少一对动态随机存取存储器（DRAM），并且包括用于在每个突发操作开始时存储地址序列的第一地址的电路，并且使用预定位来产生任何作为这些位的状态的函数的一组地址序列中的一个。第一预定地址位被用于选择由该对DRAM传送给用户的寻址读出数据字的不同序列。对第二预定地址位进行补码，以反转具有特定地址序列的两个低阶寻址字响应的两个高阶寻址字应答。这些操作在不同子组中的所有必需地址序列中使用。

26. 发明授权

US4833601A Cache resiliency in processing a variety of address faults 失效
标题翻译：缓存弹性处理各种地址故障
公开(公告)号：US4833601A
公开(公告)日：1989-05-23
申请号：US55577
申请日：1987-05-28
申请人： George J. Barlow , James W. Keeley , Chester M. Nibby, Jr.
发明人： George J. Barlow , James W. Keeley , Chester M. Nibby, Jr.
IPC分类号： G06F11/00 , G06F11/07 , G06F11/14 , G06F11/16 , G06F12/08 , G06F12/10
CPC分类号： G06F11/073 , G06F11/0724 , G06F11/0793 , G06F12/0815 , G06F11/0757 , G06F11/141
摘要： A cache memory subsystem has multilevel directory memory and buffer memory pipeline stages shared by at least a pair of independently operated central processing units and a first in first out (FIFO) device which connects to a system bus of a tightly coupled data processing system. The cache subsystem includes a number of programmable control circuits which are connected to receive signals representative of the type of operations performable by the cache subsystem. These signals are logically combined for generating an output signal indicating whether or not the contents of the directiory memory should be flushed when any one of a number of types of address or system faults has been detected in order to maintain cache coherency.

27. 发明授权

US4527251A Remap method and apparatus for a memory system which uses partially good memory devices 失效
标题翻译：使用部分良好的存储器件的存储器系统的重映射方法和装置
公开(公告)号：US4527251A
公开(公告)日：1985-07-02
申请号：US450691
申请日：1982-12-17
申请人： Chester M. Nibby, Jr. , Reeni Goldin , Timothy A. Andrews
发明人： Chester M. Nibby, Jr. , Reeni Goldin , Timothy A. Andrews
IPC分类号： G06F12/02 , G11C29/00 , G06F13/00
CPC分类号： G11C29/76 , G06F12/0292
摘要： A remapping method and apparatus is employed by a memory controller system which includes a microprocessing section which couples to a memory section. The memory section includes a partially good bulk random access memory constructed from a plurality of bit wide chips containing a predefined small number of row or column faults randomly distributed. System columns of chips are organized into a plurality of groups or slices, each of which provide a different predetermined portion of the locations within the partially good bulk memory. A defective-free memory having substantially less capacity is similarly organized. Both memories couple to a static memory which is remapped under the control of the microprocessing section. Prior to remapping, the microprocessing section generates a "slice bit map" indicating the results of testing successive bit groups/slices within the bulk memory locations. Thereafter, the microprocessor section interprets the "slice bit map" and assigns column addresses in the static memory locations designating locations within the defect-free memory. The assignment is carried out in a predetermined manner according to fault category to maximize the use of all of the groups of bit locations within each defect free memory location thereby making storage available for remapping new faults.
摘要翻译：存储器控制器系统采用重映射方法和装置，该系统包括耦合到存储器部分的微处理部分。存储器部分包括由多个位宽的芯片构成的部分良好的批量随机存取存储器，其包含预定义的少量随机分配的行或列故障。芯片的系统列被组织成多个组或片，每个组或片提供部分良好大容量存储器内的位置的不同预定部分。类似地组织了具有基本上较小容量的无缺陷存储器。两个存储器耦合到在微处理部分的控制下重新映射的静态存储器。在重新映射之前，微处理部分产生指示在大容量存储器位置内测试连续位组/片的结果的“片位图”。此后，微处理器部分解释“切片位图”，并在无缺陷存储器内指定位置的静态存储单元中分配列地址。根据故障类别以预定方式执行分配，以最大限度地利用每个无缺陷存储器位置内的所有位组组的使用，从而使存储可用于重新映射新故障。

28. 发明授权

US4468731A Identification apparatus for use in a controller to facilitate the diagnosis of faults 失效
标题翻译：用于控制器的识别装置，以便于诊断故障
公开(公告)号：US4468731A
公开(公告)日：1984-08-28
申请号：US330971
申请日：1981-12-15
申请人： Robert B. Johnson , Chester M. Nibby, Jr. , Edward R. Salas
发明人： Robert B. Johnson , Chester M. Nibby, Jr. , Edward R. Salas
IPC分类号： G06F11/22 , G06F11/10
CPC分类号： G06F11/22
摘要： A data processing system includes a main memory system which couples in common with a central processing unit to a bus for transfer of data between the central processing unit and memory system. The memory system includes a plurality of memory controllers, each of which controls the operation of a number of memory modules. Each controller also includes reconfiguration apparatus for enabling reconfiguration of the memory system upon detection of a fault. The reconfiguration apparatus includes apparatus for identifying the type and design revision of the controller associated therewith enabling more expeditious fault diagnosis based upon status signals provided by the controller during diagnostic testing by the central processing unit.
摘要翻译：一种数据处理系统包括一个与中央处理单元共同耦合到总线的主存储系统，用于在中央处理单元和存储器系统之间传送数据。存储器系统包括多个存储器控制器，每个存储器控制器控制多个存储器模块的操作。每个控制器还包括重新配置装置，用于在检测到故障时能够重新配置存储器系统。重新配置装置包括用于识别与其相关联的控制器的类型和设计版本的装置，其基于由中央处理单元在诊断测试期间由控制器提供的状态信号进行更快速的故障诊断。

29. 发明授权

US4366539A Memory controller with burst mode capability 失效
标题翻译：具有突发模式功能的存储控制器
公开(公告)号：US4366539A
公开(公告)日：1982-12-28
申请号：US202819
申请日：1980-10-31
申请人： Robert B. Johnson , Chester M. Nibby, Jr.
发明人： Robert B. Johnson , Chester M. Nibby, Jr.
IPC分类号： G06F13/16 , G06F13/28 , G06F13/00
CPC分类号： G06F13/28 , G06F13/16
摘要： A memory controller coupled to a number of memory module units and includes a number of control circuits. The control circuits include address counter circuits which are loaded with a portion of the address of each predetermined type of command or memory request from a requesting device. This command when decoded causes the controller to read out from the memory module units a predetermined number of word pairs starting with the location specified by the stored address portion.
摘要翻译：存储器控制器，其耦合到多个存储器模块单元并且包括多个控制电路。控制电路包括地址计数器电路，其中装载有来自请求装置的每个预定类型的命令或存储器请求的地址的一部分。当解码时，该命令使得控制器从存储器模块单元读出由存储的地址部分指定的位置开始的预定数量的字对。

30. 发明授权

US4323965A Sequential chip select decode apparatus and method 失效
标题翻译：顺序芯片选择解码装置及方法
公开(公告)号：US4323965A
公开(公告)日：1982-04-06
申请号：US110523
申请日：1980-01-08
申请人： Robert B. Johnson , Chester M. Nibby, Jr. , Dana Moore
发明人： Robert B. Johnson , Chester M. Nibby, Jr. , Dana Moore
IPC分类号： G11C11/406 , G06F12/04 , G06F12/06 , G06F13/00
CPC分类号： G06F12/04 , G06F12/0607
摘要： A memory subsystem which couples to a multiword bus for processing memory requests received therefrom includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem receives as part of each memory request an address, the least significant portion of which selects the row of chips to be accessed within one of the pair of memory units. Address decode circuits include gating circuits which couple to both module units. The gating circuits are interconnected so that the decoding of the least significant address bits results in the generation of a pair of row address strobe signals. These signals enable simultaneously the rows of RAM chips for access within both module units for read out of information to a multiword bus eliminating any delay in address incrementing.
摘要翻译：耦合到多字总线以用于处理从其接收的存储器请求的存储器子系统包括至少一对独立可寻址的动态存储器模块单元。每个存储器单元包括多行随机存取存储器（RAM）芯片。子系统作为每个存储器请求的一部分接收一个地址，其中最不重要的部分在一对存储器单元之一内选择要访问的芯片行。地址解码电路包括耦合到两个模块单元的选通电路。门控电路互连，使得对最低有效地址位的解码导致产生一对行地址选通信号。这些信号同时支持RAM芯片的行，以在两个模块单元内进行访问，以将信息读出到多字总线，从而消除地址递增的任何延迟。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式