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21. 发明授权

US06455373B1 Semiconductor device having gate edges protected from charge gain/loss 有权
标题翻译：具有防止电荷增益/损耗的栅极边缘的半导体器件
公开(公告)号：US06455373B1
公开(公告)日：2002-09-24
申请号：US09834419
申请日：2001-04-12
申请人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
发明人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L21/823468 , H01L27/105 , H01L27/11536
摘要： A plurality of core gate stacks and periphery gates on the substrate, each core gate stack and periphery gate having at least one side and first and second protective shoulders formed on said plurality of core gate stacks and periphery gates, such that a dopant can be implanted sequentially into source and drain regions of a substrate supporting the stacks to establish transistors and such that charge migration into said at least one side of the gate stacks during interlayer dielectric (ILD) formation and device metallization is prevented, at least the second shoulder being frabricated from at least one material selected from a group consisting essentially of nitride and silicon oxynitride (SiON).
摘要翻译：在基板上的多个核心栅极叠层和周边栅极，每个芯栅极叠层和周边栅极具有形成在所述多个芯栅极叠层和外围栅极上的至少一个侧面和第一和第二保护肩部，使得掺杂剂可被植入顺序地进入支撑堆叠的衬底的源极和漏极区域以建立晶体管，并且防止在层间电介质（ILD）形成和器件金属化期间电荷迁移到栅极叠层的所述至少一个侧面，至少第二肩部被破坏选自由氮化物和氮氧化硅（SiON）组成的组中的至少一种材料。

22. 发明授权

US06448608B1 Capping layer 有权
标题翻译：封盖层
公开(公告)号：US06448608B1
公开(公告)日：2002-09-10
申请号：US09631894
申请日：2000-08-04
申请人： Tuan Duc Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui
发明人： Tuan Duc Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui
IPC分类号： H01L29788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11543
摘要： An improved flash memory device, which comprises core stacks and periphery stacks which are protected with an oxide layer, a protective layer and an insulating layer. A high energy dopant implant is used to pass the dopant through the insulating layer, the protective layer, and oxide layer into the substrate to create source and drain regions, without using a self aligned etch. The flash memory device has an intermetallic dielectric layer placed over the core stacks and the periphery stacks. A tungsten plug is placed in the intermetallic dielectric layer to provide an electrical connection to the drain of the flash memory device. The use of a high energy dopant implant to pass through dopant through the insulating layer, the protective layer, and the oxide layer into the substrate without the use of a self aligned source etch, reduces damage to the core stacks and periphery stacks caused by various etches during the production of the flash memory device and provides insulation to reduce unwanted current leakage between the tungsten plug and the stacks.
摘要翻译：一种改进的闪速存储器件，其包括用氧化物层，保护层和绝缘层保护的芯堆叠和外围堆叠。使用高能掺杂剂注入来使掺杂剂通过绝缘层，保护层和氧化物层进入衬底以产生源区和漏区，而不使用自对准蚀刻。闪存器件具有放置在芯堆叠和外围堆叠体上的金属间介电层。将钨塞放置在金属间介电层中以提供与闪存器件的漏极的电连接。使用高能掺杂剂注入物通过掺杂剂通过绝缘层，保护层和氧化物层进入衬底而不使用自对准源蚀刻，减少了由各种不同的引线引起的芯堆叠和外围堆叠的损坏在制造闪速存储器件期间蚀刻并提供绝缘以减少钨丝塞和叠层之间的不必要的电流泄漏。

23. 发明授权

US06248627B1 Method for protecting gate edges from charge gain/loss in semiconductor device 有权
标题翻译：在半导体器件中保护栅极边缘免受电荷增益/损耗的方法
公开(公告)号：US06248627B1
公开(公告)日：2001-06-19
申请号：US09376658
申请日：1999-08-18
申请人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
发明人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L21/823468 , H01L27/105 , H01L27/11536
摘要： A method for making a ULSI MOSFET includes covering core gate stacks with a first protective layer, etching away the first layer such that intended source regions of the substrate are exposed, and implanting dopant into the source regions. A second protective layer is then deposited over the first layer and is etched back to conform to the first layer, covering only the sides of the gate stacks, and exposing intended drain regions of the substrate. Dopant is then implanted into the drain regions. During subsequent manufacturing steps including ILD formation and metallization, mobile ions and other process-induced charges are blocked from entering the floating gates of the gate stacks by the protective layers, thereby preventing unwanted charge gain/loss.
摘要翻译：制造ULSI MOSFET的方法包括用第一保护层覆盖芯栅极叠层，蚀刻掉第一层，使得衬底的预期源极区域暴露，并将掺杂剂注入到源极区域中。然后在第一层上沉积第二保护层，并将其回蚀刻以符合第一层，仅覆盖栅极堆叠的侧面，并暴露衬底的预期漏极区域。然后将掺杂剂注入漏区。在包括ILD形成和金属化的后续制造步骤期间，阻止移动离子和其它工艺感应电荷被保护层进入栅极堆叠的浮置栅极，从而防止不必要的电荷增益/损耗。

24. 发明授权

US6046932A Circuit implementation to quench bit line leakage current in programming and over-erase correction modes in flash EEPROM 有权
标题翻译：电路实现在闪存EEPROM中编程和过擦除校正模式中的位线漏电流
公开(公告)号：US6046932A
公开(公告)日：2000-04-04
申请号：US417273
申请日：1999-10-13
申请人： Colin Bill , Sameer S. Haddad , Jonathan Shi-Chang Su , Vei-Han Chan
发明人： Colin Bill , Sameer S. Haddad , Jonathan Shi-Chang Su , Vei-Han Chan
IPC分类号： G11C16/06 , G11C16/02 , G11C16/30 , G11C16/34 , H01L21/8247 , H01L27/115 , G11C16/12 , G11C16/16
CPC分类号： G11C16/3409 , G11C16/30 , G11C16/3404
摘要： A method of and a flash memory device for quenching bitline leakage current during programming and over-erase correction operations. The flash memory cells are organized in an array of I/O blocks with each block having columns and rows. An array of resistors is connected between the common array source connection and ground. The array of resistors is made up of sets of resistors, each set having a programming mode resistor and an APDE mode resistor. A data buffer switches either a programming mode resistor or APDE mode resistor into the circuit when a bitline is selected for either programming or APDE. The values of the resistors are selected to raise the voltage at the source above a selected threshold voltage of the memory cells so that over-erased cells will not provide leakage current to the bitline during either programming or APDE.
摘要翻译：一种用于在编程和过擦除校正操作期间淬灭位线泄漏电流的闪存器件的方法和闪存器件。闪存单元被组织成具有每个块具有列和行的I / O块的阵列。公共阵列源连接和地之间连接一组电阻。电阻器阵列由电阻器组成，每组具有编程模式电阻器和APDE模式电阻器。当选择编程或APDE的位线时，数据缓冲区将编程模式电阻器或APDE模式电阻器切换到电路中。选择电阻器的值以将源极处的电压提高到存储器单元的选定阈值电压以上，使得在编程或APDE期间，过擦除的单元将不会向位线提供泄漏电流。

25. 发明授权

US5815438A Optimized biasing scheme for NAND read and hot-carrier write operations 失效
标题翻译： NAND读取和热载体写入操作的优化偏置方案
公开(公告)号：US5815438A
公开(公告)日：1998-09-29
申请号：US810170
申请日：1997-02-28
申请人： Sameer S. Haddad , Pau-Ling Chen
发明人： Sameer S. Haddad , Pau-Ling Chen
IPC分类号： G11C16/26 , G11C16/06
CPC分类号： G11C16/3427 , G11C16/26
摘要： There is provided an improved method for eliminating hot-carrier disturb during a read operation in a NAND memory architecture in which a floating gate device is used as a select gate. A first positive pulse voltage having a ramp-rate characteristic on its leading edge is applied to the drain of the floating gate device during the read operation. Simultaneously, a second positive pulse voltage is applied to the control gate of the floating gate device during the read operation so as to overlap the first positive pulse voltage.
摘要翻译：提供了一种在浮动栅极器件用作选择栅极的NAND存储器架构中在读取操作期间消除热载波干扰的改进方法。在读取操作期间，在其前沿具有斜率特性的第一正脉冲电压被施加到浮动栅极器件的漏极。同时，在读取操作期间，第二正脉冲电压施加到浮动栅极器件的控制栅极，以便与第一正脉冲电压重叠。

26. 发明授权

US5590076A Channel hot-carrier page write 失效
标题翻译：频道热门页面写入
公开(公告)号：US5590076A
公开(公告)日：1996-12-31
申请号：US493138
申请日：1995-06-21
申请人： Sameer S. Haddad , Chi Chang , David K. Y. Liu
发明人： Sameer S. Haddad , Chi Chang , David K. Y. Liu
IPC分类号： G11C16/02 , G11C16/10 , G11C7/00
CPC分类号： G11C16/10
摘要： Disclosed herein is a channel hot-carrier page write including an array of stacked gate flash EEPROM memory cells operating in a very low energy programming mode permitting page writing of 1024 bits within a 20-100 .mu.S programming interval. Internal programming voltage levels are derived from on-chip circuits, such as charge pumps, operated from a single +V.sub.CC source. In a preferred embodiment, a cache memory buffers data transfers between a computer bus and the page oriented storage array. In another embodiment, core doping is increased in the channel and drain regions to enhance hot carrier injection and to lower the programming drain voltage. The stacked floating gate structure is shown to exhibit a high programming efficiency in a range from 10.sup.-6 to 10.sup.-4 at drain voltages below 5.2 VDC. In another embodiment AC components of the programming current are minimized by precharging a common source line at the start of a programming cycle.
摘要翻译：本文公开了一种通道热载体页面写入，其包括以非常低能量编程模式操作的堆叠栅极快闪EEPROM存储器单元的阵列，允许在20-100μs编程间隔内1024页的页写入。内部编程电压电平源自片上电路，如电荷泵，由单个+ VCC源运行。在优选实施例中，高速缓冲存储器缓冲计算机总线和面向页面的存储阵列之间的数据传输。在另一个实施例中，在沟道和漏极区域中增加了芯掺杂以增强热载流子注入并降低编程漏极电压。堆叠的浮置栅极结构在低于5.2VDC的漏极电压下表现出在10-6至10-4的范围内的高编程效率。在另一个实施例中，通过在编程周期开始时对公共源极线进行预充电，使编程电流的AC分量最小化。

27. 发明授权

US5491657A Method for bulk (or byte) charging and discharging an array of flash EEPROM memory cells 失效
标题翻译：批量（或字节）对闪存EEPROM存储单元阵列进行充电和放电的方法
公开(公告)号：US5491657A
公开(公告)日：1996-02-13
申请号：US393636
申请日：1995-02-24
申请人： Sameer S. Haddad , Hao Fang
发明人： Sameer S. Haddad , Hao Fang
IPC分类号： G11C16/10 , G11C16/16 , G11C11/40
CPC分类号： G11C16/3477 , G11C16/10 , G11C16/16 , G11C16/3427 , G11C16/3486 , G11C2216/16 , G11C2216/18
摘要： There is provided an improved method for bulk (or byte) programming an array of flash EEPROM memory cells. A negative voltage is applied to the substrate of the array. A reference voltage of zero volts is applied simultaneously to the drain regions of selected memory cells that are to be programmed. There is also applied simultaneously the same reference voltage of zero volts to the control gates of the selected memory cells. The present invention provides for low current consumption and fast programming of the memory cell, which require only a single, low voltage power supply. The endurance reliability is greater than 100,000 cycles.
摘要翻译：提供了用于批量（或字节）编程闪存EEPROM存储器单元阵列的改进方法。对阵列的衬底施加负电压。将零编程的参考电压同时施加到要编程的所选存储单元的漏极区域。同时也向所选择的存储器单元的控制栅极同时施加零伏特的相同参考电压。本发明提供了仅需要单个低电压电源的存储单元的低电流消耗和快速编程。耐久可靠性大于100,000次。

28. 发明授权

US06894932B1 Dual cell memory device having a top dielectric stack 有权
标题翻译：具有顶部电介质叠层的双电池存储器件
公开(公告)号：US06894932B1
公开(公告)日：2005-05-17
申请号：US10716230
申请日：2003-11-18
申请人： Ashot Melik-Martirosian , Mark W. Randolph , Sameer S. Haddad
发明人： Ashot Melik-Martirosian , Mark W. Randolph , Sameer S. Haddad
IPC分类号： G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8246 , H01L27/06 , H01L27/115 , H01L29/792
CPC分类号： H01L27/11568 , G11C16/0475 , H01L21/28273 , H01L27/0688 , H01L27/115 , H01L27/11578 , H01L29/512 , H01L29/517 , H01L29/66833 , H01L29/7923
摘要： A non-volatile memory device includes a semiconductor substrate and a pair of buried bitlines within the substrate. A bottom dielectric layer is formed over the substrate and a charge trapping dielectric layer is formed over the bottom dielectric layer. A multi-layer top dielectric stack is formed over the charge trapping dielectric layer. The top dielectric stack includes a first oxide layer, a nitride layer, and a second oxide layer. A wordline is formed over the top dielectric stack. The multi-layer top dielectric stack has a reduced electrical thickness, thereby providing a memory device, which is operative to be programmed using a reduced operating voltage of less than about +8 Volts.
摘要翻译：非易失性存储器件包括衬底内的半导体衬底和一对掩埋位线。底部电介质层形成在衬底上，并且电荷俘获电介质层形成在底部电介质层上。在电荷捕获介电层上形成多层顶层电介质叠层。顶部电介质堆叠包括第一氧化物层，氮化物层和第二氧化物层。在顶部电介质叠层上形成字线。多层顶部电介质堆叠具有减小的电气厚度，从而提供存储器件，其可操作地使用小于约+8伏特的降低的工作电压进行编程。

29. 发明授权

US06894925B1 Flash memory cell programming method and system 有权
标题翻译：闪存单元编程方法和系统
公开(公告)号：US06894925B1
公开(公告)日：2005-05-17
申请号：US10342585
申请日：2003-01-14
申请人： Sheunghee Park , Sameer S. Haddad , Chi Chang , Richard M. Fastow , Ming Sang Kwan , Zhigang Wang
发明人： Sheunghee Park , Sameer S. Haddad , Chi Chang , Richard M. Fastow , Ming Sang Kwan , Zhigang Wang
IPC分类号： G11C11/56 , G11C16/04 , H01L29/423 , H01L29/788
CPC分类号： G11C11/5621 , G11C16/0416 , H01L29/42324 , H01L29/7883
摘要： A flash memory cell programming system and method that facilitate efficient and quick operation of a flash memory cell by providing a biasable well (e.g., substrate) is presented. The biasable well flash memory cell enables increases in electrical field strengths in a manner that eases resistance to charge penetration of a dielectric barrier (e.g., oxide) around a charge trapping region (e.g., a floating gate). The present biasable well system and method also create a self convergence point that increase control during programming operations and reduces the chances of excessive correction for over erased memory cells. The biasing can assist hard programming to store information and/or soft programming to correct the effects of over-erasing. The biasing can also reduce stress on a drain voltage pump, reduce leakage current and reduce programming durations. Some implementations also include a biasable control gate component, biasable source component and biasable drain component.
摘要翻译：提出了一种闪存单元编程系统和方法，其通过提供可偏置的阱（例如，衬底）来促进闪存单元的有效和快速的操作。可偏置阱快闪存储器单元能够以减轻电荷俘获区域（例如浮栅）周围的电介质势垒（例如氧化物）的电荷穿透的方式增加电场强度。本发明的偏压井系统和方法还创建了一个自会聚点，从而在编程操作期间增加了控制，并降低了对擦除过的存储器单元过度校正的可能性。偏置可以帮助硬编程来存储信息和/或软编程以校正过度擦除的影响。偏置还可以减少漏极电压泵上的应力，减少泄漏电流并减少编程持续时间。一些实施方案还包括可偏置控制栅极分量，可偏置源分量和可偏置漏极分量。

30. 发明授权

US06735124B1 Flash memory device having four-bit cells 失效
标题翻译：具有四位单元的闪存器件
公开(公告)号：US06735124B1
公开(公告)日：2004-05-11
申请号：US10315632
申请日：2002-12-10
申请人： Ashot Melik-Martirosian , Sameer S. Haddad , Mark W. Randolph
发明人： Ashot Melik-Martirosian , Sameer S. Haddad , Mark W. Randolph
IPC分类号： G11C1604
CPC分类号： G11C16/0475 , G11C11/5671
摘要： A non-volatile memory device includes a semiconductor substrate having first and second bitlines buried therein. The first bitline serves as a source terminal and the second bitline serves as a drain terminal. An oxide-nitride-oxide (ONO) stack is formed over the substrate. The ONO stack includes a charge storing layer having at least four charge storing cells therein. A pair of complementary conductive regions are disposed on opposite sides of the ONO stack extending in a direction perpendicular to the first and second bitlines. A wordline, which serves as a gate electrode, is disposed above the ONO stack and laterally between the first and second complementary conductive regions.
摘要翻译：非易失性存储器件包括其中埋有第一和第二位线的半导体衬底。第一位线用作源极端子，第二位线用作漏极端子。在衬底上形成氧化物 - 氧化物 - 氧化物（ONO）堆叠。 ONO堆叠包括其中具有至少四个电荷存储单元的电荷存储层。一对互补导电区域设置在ONO堆叠的相对两侧，该垂直于第一和第二位线的方向延伸。用作栅电极的字线布置在ONO堆叠之上，并且横向地设置在第一和第二互补导电区域之间。

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