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1. 发明授权

US06868014B1 Memory device with reduced operating voltage having dielectric stack 有权
标题翻译：具有电介质叠层的具有降低工作电压的存储器
公开(公告)号：US06868014B1
公开(公告)日：2005-03-15
申请号：US10430604
申请日：2003-05-06
申请人： Ashot Melik-Martirosian , Mark W. Randolph , Sameer S. Haddad
发明人： Ashot Melik-Martirosian , Mark W. Randolph , Sameer S. Haddad
IPC分类号： G11C16/04 , H01L21/28 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7923 , H01L21/28282 , H01L29/42324 , H01L29/7887
摘要： A non-volatile memory device includes a semiconductor substrate and a pair of buried bitlines within the substrate. A scaled down dielectric stack is formed over the substrate. The scaled down dielectric stack includes a scaled down top dielectric layer, a scaled down charge trapping dielectric layer and a bottom dielectric layer. A wordline is formed over the dielectric stack. The memory device is operative to be programmed using a reduced wordline operating voltage of less than about +8 Volts, and to be erased using a reduced wordline operating voltage of less than about −6 Volts.
摘要翻译：非易失性存储器件包括衬底内的半导体衬底和一对掩埋位线。在衬底上形成按比例缩小的电介质叠层。按比例缩小的电介质堆叠包括按比例缩小的顶部介电层，按比例缩小的电荷俘获电介质层和底部电介质层。在介质叠层上形成一条字线。存储器装置可操作以使用小于约+8伏特的减小的字线工作电压进行编程，并且使用小于约-6伏的减小的字线工作电压来擦除存储器装置。

2. 发明授权

US06862221B1 Memory device having a thin top dielectric and method of erasing same 有权
标题翻译：具有薄顶电介质的存储器件及其擦除方法
公开(公告)号：US06862221B1
公开(公告)日：2005-03-01
申请号：US10459102
申请日：2003-06-11
申请人： Ashot Melik-Martirosian , Mark W. Randolph , Sameer S. Haddad
发明人： Ashot Melik-Martirosian , Mark W. Randolph , Sameer S. Haddad
IPC分类号： G11C16/04 , H01L21/28 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28282 , G11C16/0475 , H01L29/42324 , H01L29/7887 , H01L29/7923
摘要： A non-volatile memory device includes a semiconductor substrate and a source and drain within the substrate. A dielectric stack is formed over the substrate. The dielectric stack includes a thin top dielectric layer. A gate electrode is formed over the dielectric stack. The memory device is operative to perform a direct tunneling channel erase operation in which a pair of charge storing cells within a charge storing layer are erased via direct tunneling through the thin top dielectric layer.
摘要翻译：非易失性存储器件包括半导体衬底和衬底内的源极和漏极。在衬底上形成电介质叠层。电介质堆叠包括薄的顶部电介质层。在电介质叠层上形成栅电极。存储器装置可操作以执行直接隧道通道擦除操作，其中电荷存储层内的一对电荷存储单元通过经由薄顶介电层的直接隧穿而被擦除。

3. 发明授权

US06894932B1 Dual cell memory device having a top dielectric stack 有权
标题翻译：具有顶部电介质叠层的双电池存储器件
公开(公告)号：US06894932B1
公开(公告)日：2005-05-17
申请号：US10716230
申请日：2003-11-18
申请人： Ashot Melik-Martirosian , Mark W. Randolph , Sameer S. Haddad
发明人： Ashot Melik-Martirosian , Mark W. Randolph , Sameer S. Haddad
IPC分类号： G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8246 , H01L27/06 , H01L27/115 , H01L29/792
CPC分类号： H01L27/11568 , G11C16/0475 , H01L21/28273 , H01L27/0688 , H01L27/115 , H01L27/11578 , H01L29/512 , H01L29/517 , H01L29/66833 , H01L29/7923
摘要： A non-volatile memory device includes a semiconductor substrate and a pair of buried bitlines within the substrate. A bottom dielectric layer is formed over the substrate and a charge trapping dielectric layer is formed over the bottom dielectric layer. A multi-layer top dielectric stack is formed over the charge trapping dielectric layer. The top dielectric stack includes a first oxide layer, a nitride layer, and a second oxide layer. A wordline is formed over the top dielectric stack. The multi-layer top dielectric stack has a reduced electrical thickness, thereby providing a memory device, which is operative to be programmed using a reduced operating voltage of less than about +8 Volts.
摘要翻译：非易失性存储器件包括衬底内的半导体衬底和一对掩埋位线。底部电介质层形成在衬底上，并且电荷俘获电介质层形成在底部电介质层上。在电荷捕获介电层上形成多层顶层电介质叠层。顶部电介质堆叠包括第一氧化物层，氮化物层和第二氧化物层。在顶部电介质叠层上形成字线。多层顶部电介质堆叠具有减小的电气厚度，从而提供存储器件，其可操作地使用小于约+8伏特的降低的工作电压进行编程。

4. 发明授权

US06735124B1 Flash memory device having four-bit cells 失效
标题翻译：具有四位单元的闪存器件
公开(公告)号：US06735124B1
公开(公告)日：2004-05-11
申请号：US10315632
申请日：2002-12-10
申请人： Ashot Melik-Martirosian , Sameer S. Haddad , Mark W. Randolph
发明人： Ashot Melik-Martirosian , Sameer S. Haddad , Mark W. Randolph
IPC分类号： G11C1604
CPC分类号： G11C16/0475 , G11C11/5671
摘要： A non-volatile memory device includes a semiconductor substrate having first and second bitlines buried therein. The first bitline serves as a source terminal and the second bitline serves as a drain terminal. An oxide-nitride-oxide (ONO) stack is formed over the substrate. The ONO stack includes a charge storing layer having at least four charge storing cells therein. A pair of complementary conductive regions are disposed on opposite sides of the ONO stack extending in a direction perpendicular to the first and second bitlines. A wordline, which serves as a gate electrode, is disposed above the ONO stack and laterally between the first and second complementary conductive regions.
摘要翻译：非易失性存储器件包括其中埋有第一和第二位线的半导体衬底。第一位线用作源极端子，第二位线用作漏极端子。在衬底上形成氧化物 - 氧化物 - 氧化物（ONO）堆叠。 ONO堆叠包括其中具有至少四个电荷存储单元的电荷存储层。一对互补导电区域设置在ONO堆叠的相对两侧，该垂直于第一和第二位线的方向延伸。用作栅电极的字线布置在ONO堆叠之上，并且横向地设置在第一和第二互补导电区域之间。

5. 发明授权

US08957472B2 Memory device having trapezoidal bitlines and method of fabricating same 有权
标题翻译：具有梯形位线的存储器件及其制造方法
公开(公告)号：US08957472B2
公开(公告)日：2015-02-17
申请号：US13357252
申请日：2012-01-24
申请人： Ashot Melik-Martirosian , Mark T. Ramsbey , Mark W. Randolph
发明人： Ashot Melik-Martirosian , Mark T. Ramsbey , Mark W. Randolph
IPC分类号： H01L29/792 , H01L27/115 , H01L29/66
CPC分类号： H01L29/7923 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of bitlines, where the bitlines have a lower portion and a substantially trapezoidal shaped upper portion.
摘要翻译：提供了存储器件和制造方法。存储器件包括设置在半导体衬底上的半导体衬底和电荷俘获介质堆叠。栅电极设置在电荷捕获电介质堆叠之上，其中栅极电极限定半导体衬底的一部分内的沟道。存储器件包括一对位线，其中位线具有下部分和基本上梯形的上部部分。

6. 发明授权

US08125018B2 Memory device having trapezoidal bitlines and method of fabricating same 有权
标题翻译：具有梯形位线的存储器件及其制造方法
公开(公告)号：US08125018B2
公开(公告)日：2012-02-28
申请号：US11033588
申请日：2005-01-12
申请人： Ashot Melik-Martirosian , Mark T. Ramsbey , Mark W. Randolph
发明人： Ashot Melik-Martirosian , Mark T. Ramsbey , Mark W. Randolph
IPC分类号： H01L29/792
CPC分类号： H01L29/7923 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of bitlines, where the bitlines have a lower portion and a substantially trapezoidal shaped upper portion.
摘要翻译：提供了存储器件和制造方法。存储器件包括设置在半导体衬底上的半导体衬底和电荷俘获介质堆叠。栅电极设置在电荷捕获电介质堆叠之上，其中栅极电极限定半导体衬底的一部分内的沟道。存储器件包括一对位线，其中位线具有下部分和基本上梯形的上部部分。

7. 发明授权

US06958272B2 Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell 有权
标题翻译：袖珍种植体用于SONOS存储器单元的互补位干扰改进和充电改进
公开(公告)号：US06958272B2
公开(公告)日：2005-10-25
申请号：US10755740
申请日：2004-01-12
申请人： Emmanuil H. Lingunis , Nga-Ching Alan Wong , Sameer Haddad , Mark W. Randolph , Mark T. Ramsbey , Ashot Melik-Martirosian , Edward F. Runnion , Yi He
发明人： Emmanuil H. Lingunis , Nga-Ching Alan Wong , Sameer Haddad , Mark W. Randolph , Mark T. Ramsbey , Ashot Melik-Martirosian , Edward F. Runnion , Yi He
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8234 , H01L21/8246 , H01L27/115 , H01L29/10 , H01L29/792
CPC分类号： H01L27/11568 , H01L21/26586 , H01L27/115 , H01L29/1083 , H01L29/66833 , Y10S438/959
摘要： A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer is formed over a substrate and a resist is formed over the portion of the charge trapping dielectric layer. The resist is patterned and a pocket implant is performed at an angle to establish pocket implants within the substrate. A bitline implant is then performed to establish buried bitlines within the substrate. The patterned resist is then removed and the remainder of the charge trapping dielectric layer is formed. A wordline material is formed over the remainder of the charge trapping dielectric layer and patterned to form wordlines that overlie the bitlines. The pocket implants serve to mitigate, among other things, complementary bit disturb (CBD) that can result from semiconductor scaling. As such, semiconductor devices can be made smaller and increased packing densities can be achieved by virtue of the inventive concepts set forth herein.
摘要翻译：公开了一种用于形成双位存储器核心的阵列的至少一部分的技术。最初，电荷俘获电介质层的一部分形成在衬底上，并且在电荷俘获电介质层的部分上形成抗蚀剂。抗蚀剂被图案化，并且以一定角度执行凹穴注入以在衬底内建立口袋植入物。然后执行位线注入以在衬底内建立掩埋位线。然后去除图案化的抗蚀剂，并形成剩余的电荷捕获介电层。在剩余的电荷俘获电介质层中形成字线材料，并且被图案化以形成覆盖在位线上的字线。口袋种植体用于缓解由半导体尺度缩小引起的互补位干扰（CBD）。因此，可以使半导体器件更小，并且可以通过本文所阐述的发明概念来实现增加的封装密度。

8. 发明申请

US20120122285A1 MEMORY DEVICE HAVING TRAPEZOIDAL BITLINES AND METHOD FO FABRICATING SAME 有权
标题翻译：具有铁氰酸钾的存储器件及其制造方法
公开(公告)号：US20120122285A1
公开(公告)日：2012-05-17
申请号：US13357252
申请日：2012-01-24
申请人： Ashot Melik-Martirosian , Mark T. Ramsbey , Mark W. Randolph
发明人： Ashot Melik-Martirosian , Mark T. Ramsbey , Mark W. Randolph
IPC分类号： H01L21/336
CPC分类号： H01L29/7923 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of bitlines, where the bitlines have a lower portion and a substantially trapezoidal shaped upper portion.
摘要翻译：提供了存储器件和制造方法。存储器件包括设置在半导体衬底上的半导体衬底和电荷俘获介质堆叠。栅电极设置在电荷捕获电介质堆叠之上，其中栅极电极限定半导体衬底的一部分内的沟道。存储器件包括一对位线，其中位线具有下部分和基本上梯形的上部部分。

9. 发明授权

US08656256B2 Apparatus and method for multi-mode operation of a flash memory device 有权
标题翻译：闪存器件的多模式操作的装置和方法
公开(公告)号：US08656256B2
公开(公告)日：2014-02-18
申请号：US13177482
申请日：2011-07-06
申请人： Anthony D. Weathers , Richard D. Barndt , Ashot Melik-Martirosian
发明人： Anthony D. Weathers , Richard D. Barndt , Ashot Melik-Martirosian
IPC分类号： G11C29/00 , G06F13/00 , G06F13/28 , G11C11/34 , G11C16/06 , G11C7/00
CPC分类号： G06F11/1072 , G11C11/5621 , G11C16/10 , G11C16/34 , G11C29/44 , G11C29/52 , G11C2029/0409 , G11C2029/0411 , G11C2029/4402 , G11C2211/5641 , H03M13/03
摘要： Disclosed is an apparatus and method for operating a multi-level cell (MLC) flash memory circuit. Data is read from a memory block of a plurality of memory blocks in the MLC flash memory circuit, wherein each of the plurality of memory blocks can operate in one of at least three modes of operation comprising an MLC mode, a single-level cell (SLC) mode and a defective mode, and wherein the memory block is initially operating in the MLC mode. Error correction is performed on the read data to correct read errors in the read data. A determination is made if a number of bits corrected by the error correction exceeds a predetermined threshold value. If the number of bits corrected by the error correction exceeds the predetermined threshold value, the operating mode of the memory block is switched from the MLC mode to the SLC mode.
摘要翻译：公开了一种用于操作多电平单元（MLC）闪速存储器电路的装置和方法。从MLC闪速存储器电路中的多个存储器块的存储器块读取数据，其中多个存储器块中的每一个可以在至少三种操作模式中的一种操作，包括MLC模式，单级单元（ SLC）模式和缺陷模式，并且其中存储块最初在MLC模式下操作。对读取的数据进行错误校正，以纠正读取数据中的读取错误。如果通过纠错校正的位数超过预定阈值，则确定。如果通过纠错校正的比特数超过预定阈值，则将存储块的操作模式从MLC模式切换到SLC模式。

10. 发明授权

US08644099B2 Apparatus and method for determining a read level of a flash memory after an inactive period of time 有权
标题翻译：用于在非活动时间段之后确定闪速存储器的读取电平的装置和方法
公开(公告)号：US08644099B2
公开(公告)日：2014-02-04
申请号：US13179466
申请日：2011-07-08
申请人： Aldo G. Cometti , Lun Bin Huang , Ashot Melik-Martirosian
发明人： Aldo G. Cometti , Lun Bin Huang , Ashot Melik-Martirosian
IPC分类号： G11C7/00
CPC分类号： G11C16/26 , G11C11/5628 , G11C11/5642 , G11C16/10
摘要： Disclosed is an apparatus and method for determining a dwell time in a non-volatile memory circuit after a shutdown of the memory circuit. A voltage shift is calculated by comparing a first read level voltage required to read a test block stored before the shutdown and a second read level voltage required to read a second test block stored after the shutdown. A shutdown time is determined from a look up table indexed by the voltage shift and a number of program/erase cycles. The dwell time is calculated as a function of the drive temperature, a clock, and a block time stamp. Once the dwell time is calculated, a controller calculates a new read level voltage based, in part, on the dwell time and provides one or more programming commands representative of the new read level voltage to the memory circuit to read the memory circuit.
摘要翻译：公开了一种用于在存储器电路关闭之后确定非易失性存储器电路中的驻留时间的装置和方法。通过比较读取在关闭之前存储的测试块所需的第一读取电平电压和读取关闭后存储的第二测试块所需的第二读取电平电平来计算电压偏移。从由电压偏移索引的查找表和编程/擦除周期数确定停机时间。停留时间是根据驱动器温度，时钟和块时间戳计算的。一旦计算了停留时间，控制器就部分地基于驻留时间计算新的读取电平电压，并且向存储器电路提供表示新的读取电平电压的一个或多个编程命令以读取存储器电路。

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