专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US07459743B2 Dual port gain cell with side and top gated read transistor 有权
标题翻译：双端口增益单元，具有侧和顶栅控读取晶体管
公开(公告)号：US07459743B2
公开(公告)日：2008-12-02
申请号：US11161962
申请日：2005-08-24
申请人： Jack A. Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Geng Wang
发明人： Jack A. Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Geng Wang
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译：使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。各种增益单元布局在本领域中是已知的。本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

22. 发明授权

US06693041B2 Self-aligned STI for narrow trenches 失效
标题翻译：用于窄沟槽的自对准STI
公开(公告)号：US06693041B2
公开(公告)日：2004-02-17
申请号：US09885790
申请日：2001-06-20
申请人： Ramachandra Divakaruni , Jack A. Mandelman , Carl J. Radens
发明人： Ramachandra Divakaruni , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L21311
CPC分类号： H01L27/10867 , H01L21/76232 , H01L21/76235 , H01L27/0207 , H01L27/10864
摘要： A self-aligned shallow trench isolation region for a memory cell array is formed by etching a plurality of vertical deep trenches in a substrate and coating the trenches with an oxidation barrier layer. The oxidation barrier layer is recessed in portions of the trenches to expose portions of the substrate in the trenches. The exposed portions of the substrate are merged by oxidization into thermal oxide regions to form the self-aligned shallow trench isolation structure which isolates adjacent portions of substrate material. The merged oxide regions are self-aligned as they automatically aligned to the edges of the deep trenches when merged together to define the location of the isolation region within the memory cell array during IC fabrication. The instant self-aligned shallow trench isolation structure avoids the need for an isolation mask to separate or isolate the plurality of trenches within adjacent active area rows on a single substrate.
摘要翻译：通过蚀刻衬底中的多个垂直深沟槽并用氧化阻挡层涂覆沟槽，形成用于存储单元阵列的自对准浅沟槽隔离区。氧化阻挡层凹陷在沟槽的部分中以暴露沟槽中的衬底的部分。衬底的暴露部分通过氧化合并成热氧化物区域，以形成隔离衬底材料的相邻部分的自对准浅沟槽隔离结构。合并的氧化物区域是自对准的，因为它们在合成时自动对准深沟槽的边缘，以在IC制造期间限定存储单元阵列内的隔离区域的位置。瞬时自对准浅沟槽隔离结构避免了需要隔离掩模以在单个衬底上的相邻有效区域行内分离或隔离多个沟槽。

23. 发明授权

US06426526B1 Single sided buried strap 失效
标题翻译：单面埋地带
公开(公告)号：US06426526B1
公开(公告)日：2002-07-30
申请号：US09870068
申请日：2001-05-30
申请人： Ramachandra Divakaruni , Jack A. Mandelman , Gary B. Bronner , Carl J. Radens
发明人： Ramachandra Divakaruni , Jack A. Mandelman , Gary B. Bronner , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10864
摘要： An easily manufactured connecting structure from a node conductor of trench capacitor device is characterized at least in part by the presence of an isolation collar located above the node conductor, at least a portion of the collar having an exterior surface which is substantially conformal with at least a portion of an adjacent wall of the trench, a buried strap region in the trench above the node conductor, the strap region being bounded laterally by the isolation collar except at an opening in the collar. The connecting structure is preferably formed by a method involving clearing an isolation collar from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench.
摘要翻译：至少部分地由位于节点导体上方的隔离套管的存在而将来自沟槽电容器装置的节点导体的容易制造的连接结构的特征在于，所述套环的至少一部分具有至少基本上保形的外表面沟槽的相邻壁的一部分，在节点导体上方的沟槽中的掩埋带区域，除了在套环的开口处之外，带区域被隔离套环侧向限定。连接结构优选地通过一种方法来形成，该方法包括在存储电容器上方的位置处从深沟槽的第一内表面清除隔离套环，同时将隔离套环留在深沟槽的其他表面。

24. 发明授权

US06376324B1 Collar process for reduced deep trench edge bias 失效
标题翻译：用于减小深沟槽边缘偏置的套圈过程
公开(公告)号：US06376324B1
公开(公告)日：2002-04-23
申请号：US09602969
申请日：2000-06-23
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Ulrike Gruening , Akira Sudo
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Ulrike Gruening , Akira Sudo
IPC分类号： H01L2120
CPC分类号： H01L27/10867
摘要： Disclosed is a method to provide a new deep trench collar process which reduces encroachment of strap diffusion upon array metal oxide semiconductor field effect transistors (MOSFET's) in semiconductor devices. The invention allows a reduced effective deep trench edge bias at the top of the deep trench, without compromising storage capacitance, by maximizing the distance between the MOSFET gate conductor and the deep trench storage capacitor.
摘要翻译：公开了一种提供新的深沟槽套环工艺的方法，其减少了半导体器件中的阵列金属氧化物半导体场效应晶体管（MOSFET）上带扩散的侵入。通过使MOSFET栅极导体和深沟槽存储电容器之间的距离最大化，本发明允许在深沟槽顶部减少有效的深沟槽边缘偏压，而不损害存储电容。

25. 发明授权

US06348374B1 Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structure 失效
标题翻译：具有垂直MOSFET和埋地位线导体结构的4F2 STC电池的工艺
公开(公告)号：US06348374B1
公开(公告)日：2002-02-19
申请号：US09597887
申请日：2000-06-19
申请人： Satish D. Athavale , Gary B. Bronner , Ramachandra Divakaruni , Ulrike Gruening , Jack A. Mandelman , Carl J. Radens
发明人： Satish D. Athavale , Gary B. Bronner , Ramachandra Divakaruni , Ulrike Gruening , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L218242
CPC分类号： H01L27/10876 , H01L27/10814 , H01L27/10823 , H01L27/10885
摘要： A method of forming a vertical transistor. A pad layer is formed over a semiconductor substrate. A trough is formed through the pad layer and in the semiconductor substrate. A bit line is formed buried in the trough. The bit line is enclosed by a dielectric material. A strap is formed extending through the dielectric material to connect the bit line to the semiconductor substrate. The trough is filled above the bit line with a conductor. The conductor is cut along its longitudinal axis such that the conductor remains on one side of the trough. Wordline troughs are formed, substantially orthogonal to the bit line, above the semiconductor substrate. A portion of the conductor is removed under the wordline trough to separate the conductor into separate gate conductors. Wordlines are formed in the wordline trough connected to the separate gate conductors.
摘要翻译：一种形成垂直晶体管的方法。在半导体衬底上形成衬垫层。通过焊盘层和半导体衬底形成槽。埋在槽中的位线形成。位线被电介质材料包围。形成延伸穿过介电材料的带，以将位线连接到半导体衬底。槽被填充在位线上方的导体。导体沿其纵向轴线切割，使得导体保持在槽的一侧。在半导体衬底之上形成基本上与位线正交的字线槽。导体的一部分在字线槽下移除，以将导体分离成单独的栅极导体。字线形成在连接到单独的栅极导体的字线槽中。

26. 发明授权

US06150212A Shallow trench isolation method utilizing combination of spacer and fill 失效
标题翻译：使用间隔物和填充物的组合的浅沟槽隔离方法
公开(公告)号：US06150212A
公开(公告)日：2000-11-21
申请号：US359287
申请日：1999-07-22
申请人： Ramachandra Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman , Carl J. Radens , William R. Tonti
发明人： Ramachandra Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman , Carl J. Radens , William R. Tonti
IPC分类号： H01L21/762 , H01L21/8242
CPC分类号： H01L21/76232 , H01L27/10861 , H01L27/1087
摘要： A method for forming an isolation trench region in a semiconductor substrate includes providing the trench region in the semiconductor substrate, adding spacer material at least to sidewalls of the trench region, and etching the trench region at a bottom surface thereof to extend the trench region below the bottom surface and form a crevice region. The spacer material may be subsequently heated such that the spacer material flows from the sidewalls and into the crevice region.
摘要翻译：一种用于在半导体衬底中形成隔离沟槽区域的方法包括：在半导体衬底中设置沟槽区域，至少在沟槽区域的侧壁上添加衬垫材料，并在其底表面处蚀刻沟槽区域，以将沟槽区域延伸到下面底面并形成缝隙区域。间隔物材料可以随后被加热，使得间隔物材料从侧壁流入缝隙区域。

27. 发明授权

US07759188B2 Method of fabricating vertical body-contacted SOI transistor 失效
标题翻译：垂直体接触SOI晶体管的制造方法
公开(公告)号：US07759188B2
公开(公告)日：2010-07-20
申请号：US12002828
申请日：2007-12-19
申请人： Kangguo Cheng , Gary B. Bronner , Ramachandra Divakaruni , Carl J. Radens
发明人： Kangguo Cheng , Gary B. Bronner , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/66666 , H01L29/78642
摘要： A method of fabricating a vertical field effect transistor (“FET”) is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator (“SOI”) region of a substrate adjacent a sidewall of a trench. The substrate includes a buried insulator layer underlying the SOI region and a bulk region underlying the buried insulator layer. A buried strap conductively connects the SOI region to a lower node disposed below the SOI region and a body contact extends from the transistor body region to the bulk region of the substrate, the body contact being insulated from the buried strap.
摘要翻译：提供一种制造垂直场效应晶体管（“FET”）的方法，其包括晶体管本体区域和设置在邻近侧壁的衬底的单晶半导体绝缘体（“SOI”）区域中的源极和漏极区域的沟渠衬底包括在SOI区域下面的掩埋绝缘体层和埋在掩埋绝缘体层下面的主体区域。掩埋带导电地将SOI区域连接到设置在SOI区域下方的下部节点，并且主体接触从晶体管本体区域延伸到衬底的主体区域，身体接触部与掩埋带绝缘。

28. 发明授权

US07737482B2 Self-aligned strap for embedded trench memory on hybrid orientation substrate 失效
标题翻译：用于混合取向基板上嵌入式沟槽存储器的自对准带
公开(公告)号：US07737482B2
公开(公告)日：2010-06-15
申请号：US11538982
申请日：2006-10-05
申请人： Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens
发明人： Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L29/76
CPC分类号： H01L27/1203 , H01L21/743 , H01L21/84 , H01L27/10829 , H01L27/10867 , H01L27/1087 , H01L27/1207 , H01L29/78
摘要： Structures including a self-aligned strap for embedded trench memory (e.g., trench capacitor) on hybrid orientation technology (HOT) substrate, and related method, are disclosed. One structure includes a hybrid orientation substrate including a semiconductor-on-insulator (SOI) section and a bulk semiconductor section; a transistor over the SOI section; a trench capacitor in the bulk semiconductor section; and a self-aligned strap extending from a source/drain region of the transistor to an electrode of the trench capacitor. The method does not require additional masks to generate the strap, results in a self-aligned strap and improved device performance. In one embodiment, the strap is a silicide strap.
摘要翻译：公开了包括用于混合取向技术（HOT）衬底上的嵌入式沟槽存储器（例如，沟槽电容器）的自对准带的结构以及相关方法。一种结构包括：包含绝缘体上半导体（SOI）部分和体半导体部分的混合取向衬底; SOI部分上的晶体管; 体半导体部分中的沟槽电容器; 以及从晶体管的源极/漏极区域延伸到沟槽电容器的电极的自对准带。该方法不需要额外的掩模来生成带，导致自对准带和改进的设备性能。在一个实施例中，带是硅化物带。

29. 发明授权

US07439559B2 SOI device with different crystallographic orientations 有权
标题翻译：具有不同晶体取向的SOI器件
公开(公告)号：US07439559B2
公开(公告)日：2008-10-21
申请号：US11469039
申请日：2006-08-31
申请人： Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens
发明人： Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L29/74
CPC分类号： H01L29/78642 , H01L27/10864 , H01L27/1087
摘要： A method of forming a memory cell having a trench capacitor and a vertical transistor in a semiconductor substrate includes a step of providing a bonded semiconductor wafer having a lower substrate with an [010] axis parallel to a first wafer axis and an upper semiconductor layer having an [010] axis oriented at forty-five degrees with respect to the wafer axis, the two being connected by a layer of bonding insulator; etching a trench through the upper layer and lower substrate; enlarging the lower portion of the trench and converting the cross section of the upper portion of the trench from octagonal to rectangular, so that sensitivity to alignment errors between the trench lithography and the active area lithography is reduced. An alternative version employs a bonded semiconductor wafer having a lower substrate formed from a (111) crystal structure and the same upper portion. Applications include a vertical transistor that becomes insensitive to misalignment between the trench and the lithographic pattern for the active area, in particular a DRAM cell with a vertical transistor.
摘要翻译：在半导体衬底中形成具有沟槽电容器和垂直晶体管的存储单元的方法包括提供具有平行于第一晶片轴的[010]轴的下基板的接合半导体晶片的步骤，以及具有相对于晶片轴线定向成四十五度的[010]轴，两者通过一层粘合绝缘体连接; 蚀刻通过上层和下衬底的沟槽; 扩大沟槽的下部并将沟槽的上部的横截面从八边形转换为矩形，从而降低对沟槽光刻和有源区光刻之间对准误差的敏感性。替代方案采用具有由（111）晶体结构和相同上部形成的下基板的键合半导体晶片。应用包括对于有源区域，特别是具有垂直晶体管的DRAM单元对沟槽和光刻图案之间的未对准变得不敏感的垂直晶体管。

30. 发明申请

US20080083941A1 SELF-ALIGNED STRAP FOR EMBEDDED TRENCH MEMORY ON HYBRID ORIENTATION SUBSTRATE 失效
标题翻译：用于混合定向衬底上嵌入式TRENCH存储器的自对准层
公开(公告)号：US20080083941A1
公开(公告)日：2008-04-10
申请号：US11538982
申请日：2006-10-05
申请人： Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens
发明人： Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L29/94
CPC分类号： H01L27/1203 , H01L21/743 , H01L21/84 , H01L27/10829 , H01L27/10867 , H01L27/1087 , H01L27/1207 , H01L29/78
摘要： Structures including a self-aligned strap for embedded trench memory (e.g., trench capacitor) on hybrid orientation technology (HOT) substrate, and related method, are disclosed. One structure includes a hybrid orientation substrate including a semiconductor-on-insulator (SOI) section and a bulk semiconductor section; a transistor over the SOI section; a trench capacitor in the bulk semiconductor section; and a self-aligned strap extending from a source/drain region of the transistor to an electrode of the trench capacitor. The method does not require additional masks to generate the strap, results in a self-aligned strap and improved device performance. In one embodiment, the strap is a silicide strap.
摘要翻译：公开了包括用于混合取向技术（HOT）衬底上的嵌入式沟槽存储器（例如，沟槽电容器）的自对准带的结构以及相关方法。一种结构包括：包含绝缘体上半导体（SOI）部分和体半导体部分的混合取向衬底; SOI部分上的晶体管; 体半导体部分中的沟槽电容器; 以及从晶体管的源极/漏极区域延伸到沟槽电容器的电极的自对准带。该方法不需要额外的掩模来生成带，导致自对准带和改进的设备性能。在一个实施例中，带是硅化物带。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式