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21. 发明授权

US10275242B2 System and method for real time instruction tracing 有权
公开(公告)号：US10275242B2
公开(公告)日：2019-04-30
申请号：US13997016
申请日：2012-03-30
申请人： Huy V. Nguyen , Jason W. Brandt , Jonathan J. Tyler
发明人： Huy V. Nguyen , Jason W. Brandt , Jonathan J. Tyler
IPC分类号： G06F9/30 , G06F11/34 , G06F11/36
摘要： An apparatus and method are described for real time instruction tracing. For example, a method according to one embodiment comprises: recording user specified address ranges for which tracing is required; monitoring a next linear instruction pointer (NLIP) values and/or branch linear instruction pointer (BLIP) values to determine if address range has been entered; when the range is entered, compressing the NLIP and/or BLIP values and constructing fixed length packets containing the tracing data; and transferring the fixed length packets to a memory execution cluster.

22. 发明授权

US09703566B2 Sharing TLB mappings between contexts 有权
公开(公告)号：US09703566B2
公开(公告)日：2017-07-11
申请号：US13997789
申请日：2011-12-29
申请人： Jonathan D. Combs , Jason W. Brandt , Benjamin C. Chaffin , Julio Gago
发明人： Jonathan D. Combs , Jason W. Brandt , Benjamin C. Chaffin , Julio Gago , Andrew F. Glew
IPC分类号： G06F12/00 , G06F9/38 , G06F12/1036
CPC分类号： G06F9/3814 , G06F9/3851 , G06F12/0842 , G06F12/1036 , G06F2212/1024 , G06F2212/657
摘要： In some implementations, a processor may include a data structure, such as a translation lookaside buffer, that includes an entry containing first mapping information having a virtual address and a first context associated with a first thread. Control logic may receive a request for second mapping information having the virtual address and a second context associated with a second thread. The control logic may determine whether the second mapping information associated with the second context is equivalent to the first mapping information in the entry of the data structure. If the second mapping information is equivalent to the first mapping information, the control logic may associate the second thread with the first mapping information contained in the entry of the data structure to share the entry between the first thread and the second thread.

23. 发明授权

US09323533B2 Supervisor mode execution protection 有权
标题翻译：主管模式执行保护
公开(公告)号：US09323533B2
公开(公告)日：2016-04-26
申请号：US13997857
申请日：2011-12-29
申请人： Adriaan Van De Ven , Baiju V. Patel , Asit K. Mallick , Gilbert Neiger , James S. Coke , Martin G. Dixon , Jason W. Brandt
发明人： Adriaan Van De Ven , Baiju V. Patel , Asit K. Mallick , Gilbert Neiger , James S. Coke , Martin G. Dixon , Jason W. Brandt
IPC分类号： G06F21/00 , H04L29/06 , G06F9/30 , G06F12/02 , G06F12/10 , G06F12/14 , G06F9/455 , G06F17/28
CPC分类号： G06F9/30189 , G06F9/30043 , G06F12/0292 , G06F12/1009 , G06F12/1491
摘要： Apparatuses and methods for supervisor mode execution protection are disclosed. In one embodiment, a processor includes an interface to access a memory, execution hardware, and control logic. A region in the memory is user memory. The execution hardware is to execute an instruction. The control logic is to prevent the execution hardware from executing the instruction when the instruction is stored in user memory and the processor is in supervisor mode.
摘要翻译：公开了用于监督模式执行保护的装置和方法。在一个实施例中，处理器包括访问存储器，执行硬件和控制逻辑的接口。存储器中的区域是用户存储器。执行硬件是执行指令。当指令存储在用户存储器中并且处理器处于主管模式时，控制逻辑是防止执行硬件执行指令。

24. 发明授权

US09189360B2 Processor that records tracing data in non contiguous system memory slices 有权
标题翻译：在不连续的系统内存片中记录跟踪数据的处理器
公开(公告)号：US09189360B2
公开(公告)日：2015-11-17
申请号：US13918940
申请日：2013-06-15
申请人： Beeman C. Strong , Jason W. Brandt , Tsvika Kurts , Peter Lachner , Itamar Kazachinsky , Stephen J. Robinson , Peggy J. Irelan
发明人： Beeman C. Strong , Jason W. Brandt , Tsvika Kurts , Peter Lachner , Itamar Kazachinsky , Stephen J. Robinson , Peggy J. Irelan
IPC分类号： G06F12/00 , G06F11/34 , G06F11/36 , G06F11/32 , G06F12/02 , G06F12/06
CPC分类号： G06F11/34 , G06F9/30 , G06F11/323 , G06F11/3466 , G06F11/3476 , G06F11/3636 , G06F11/3664 , G06F11/3668 , G06F12/023 , G06F12/06
摘要： A method is described that involves referring to first information from a directory table in system memory. The first information includes location information and size information of a first slice of system memory where first tracing data is to be stored. The method also includes tracking the amount of tracing data stored in the first slice of system memory and comparing the amount against the size information. The method also includes, before the first slice of system memory is filled, referring to second information from the directory table in system memory, where, the second information includes location information and size information of a second slice of system memory where second tracing data is to be stored. The first slice is not contiguous with the second slice of system memory.
摘要翻译：描述了涉及从系统存储器中的目录表引用第一信息的方法。第一信息包括要存储第一跟踪数据的系统存储器的第一片段的位置信息和大小信息。该方法还包括跟踪存储在系统存储器的第一片中的跟踪数据量，并将该量与尺寸信息进行比较。该方法还包括在系统存储器的第一片填充之前，参考来自系统存储器中的目录表的第二信息，其中第二信息包括系统存储器的第二片的位置信息和大小信息，其中第二追踪数据是被存储。第一个片段与系统内存的第二个片段不连续。

25. 发明授权

US09003375B2 Optional logging of debug activities in a real time instruction tracing log 有权
标题翻译：在实时指令跟踪日志中选择性地记录调试活动
公开(公告)号：US09003375B2
公开(公告)日：2015-04-07
申请号：US13993477
申请日：2011-12-30
申请人： Jason W. Brandt , Peter Lachner , Huy V. Nguyen , Jonathan J. Tyler
发明人： Jason W. Brandt , Peter Lachner , Huy V. Nguyen , Jonathan J. Tyler
IPC分类号： G06F11/36 , G06F9/44 , G06F11/34 , G06F9/06 , G06F9/30
CPC分类号： G06F11/3466 , G06F9/06 , G06F9/30 , G06F11/34 , G06F11/3476 , G06F11/3495 , G06F11/36 , G06F11/3636 , G06F2201/805
摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing optional logging of debug activities in a real time instruction tracing log. For example, in one embodiment, such means may include an integrated circuit having means for initiating instruction tracing for instructions of a traced application, mode, or code region, as the instructions are executed by the integrated circuit; means for generating a plurality of packets to a debug log describing the instruction tracing; means for initiating an alternative mode of execution within the integrated circuit; and means for suppressing indication of entering the alternative mode of execution. Additional and alternative means may be implemented for selectively causing an integrated circuit to operate in accordance with an invisible trace mode or a visible trace mode upon transition to the alternative mode of execution.
摘要翻译：根据本文公开的实施例，提供了用于在实时指令跟踪日志中实现可选日志记录调试活动的方法，系统，机制，技术和装置。例如，在一个实施例中，这种装置可以包括集成电路，该集成电路具有用于对由跟踪的应用，模式或代码区域的指令进行指令跟踪的装置，因为该指令由集成电路执行; 用于将多个分组生成到描述所述指令跟踪的调试日志的装置; 用于在集成电路内启动替代执行模式的装置; 以及用于抑制进入替代执行模式的指示的装置。可以实现附加和替代手段，用于在转换到替代执行模式时，根据不可见的跟踪模式或可视跟踪模式选择性地使集成电路进行操作。

26. 发明申请

US20150095614A1 APPARATUS AND METHOD FOR EFFICIENT MIGRATION OF ARCHITECTURAL STATE BETWEEN PROCESSOR CORES 审中-公开
标题翻译：处理器之间建筑状态有效迁移的装置和方法
公开(公告)号：US20150095614A1
公开(公告)日：2015-04-02
申请号：US14040230
申请日：2013-09-27
申请人： Bret L. Toll , Scott D. Hahn , Jason W. Brandt , Thomas F. Toll
发明人： Bret L. Toll , Scott D. Hahn , Jason W. Brandt , Thomas F. Toll
IPC分类号： G06F9/38
CPC分类号： G06F9/3824 , G06F9/3851 , G06F9/4856
摘要： An apparatus and method are described for the efficient migration of architectural state between processor cores. For example, a processor according to one embodiment comprises: a first processing core having a first instruction execution pipeline including first register set for storing a first architectural state of a first thread being executed thereon; a second processing core having a second instruction execution pipeline including a second register set for storing a second architectural state of a second thread being executed thereon; and architectural state migration logic to perform a direct, simultaneous swap of the first architectural state from the first register set with the second architectural state from the second register set responsive to detecting that the execution of the first thread is to be migrated from the first core to the second core.
摘要翻译：描述了用于处理器核心之间架构状态的有效迁移的装置和方法。例如，根据一个实施例的处理器包括：具有第一指令执行流水线的第一处理核心，第一指令执行流水线包括用于存储在其上执行的第一线程的第一架构状态的第一寄存器集; 第二处理核心，具有第二指令执行流水线，该第二指令执行流水线包括第二寄存器组，用于存储在其上执行的第二线程的第二架构状态; 以及体系结构状态迁移逻辑，用于响应于检测到要从第一核心迁移第一线程的执行，执行来自第二架构状态的第一寄存器与第二寄存器集的第一架构状态的直接同时交换到第二个核心。

27. 发明申请

US20140281457A1 METHOD FOR BOOTING A HETEROGENEOUS SYSTEM AND PRESENTING A SYMMETRIC CORE VIEW 有权
标题翻译：用于打造异质系统并提供对称核心视图的方法
公开(公告)号：US20140281457A1
公开(公告)日：2014-09-18
申请号：US13854001
申请日：2013-03-29
申请人： Elierzer Weissmann , Rinat Rappoport , Michael Mishaeli , Hisham Shafi , Oron Lenz , Jason W. Brandt , Stephen A. Fischer , Bret L. Toll , Inder M. Sodhi , Alon Naveh , Ganapati N. Srinivasa , Ashish V. Choubal , Scott D. Hahn , David A. Koufaty , Russel J. Fenger , Gaurav Khanna , Eugene Gorbatov , Mishali Naik , Andrew J. Herdrich , Abirami Prabhakaran , Sanjeev S. Sahagirdar , Paul Brett , Paolo Narvaez , Andrew D. Henroid , Dheeraj R. Subbareddy
发明人： Elierzer Weissmann , Rinat Rappoport , Michael Mishaeli , Hisham Shafi , Oron Lenz , Jason W. Brandt , Stephen A. Fischer , Bret L. Toll , Inder M. Sodhi , Alon Naveh , Ganapati N. Srinivasa , Ashish V. Choubal , Scott D. Hahn , David A. Koufaty , Russel J. Fenger , Gaurav Khanna , Eugene Gorbatov , Mishali Naik , Andrew J. Herdrich , Abirami Prabhakaran , Sanjeev S. Sahagirdar , Paul Brett , Paolo Narvaez , Andrew D. Henroid , Dheeraj R. Subbareddy
IPC分类号： G06F9/44
CPC分类号： G06F9/4401 , G06F9/45558 , G06F9/5077 , G06F9/5094 , Y02D10/22 , Y02D10/36
摘要： A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.
摘要翻译：描述异构处理器架构和启动异构处理器的方法。根据一个实施例的处理器包括：一组大的物理处理器核心; 一组具有相对较低性能处理能力的小物理处理器核和相对于大型物理处理器核的相对较低的功率使用; 以及一个包装单元，用于启用自举处理器。引导处理器初始化同构物理处理器内核，而异构处理器将均匀处理器的外观呈现给系统固件界面。

28. 发明申请

US20140281380A1 EXECUTION CONTEXT SWAP BETWEEN HETEROGENOUS FUNCTIONAL HARDWARE UNITS 有权
标题翻译：执行异构功能硬件单元之间的上下文交换
公开(公告)号：US20140281380A1
公开(公告)日：2014-09-18
申请号：US13795338
申请日：2013-03-12
申请人： Inder M. Sodhi , Marc Torrant , Zeev Offen , Michael Mishaeli , Ashish V. Choubal , Jason W. Brandt
发明人： Inder M. Sodhi , Marc Torrant , Zeev Offen , Michael Mishaeli , Ashish V. Choubal , Jason W. Brandt
IPC分类号： G06F15/76
CPC分类号： G06F9/30123 , G06F1/32 , G06F1/3243 , G06F1/3287 , G06F9/3836 , G06F9/461 , Y02D10/152 , Y02D10/171
摘要： Remapping technologies for execution context swap between heterogeneous functional hardware units are described. A computing system includes multiple registers configured to store remote contexts of functional units. A mapping table maps the remote context to the functional units. An execution unit is configured to execute a remapping tool that intercepts an operation to access a remote context of a first functional unit of the plurality of functional units that is taken offline. The remapping tool determines that the first functional unit is remapped to a second functional unit using the mapping table. The operation is performed to access the remote context that is remapped to the second functional unit. The first functional unit and the second functional unit may be heterogeneous functional units.
摘要翻译：描述用于异构功能硬件单元之间执行上下文交换的重新映射技术。计算系统包括配置成存储功能单元的远程上下文的多个寄存器。映射表将远程上下文映射到功能单元。执行单元被配置为执行重新映射工具，该重新映射工具拦截用于访问脱机的多个功能单元中的第一功能单元的远程上下文的操作。重新映射工具确定使用映射表将第一功能单元重新映射到第二功能单元。执行操作以访问被重新映射到第二功能单元的远程上下文。第一功能单元和第二功能单元可以是异构功能单元。

29. 发明申请

US20140157002A1 SYSTEMS AND METHODS FOR PROTECTING SYMMETRIC ENCRYPTION KEYS 有权
标题翻译：用于保护对称加密键的系统和方法
公开(公告)号：US20140157002A1
公开(公告)日：2014-06-05
申请号：US13996453
申请日：2011-12-21
申请人： Steven L. Grobman , Jason W. Brandt
发明人： Steven L. Grobman , Jason W. Brandt
IPC分类号： G06F21/60
CPC分类号： H04L9/0861 , G06F21/60 , H04L9/0631 , H04L9/0822 , H04L9/0877 , H04L2209/127 , H04L2209/24
摘要： Systems and methods for protecting symmetric encryption keys when performing encryption are described. In one embodiment, a computer-implemented method includes retrieving at least one real key from a secure area and executing, with a processor, a key transform instruction to generate at least one transformed key based on receiving the at least one real key. The at least one transformed key is an encrypted version of at least one round key that is encrypted by the processor using the at least one real key. The processor is able to decrypt the at least one transformed key and encrypt the at least one round key.
摘要翻译：描述在执行加密时保护对称加密密钥的系统和方法。在一个实施例中，计算机实现的方法包括从安全区域检索至少一个真实密钥，并且利用处理器执行密钥变换指令，以基于接收所述至少一个真实密钥来生成至少一个变换密钥。至少一个变换密钥是由处理器使用至少一个真实密钥加密的至少一个循环密钥的加密版本。处理器能够对至少一个变换的密钥进行解密并加密至少一个循环密钥。

30. 发明申请

US20130297915A1 FLAG NON-MODIFICATION EXTENSION FOR ISA INSTRUCTIONS USING PREFIXES 有权
标题翻译：标志使用前缀的ISA指令的非修改扩展
公开(公告)号：US20130297915A1
公开(公告)日：2013-11-07
申请号：US13976261
申请日：2011-11-14
申请人： Jonathan D. Combs , Jason W. Brandt , Robert Valentine
发明人： Jonathan D. Combs , Jason W. Brandt , Robert Valentine
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30094 , G06F9/30185
摘要： In one embodiment, a processor includes an instruction decoder to receive and decode an instruction having a prefix and an opcode, an execution unit to execute the instruction based on the opcode, and flag modification override logic to prevent the execution unit from modifying a flag register of the processor based on the prefix of the instruction.
摘要翻译：在一个实施例中，处理器包括用于接收和解码具有前缀和操作码的指令的指令解码器，基于操作码执行指令的执行单元和标志修改覆盖逻辑，以防止执行单元修改标志寄存器的处理器基于指令的前缀。

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