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    • 21. 发明专利
    • SELECTIVE ETCHING METHOD
    • JPH06260477A
    • 1994-09-16
    • JP7113793
    • 1993-03-05
    • NIPPON DENSO CO
    • SAKAKIBARA NOBUYOSHIMIZUNO NAOHITOFUJINO SEIJI
    • H01L21/306B81C1/00H01L21/268
    • PURPOSE:To perform etching of a high selection ratio at a room temperature by cooling a prescribed area of a material to be worked by making the area to react to a reactive solution after locally heating the prescribed area and again locally heating the prescribed area so that a reaction product can be scattered in the solution. CONSTITUTION:After an Si substrate 10 to be worked is set in a reactive solution, namely, pure water 20 in parallel with the surface of the water 20, a prescribed surface area 11 of the substrate 10 is irradiated with a converged pulsed laser beam 30. As a result, the surface temperature of the substrate 10 rises to about its melting point and an oxidative reaction takes place between the Si in the substrate 10 and water molecules, resulting in SiO2 12. After oxidizing the prescribed area, the substrate 10 is cooled. Then the oxidized part 12 is again irradiated with the pulsed laser beam 30 in the water 20. As a result, the SiO2 film 12 makes thermal expansion and the film 12 is stripped off from the substrate 10 and scattered in the water 20. When the stripping off and scattering process is repeated, etching can be performed at a high selection ratio.
    • 24. 发明专利
    • MANUFACTURE OF SEMICONDUCTOR DEVICE
    • JPH04293256A
    • 1992-10-16
    • JP5759091
    • 1991-03-22
    • NIPPON DENSO CO
    • KATAYAMA MASAYUKIOSHIMA HISAZUMISAKAKIBARA NOBUYOSHI
    • H01L23/522H01L21/768
    • PURPOSE:To form a multilayer interconnection structure by removing the insulating material on the surface of an underneath layer exposed in an interlayer connecting hole for filling the hole with a conductive material by simpler method. CONSTITUTION:An Si substrate 1 is coated with a layer insulating film 3 through the intermediary of a lower Al wiring layer 2 arranged on said substrate 1 to make a through hole 3a. Next, this substrate 1 is immersed in a hydrochloric acid solution to remove the insulating material 6 existing on the exposed surface of the lower Al wiring layer 2 in the through hole 3a in a uniform state. In such a state, hexafluorine tungsten is reduced using silane gas to selectively deposit the tungsten 4 in the through hole 3a. During the initial deposition process, the hydrogen contained in the fluorine and the reduced gas contained in a metallic material gas induces the chemical reaction to remove the insulation material 6 such as Al2O3 etc., deposited on said exposed surface. Finally, an upper Al wiring layer 5 is formed on the layer insulating film 3 so that a multilayer interconnection structure may be formed through the intermediary of the conductive material 4 deposited in the through hole 3a.
    • 27. 发明专利
    • SEMICONDUCTOR DEVICE
    • JPS6355942A
    • 1988-03-10
    • JP19970286
    • 1986-08-26
    • NIPPON DENSO CO
    • SAKAKIBARA TOSHIOFUJII TETSUOYAMANE HIROYUKISAKAKIBARA NOBUYOSHI
    • H01L21/316H01L21/318
    • PURPOSE:To prevent the eluation of phosphorus even in case a PSG film is used for an interlayer insulating film land to prevent an effect that is exerted on a Tr by contamination due to heavy metals by a method wherein first and second insulating films are formed in such a way as to envelop the interlayer insulating film holding the interlayer insulating film formed on the surface of a semiconductor between them. CONSTITUTION:An activated region 12, source and drain regions 13 and a field region 14 are formed in and on the surface part of an Si semiconductor substrate 11. A poly Si electrode 15 is formed in a state corresponding to the part of the region 12. A first insulating film 16 consisting of an Si nitride film and an interlayer insulating film 17 consisting of a PSG film are formed on the surface thereof. A second insulating film 18 consisting of an Si nitride film is laminated thereon, the film 18 is coupled integrally with the film 16 at the parts of contact holes 191 and 192 and the film 17 is enveloped with the films 16 and 18. A wiring metal layer 20 is formed in such a way as to connect with the poly Si electrode 15 and the region 13 at the parts of the contact holes 191 and 192 and a passivation film 21 is provided on the surface of the layer 20.