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    • 21. 发明授权
    • Modulation doped super-lattice base for heterojunction bipolar transistors
    • 用于异质结双极晶体管的调制掺杂超晶格基极
    • US08957455B1
    • 2015-02-17
    • US13438810
    • 2012-04-03
    • James Chingwei LiMarko SokolichTahir HussainDavid H. Chow
    • James Chingwei LiMarko SokolichTahir HussainDavid H. Chow
    • H01L29/737
    • H01L29/155H01L29/201H01L29/7373
    • A heterojunction bipolar transistor (HBT) having an emitter, a base, and a collector, the base including a first semiconductor layer coupled to the collector, the first semiconductor layer having a first bandgap between a first conduction band and a first valence band and a second semiconductor layer coupled to the first semiconductor layer and having a second bandgap between a second conduction band and a second valence band, wherein the second valence band is higher than the first valence band and wherein the second semiconductor layer comprises a two dimensional hole gas and a third semiconductor layer coupled to the second semiconductor layer and having a third bandgap between a third conduction band and a third valence band, wherein the third valence band is lower than the second valence band and wherein the third semiconductor layer is coupled to the emitter.
    • 具有发射极,基极和集电极的异质结双极晶体管(HBT),所述基极包括耦合到集电极的第一半导体层,所述第一半导体层在第一导带和第一价带之间具有第一带隙, 第二半导体层,其耦合到所述第一半导体层,并且在第二导带和第二价带之间具有第二带隙,其中所述第二价带高于所述第一价带,并且其中所述第二半导体层包括二维空穴气体, 耦合到所述第二半导体层并且在第三导带和第三价带之间具有第三带隙的第三半导体层,其中所述第三价带低于所述第二价带,并且其中所述第三半导体层耦合到所述发射极。
    • 25. 发明授权
    • Carbon-beryllium combinationally doped semiconductor
    • 碳铍组合掺杂半导体
    • US08575659B1
    • 2013-11-05
    • US13209395
    • 2011-08-13
    • Steven S. BuiTahir HussainJames Chingwei Li
    • Steven S. BuiTahir HussainJames Chingwei Li
    • H01L29/66H01L21/8249
    • H01L29/36H01L29/0826H01L29/1004H01L29/207H01L29/66242H01L29/7371
    • A combinationally doped semiconductor layer, a double heterojunction bipolar transistor (DHBT) including a combinationally doped semiconductor layer, and a method of making a combinationally doped semiconductor layer employ a combination of carbon and beryllium doping. The combinationally doped semiconductor layer includes a first sublayer of a semiconductor material doped substantially with beryllium and a second sublayer of the semiconductor material doped substantially with carbon. The DHBT includes a carbon-beryllium combinationally doped semiconductor layer as a base layer. The method of making a combinationally doped semiconductor layer includes growing a first sublayer of the semiconductor layer, the first sublayer being doped substantially with beryllium and growing a second sublayer of the semiconductor layer, the second sublayer being doped substantially with carbon.
    • 组合掺杂半导体层,包括组合掺杂半导体层的双异质结双极晶体管(DHBT)以及制造组合掺杂半导体层的方法采用碳和铍掺杂的组合。 组合掺杂的半导体层包括基本上掺杂有铍的半导体材料的第一子层和基本上掺杂碳的半导体材料的第二子层。 DHBT包括作为基底层的碳 - 铍组合掺杂半导体层。 制造组合掺杂半导体层的方法包括生长半导体层的第一子层,第一子层基本上掺杂有铍并生长半导体层的第二子层,第二子层基本上被碳掺杂。
    • 27. 发明授权
    • Method and apparatus for fabricating heterojunction bipolar transistors with simultaneous low base resistance and short base transit time
    • 用于制造具有同时低基极电阻和短基极传输时间的异质结双极晶体管的方法和装置
    • US07494887B1
    • 2009-02-24
    • US10920708
    • 2004-08-17
    • Tahir Hussain
    • Tahir Hussain
    • H01L21/331H01L21/20
    • H01L29/66318H01L29/7371
    • A method for fabricating heterojunction bipolar transistors that exhibit simultaneous low base resistance and short base transit times, which translate into semiconductor devices with low power consumption and fast switching times, is presented. The method comprises acts for fabricating a set of extrinsic layers by depositing a highly-doped p+ layer on a substrate, depositing a masking layer on highly-doped p+ layer, patterning the masking layer with a masking opening, removing a portion of the highly-doped p+ layer and the substrate through the masking opening in the masking layer to form a well, and growing an intrinsic layered device in the well by a combination of insitu etching and epitaxial regrowth, where an intrinsic layer has a thickness selected independently from a thickness of its corresponding extrinsic layer, thus allowing the resulting device to have thick extrinsic base layer (low base resistance) and thin intrinsic base layer (short base transit times) simultaneously.
    • 提出了一种制造异质结双极晶体管的方法,它们具有同时低的基极电阻和短的基极传输时间,从而转换成具有低功耗和快速切换时间的半导体器件。 该方法包括通过在衬底上沉积高度掺杂的p +层来制造一组非本征层的动作,在高度掺杂的p +层上沉积掩模层,用掩蔽开口对掩模层进行图案化, 掺杂的p +层和衬底通过掩模层中的掩模开口形成阱,并通过本征蚀刻和外延再生长的组合在阱中生长本征分层器件,其中本征层具有独立于厚度选择的厚度 ,从而允许所得到的器件同时具有厚的外在基极层(低基极电阻)和薄的本征基极层(短的基极传输时间)。