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21. 发明授权

US06807084B1 FeRAM memory device 失效
标题翻译： FeRAM存储器件
公开(公告)号：US06807084B1
公开(公告)日：2004-10-19
申请号：US10418734
申请日：2003-04-17
申请人： Joerg Wohlfahrt , Hans-Oliver Joachim
发明人： Joerg Wohlfahrt , Hans-Oliver Joachim
IPC分类号： G11C1122
CPC分类号： G11C11/22 , G11C7/20
摘要： A FeRAM memory chip comprises an array 5 of non-volatile ferrocapacitor memory cells for storing data. Input pins receive data to be stored, and address data indicating where in the array of memory cells the data should be stored. The FeRAM memory chip further has a reset unit 7 for recognizing an externally applied reset signal. The reset unit 7, upon recognition of the reset signal, initiates a reset operation in which at least a portion of the data stored in the memory cells is set to predetermined values.
摘要翻译：一个FeRAM存储器芯片包括用于存储数据的非易失性二元电容器存储器单元阵列5。输入引脚接收要存储的数据，以及指示存储单元数组中应存储数据的位置的地址数据。 FeRAM存储器芯片还具有用于识别外部施加的复位信号的复位单元7。复位单元7在识别到复位信号时启动复位操作，其中存储在存储单元中的数据的至少一部分被设置为预定值。

22. 发明授权

US06687150B1 Reference voltage generation for memory circuits 有权
标题翻译：存储电路的基准电压产生
公开(公告)号：US06687150B1
公开(公告)日：2004-02-03
申请号：US10064955
申请日：2002-09-04
申请人： Hans-Oliver Joachim , Takashima Daisaburo
发明人： Hans-Oliver Joachim , Takashima Daisaburo
IPC分类号： G11C1122
CPC分类号： G11C5/147 , G11C11/22 , G11C29/816
摘要： An improved reference voltage generation is described. In one embodiment, a memory block includes a plurality of memory cells interconnected by wordlines and bitlines. A plurality of reference cells are provided. A bitline includes a reference cell. The bitlines of the memory block are divided into groups or bitlines. The reference cells within a group are interconnected to average out the reference cell charge variation to improve the sensing window.
摘要翻译：描述了改进的参考电压产生。在一个实施例中，存储块包括通过字线和位线互连的多个存储器单元。提供多个参考单元。位线包括参考单元格。内存块的位线被分成组或位线。将组内的参考单元相互连接以平均参考细胞电荷变化以改善感测窗口。

23. 发明授权

US06265742B1 Memory cell structure and fabrication 失效
标题翻译：存储单元结构和制造
公开(公告)号：US06265742B1
公开(公告)日：2001-07-24
申请号：US09317662
申请日：1999-05-24
申请人： Ulrike Gruening , Jochen Beintner , Hans-Oliver Joachim
发明人： Ulrike Gruening , Jochen Beintner , Hans-Oliver Joachim
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A pair of memory cells for use in a DRAM are formed in a monocrystalline bulk portion of a silicon wafer by first forming a pair of vertical trenches spaced apart by a bulk portion of the wafer. After a dielectric layer is formed over the walls of each trench, the trenches are each filled with polycrystalline silicon. By a pair of recess forming and recess filling steps there is formed at the top of each trench a silicon region that was grown epitaxially with the intermediate bulk portion. Each epitaxial region is made to serve as the body of a separate transistor having its drain in the lower polysilicon fill of a trench, and its source in the monocrystalline bulk intermediate between the two epitaxial regions. The lower polysilicon fill of each trench is also made to serve as the storage node of the capacitor of each cell, with the bulk serving as the other plate of the capacitor.
摘要翻译：通过首先形成由晶片的主体部分隔开的一对垂直沟槽，在硅晶片的单晶体部分中形成用于DRAM中的一对存储单元。在每个沟槽的壁之上形成电介质层之后，沟槽各自填充有多晶硅。通过一对凹陷形成和凹陷填充步骤，在每个沟槽的顶部形成有与中间体部分外延生长的硅区域。使每个外延区域用作在沟槽的下多晶硅填充物中具有其漏极的单独晶体管的主体，并且其源于在两个外延区域之间的单晶体体中间。每个沟槽的较低多晶硅填充物也用作每个电池的电容器的存储节点，其体积用作电容器的另一个板。

24. 发明授权

US6127215A Deep pivot mask for enhanced buried-channel PFET performance and reliability 失效
标题翻译：深层掩模，增强埋地通道PFET性能和可靠性
公开(公告)号：US6127215A
公开(公告)日：2000-10-03
申请号：US181964
申请日：1998-10-29
申请人： Hans-Oliver Joachim , Jack A. Mandelman , Rajesh Rengarajan
发明人： Hans-Oliver Joachim , Jack A. Mandelman , Rajesh Rengarajan
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8238 , H01L27/08 , H01L27/092 , H01L29/78
CPC分类号： H01L27/0928 , H01L21/76237
摘要： A semiconductor structure comprises first gate conductors which wrap around N-wells of buried-channel P-type metal oxide semiconductor field effect transistors and second gate conductors which do not wrap around P-wells of surface-channel N-type metal oxide semiconductor field effect transistors and a method of manufacturing the same comprises forming insulators adjacent each of the N-wells and the P-wells, protecting the N-wells with a patterned mask, forming first divots in areas of the insulators adjacent the N-wells and forming second divots in areas of the insulators adjacent P-wells, wherein the first divots have a greater depth than the second divots.
摘要翻译：半导体结构包括第一栅极导体，其围绕掩埋沟道P型金属氧化物半导体场效应晶体管的N阱和不包围表面沟道N型金属氧化物半导体场效应的P阱的第二栅极导体晶体管及其制造方法包括在每个N阱和P阱附近形成绝缘体，用图案化掩模保护N阱，在与N阱相邻的绝缘体的区域中形成第一个纹理并形成第二个邻近P型井的绝缘体区域中的裂缝，其中第一层岩石具有比第二岩层更深的深度。

25. 发明授权

US6093614A Memory cell structure and fabrication 失效
标题翻译：存储单元结构和制造
公开(公告)号：US6093614A
公开(公告)日：2000-07-25
申请号：US34519
申请日：1998-03-04
申请人： Ulrike Gruening , Jochen Beintner , Hans-Oliver Joachim
发明人： Ulrike Gruening , Jochen Beintner , Hans-Oliver Joachim
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/20
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A pair of memory cells for use in a DRAM are formed in a monocrystalline bulk portion of a silicon wafer by first forming a pair of vertical trenches spaced apart by a bulk portion of the wafer. After a dielectric layer is formed over the walls of each trench, the trenches are each filled with polycrystalline silicon. By a pair of recess forming and recess filling steps there is formed at the top of each trench a silicon region that was grown epitaxially with the intermediate bulk portion. Each epitaxial region is made to serve as the body of a separate transistor having its drain in the lower polysilicon fill of a trench, and its source in the monocrystalline bulk intermediate between the two epitaxial regions. The lower polysilicon fill of each trench is also made to serve as the storage node of the capacitor of each cell, with the bulk serving as the other plate of the capacitor.
摘要翻译：通过首先形成由晶片的主体部分隔开的一对垂直沟槽，在硅晶片的单晶体部分中形成用于DRAM中的一对存储单元。在每个沟槽的壁之上形成电介质层之后，沟槽各自填充有多晶硅。通过一对凹陷形成和凹陷填充步骤，在每个沟槽的顶部形成有与中间体部分外延生长的硅区域。使每个外延区域用作在沟槽的下多晶硅填充物中具有其漏极的单独晶体管的主体，并且其源于在两个外延区域之间的单晶体体中间。每个沟槽的较低多晶硅填充物也用作每个电池的电容器的存储节点，其体积用作电容器的另一个板。

26. 发明授权

US5641980A Device having a high concentration region under the channel 失效
标题翻译：在通道下具有高浓度区域的奇偶装置
公开(公告)号：US5641980A
公开(公告)日：1997-06-24
申请号：US557558
申请日：1995-11-14
申请人： Yasuo Yamaguchi , Hans-Oliver Joachim , Yasuo Inoue
发明人： Yasuo Yamaguchi , Hans-Oliver Joachim , Yasuo Inoue
IPC分类号： H01L29/40 , H01L21/336 , H01L27/12 , H01L29/417 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66757 , H01L27/1203 , H01L29/78606 , H01L29/78609 , H01L29/78621
摘要： It is an object to obtain a semiconductor device with the LDD structure having both operational stability and high speed and a manufacturing method thereof. A high concentration region (11) with boron of about 1.times.10.sup.18 /cm.sup.3 introduced therein is formed extending from under a channel formation region (4) to under a drain region (6) and a source region (6') in a silicon substrate (1). The high concentration region (11) is formed in the surface of the silicon substrate (1) under the channel formation region (4), and is formed at a predetermined depth from the surface of the silicon substrate (1) under the drain region (6) and the source region (6'). A low concentration region (10) is formed in the surface of the silicon substrate (1) under the drain region (6) and the source region (6'). The formation of the high concentration region only in the surface of the semiconductor substrate under the channel formation region surely suppresses an increase in the leakage current and an increase in the drain capacitance.
摘要翻译：本发明的目的是获得具有操作稳定性和高速度的LDD结构的半导体器件及其制造方法。导入其中引入了约1×10 18 / cm 3的硼的高浓度区域（11）形成在沟道形成区域（4）下方延伸到漏极区域（6）下方的硅衬底（1）中的源极区域（6'））。在硅衬底（1）的沟道形成区域（4）的表面上形成高浓度区域（11），并且形成在与硅衬底（1）的漏极区域 6）和源极区（6'）。在漏极区域（6）和源极区域（6'）的下方的硅衬底（1）的表面中形成低浓度区域（10）。仅在沟道形成区域的半导体衬底的表面形成高浓度区域确实地抑制了漏电流的增加和漏极电容的增加。

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