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21. 发明授权

US6147402A Refractory metal capped low resistivity metal conductor lines and vias 失效
$Refractory metal capped low resistivity metal conductor lines and vias$
标题翻译：耐火金属封盖的低电阻金属导线和通孔
公开(公告)号：US6147402A
公开(公告)日：2000-11-14
申请号：US113918
申请日：1998-07-10
申请人： Rajiv V. Joshi , Jerome J. Cuomo , Hormazdyar M. Dalal , Louis L. Hsu
发明人： Rajiv V. Joshi , Jerome J. Cuomo , Hormazdyar M. Dalal , Louis L. Hsu
IPC分类号： H01L21/28 , H01L21/312 , H01L21/316 , H01L21/318 , H01L21/768 , H01L23/498 , H01L23/522 , H01L23/532 , H01L29/440 , H01L29/460
CPC分类号： H01L21/76843 , H01L21/76838 , H01L21/7684 , H01L21/76847 , H01L21/76849 , H01L21/76852 , H01L21/76877 , H01L23/49866 , H01L23/53223 , H01L23/53228 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/09701 , Y10S148/015 , Y10S257/915 , Y10S438/959
摘要： Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH.sub.4 to WF.sub.6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metalizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1 mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1 mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.
摘要翻译：用难熔金属覆盖低电阻率金属导体线或通孔允许有效地使用化学机械抛光技术，因为在化学机械抛光期间难熔金属的硬度降低的磨损特性不会划伤，腐蚀或涂抹。使用低电阻率金属或合金的物理气相沉积（例如，蒸发或准直溅射）以及随后的难熔金属的化学气相沉积（CVD）和随后的平坦化的组合来产生优异的导电线和通孔。在通过CVD施加难熔金属帽时改变SiH4与WF6的比率允许将钨控制并入钨覆盖层中。准直溅射允许在电介质中的开口中形成难熔金属衬垫，其适合作为铜基金属化的扩散阻挡层以及CVD钨。理想地，为了更快地扩散金属如铜，通过两步准直溅射工艺产生衬垫，其中第一层在相对低的真空压力下沉积，其中定向沉积占主导地位（例如，低于1mTorr），并且第二层沉积在较高的散射沉积占主导地位的真空压力（例如高于1mTorr）。对于诸如CVD钨的难熔金属，可以在较高的真空压力下使用准直溅射在一个步骤中创建衬垫。

22. 发明授权

US5976975A Refractory metal capped low resistivity metal conductor lines and vias 失效
$Refractory metal capped low resistivity metal conductor lines and vias$
标题翻译：耐火金属封盖的低电阻金属导线和通孔
公开(公告)号：US5976975A
公开(公告)日：1999-11-02
申请号：US113917
申请日：1998-07-10
申请人： Rajiv V. Joshi , Jerome J. Cuomo , Hormazdyar M. Dalal , Louis L. Hsu
发明人： Rajiv V. Joshi , Jerome J. Cuomo , Hormazdyar M. Dalal , Louis L. Hsu
IPC分类号： H01L21/28 , H01L21/312 , H01L21/316 , H01L21/318 , H01L21/768 , H01L23/498 , H01L23/522 , H01L23/532 , H01L21/44
CPC分类号： H01L21/76843 , H01L21/76838 , H01L21/7684 , H01L21/76847 , H01L21/76849 , H01L21/76852 , H01L21/76877 , H01L23/49866 , H01L23/53223 , H01L23/53228 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/09701 , Y10S148/015 , Y10S257/915 , Y10S438/959
摘要： Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the-hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH.sub.4 to WF.sub.6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metalizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below lmtorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1 mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.
摘要翻译：用难熔金属覆盖低电阻率金属导体线或通孔允许有效地使用化学机械抛光技术，因为在化学机械抛光期间难熔金属的硬度降低的磨损特性不会划伤，腐蚀或涂抹。使用低电阻率金属或合金的物理气相沉积（例如，蒸发或准直溅射）以及随后的难熔金属的化学气相沉积（CVD）和随后的平坦化的组合来产生优异的导电线和通孔。在通过CVD施加难熔金属帽时改变SiH4与WF6的比率允许将钨控制并入钨覆盖层中。准直溅射允许在电介质中的开口中形成难熔金属衬垫，其适合作为铜基金属化的扩散阻挡层以及CVD钨。理想地，为了更快地扩散金属如铜，通过两步准直溅射工艺产生衬垫，其中第一层在相对低的真空压力下沉积，其中定向沉积占主导地位（例如，低于1mtorr），并且在较高真空下沉积第二层散射沉积占主导地位的压力（例如高于1mTorr）。对于诸如CVD钨的难熔金属，可以在较高的真空压力下使用准直溅射在一个步骤中创建衬垫。

23. 发明授权

US5403779A Refractory metal capped low resistivity metal conductor lines and vias formed using PVD and CVD 失效
$Refractory metal capped low resistivity metal conductor lines and vias formed using PVD and CVD$
标题翻译：使用PVD和CVD形成耐火金属封盖的低电阻率金属导体线和通孔
公开(公告)号：US5403779A
公开(公告)日：1995-04-04
申请号：US928335
申请日：1992-08-12
申请人： Rajiv V. Joshi , Jerome J. Cuomo , Hormazdyar M. Dalal , Louis L. Hsu
发明人： Rajiv V. Joshi , Jerome J. Cuomo , Hormazdyar M. Dalal , Louis L. Hsu
IPC分类号： H01L21/28 , H01L21/312 , H01L21/316 , H01L21/318 , H01L21/768 , H01L23/498 , H01L23/522 , H01L23/532 , H01L21/44 , H01L21/48
CPC分类号： H01L21/76843 , H01L21/76838 , H01L21/7684 , H01L21/76847 , H01L21/76849 , H01L21/76852 , H01L21/76877 , H01L23/49866 , H01L23/53223 , H01L23/53228 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/09701 , Y10S148/015 , Y10S257/915 , Y10S438/959
摘要： Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH.sub.4 to WF.sub.6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metalizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1 mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1 mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.
摘要翻译：用难熔金属覆盖低电阻率金属导体线或通孔允许有效地使用化学机械抛光技术，因为在化学机械抛光期间难熔金属的硬度降低的磨损性质不会划伤，腐蚀或涂抹。使用低电阻率金属或合金的物理气相沉积（例如，蒸发或准直溅射）以及随后的难熔金属的化学气相沉积（CVD）和随后的平坦化的组合来产生优异的导电线和通孔。在通过CVD施加难熔金属帽时改变SiH4与WF6的比率允许将钨控制并入钨覆盖层中。准直溅射允许在电介质中的开口中形成难熔金属衬垫，其适合作为铜基金属化的扩散阻挡层以及CVD钨。理想地，为了更快地扩散金属如铜，通过两步准直溅射工艺产生衬垫，其中第一层在相对低的真空压力下沉积，其中定向沉积占主导地位（例如，低于1mTorr），并且第二层沉积在较高的散射沉积占主导地位的真空压力（例如高于1mTorr）。对于诸如CVD钨的难熔金属，可以在较高的真空压力下使用准直溅射在一个步骤中创建衬垫。

24. 发明授权

US07329939B2 Metal-insulator-metal capacitor and method of fabricating same 有权
标题翻译：金属绝缘体金属电容器及其制造方法
公开(公告)号：US07329939B2
公开(公告)日：2008-02-12
申请号：US11205719
申请日：2005-08-17
申请人： Louis L. Hsu , Rajiv V. Joshi , Chun-Yung Sung
发明人： Louis L. Hsu , Rajiv V. Joshi , Chun-Yung Sung
IPC分类号： H01L29/92
CPC分类号： H01G4/228 , H01G4/33 , H01L21/768 , H01L23/5223 , H01L28/60 , H01L2924/0002 , Y10S438/957 , H01L2924/00
摘要： A metal-insulator-metal (MIM) capacitor including a metal layer, an insulating layer formed on the metal layer, at least a first opening and at least a second opening formed in the first insultaing layer, a dielectric layer formed in the first opening, a conductive material deposited in the first and second openings, and a first metal plate formed over the first opening and a second metal plate formed over the second opening. A method for fabricating the MIM capacitor, includes forming the first metal layer, forming the insulating layer on the first metal layer, forming at least the first opening and at least the second opening in the first insultaing layer, depositing a mask over the second opening, forming the dielectric layer in the first opening, removing the mask, depositing the conductive material in the first and second openings, and depositing a second metal layer over the first and second openings. MIM capacitors and methods of fabricating same are described, wherein the MIM capacitors are formed simultaneously with the BEOL interconnect and large density MIM capacitors are fabricated at low cost.
摘要翻译：一种金属绝缘体金属（MIM）电容器，包括金属层，形成在金属层上的绝缘层，至少第一开口和形成在第一绝缘层中的至少第二开口，形成在第一开口中的电介质层沉积在第一和第二开口中的导电材料和形成在第一开口上的第一金属板和形成在第二开口上的第二金属板。一种制造MIM电容器的方法，包括形成第一金属层，在第一金属层上形成绝缘层，至少在第一绝缘层中形成第一开口和至少第二开口，在第二开口上沉积掩模在第一开口中形成电介质层，去除掩模，在第一和第二开口中沉积导电材料，并在第一和第二开口上沉积第二金属层。描述MIM电容器及其制造方法，其中MIM电容器与BEOL互连同时形成，并且以低成本制造大密度MIM电容器。

25. 发明授权

US07305515B2 Performance optimizing compiler for building a compiled DRAM 失效
标题翻译：用于构建编译的DRAM的性能优化编译器
公开(公告)号：US07305515B2
公开(公告)日：2007-12-04
申请号：US09793037
申请日：2001-02-26
申请人： Louis L. Hsu , Rajiv V. Joshi , John A. Fifield , Wayne F. Ellis
发明人： Louis L. Hsu , Rajiv V. Joshi , John A. Fifield , Wayne F. Ellis
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F17/5045
摘要： A compiler is provided for compiling at least one array or bank unit of a DRAM macro such that electrical performance, including cycle time, access time, setup time, among other properties, is optimized. The compiler compiles the DRAM macro according to inputted information. The compiler receives an input capacity and configuration for the DRAM macro. A compiler algorithm determines a number of wordlines and bitlines required to create the DRAM macro of the input capacity. The compiler algorithm optimizes the cycle time and access time of the DRAM macro by properly configuring a support unit of the DRAM macro based upon the number of wordlines and bitlines.
摘要翻译：提供了一种用于编译DRAM宏的至少一个阵列或存储体单元的编译器，使得包括循环时间，访问时间，建立时间在内的电性能以及其他特性被优化。编译器根据输入的信息编译DRAM宏。编译器接收DRAM宏的输入容量和配置。编译器算法确定创建输入容量的DRAM宏所需的字数和位线数。编译器算法通过根据字线和位线的数量正确配置DRAM宏的支持单元来优化DRAM宏的周期时间和访问时间。

26. 发明授权

US07018916B2 Structure and method for forming a dielectric chamber and electronic device including the dielectric chamber 有权
标题翻译：用于形成电介质室的结构和方法以及包括介电室的电子器件
公开(公告)号：US07018916B2
公开(公告)日：2006-03-28
申请号：US10698483
申请日：2003-11-03
申请人： George C. Feng , Louis L. Hsu , Rajiv V. Joshi
发明人： George C. Feng , Louis L. Hsu , Rajiv V. Joshi
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A method (and structure) that selectively forms a dielectric chamber on an electronic device by forming a dummy structure over a semiconductor substrate, depositing a dielectric layer over the dummy structure, forming an opening through the dielectric layer to the dummy structure, and removing the dummy structure to form the dielectric chamber.
摘要翻译：一种通过在半导体衬底上形成虚设结构而在电子器件上选择性地形成电介质室的方法（和结构），在虚拟结构上沉积介电层，通过介电层形成通向虚拟结构的开口，虚拟结构形成电介质室。

27. 发明授权

US06876557B2 Unified SRAM cache system for an embedded DRAM system having a micro-cell architecture 有权
标题翻译：具有微小区架构的嵌入式DRAM系统的统一SRAM缓存系统
公开(公告)号：US06876557B2
公开(公告)日：2005-04-05
申请号：US09879653
申请日：2001-06-12
申请人： Louis L. Hsu , Rajiv V. Joshi
发明人： Louis L. Hsu , Rajiv V. Joshi
IPC分类号： G06F12/08 , G11C15/00
CPC分类号： G06F12/0893
摘要： A unified SRAM cache system is provided incorporated several SRAM macros of an embedded DRAM (eDRAM) system and their functions. Each incorporated SRAM macro can be independently accessed without interfering with the other incorporated SRAM macros within the unified SRAM cache system. The incorporated SRAM macros share a single set of support circuits, such as row decoders, bank decoders, sense amplifiers, wordline drivers, bank pre-decoders, row pre-decoders, I/O drivers, multiplexer switch circuits, and data buses, without compromising the performance of the eDRAM system.
摘要翻译：提供了一个统一的SRAM缓存系统，其中并入了嵌入式DRAM（eDRAM）系统的多个SRAM宏及其功能。每个并入的SRAM宏可以独立访问，而不会干扰统一SRAM缓存系统中的其他并入的SRAM宏。结合的SRAM宏共享一组支持电路，例如行解码器，存储体解码器，读出放大器，字线驱动器，存储体解码器，行预解码器，I / O驱动器，复用器开关电路和数据总线，无需损害eDRAM系统的性能。

28. 发明授权

US06751156B2 Semiconductor memory system having dynamically delayed timing for high-speed data transfers 有权
标题翻译：半导体存储器系统具有用于高速数据传输的动态延迟定时
公开(公告)号：US06751156B2
公开(公告)日：2004-06-15
申请号：US10042604
申请日：2002-01-09
申请人： Louis L. Hsu , Rajiv V. Joshi
发明人： Louis L. Hsu , Rajiv V. Joshi
IPC分类号： G11C800
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/1066 , G11C7/222 , G11C29/84 , G11C2207/104
摘要： A timing system for controlling timing of data transfers within a semiconductor memory system is provided. The timing system includes a programming circuit for generating a bias signal, wherein the bias signal is biased in accordance with an incoming data transfer address corresponding to a memory address of the memory system, and a delay module for receiving the bias signal and generating an output clock signal, wherein the output clock signal is delayed in accordance with the bias signal.
摘要翻译：提供了一种用于控制半导体存储器系统内的数据传输定时的定时系统。定时系统包括用于产生偏置信号的编程电路，其中偏置信号根据与存储器系统的存储器地址对应的输入数据传输地址偏置，延迟模块用于接收偏置信号并产生输出时钟信号，其中所述输出时钟信号根据所述偏置信号被延迟。

29. 发明授权

US06713791B2 T-RAM array having a planar cell structure and method for fabricating the same 有权
标题翻译：具有平面单元结构的T-RAM阵列及其制造方法
公开(公告)号：US06713791B2
公开(公告)日：2004-03-30
申请号：US09770788
申请日：2001-01-26
申请人： Louis L. Hsu , Rajiv V. Joshi , Fariborz Assaderaghi , Dan Moy , Werner Rausch , James Culp
发明人： Louis L. Hsu , Rajiv V. Joshi , Fariborz Assaderaghi , Dan Moy , Werner Rausch , James Culp
IPC分类号： H01L2974
CPC分类号： H01L27/1027 , G11C5/142 , G11C11/39
摘要： A T-RAM array having a planar cell structure is presented. The T-RAM array includes n-MOS and p-MOS support devices which are fabricated by sharing process implant steps with T-RAM cells of the T-RAM array. A method is also presented for fabricating the T-RAM array having the planar cell structure. The method entails simultaneously fabricating a first portion of a T-RAM cell and the n-MOS support device; simultaneously fabricating a second portion of the T-RAM cell and the p-MOS support device; and finishing the fabrication of the T-RAM cell by interconnecting the T-RAM cell with the p-MOS and n-MOS support devices. The first portion of the T-RAM cell is a transfer gate and the second portion of the T-RAM cell is a gated-lateral thyristor storage element. Accordingly, process steps in fabricating the T-RAM cells are shared with process steps in fabricating the n-MOS and p-MOS support devices. The n-MOS and p-MOS support devices refer to sense amplifiers, wordline drivers, column and row decoders, etc. which are connected to the T-RAM array.
摘要翻译：提出了具有平面单元结构的T-RAM阵列。 T-RAM阵列包括通过与T-RAM阵列的T-RAM单元共享处理注入步骤制造的n-MOS和p-MOS支持器件。还提出了一种制造具有平面单元结构的T-RAM阵列的方法。该方法需要同时制造T-RAM单元和n-MOS支持器件的第一部分; 同时制造T-RAM单元和p-MOS支持装置的第二部分; 并通过将T-RAM单元与p-MOS和n-MOS支持器件相互连接来完成T-RAM单元的制造。 T-RAM单元的第一部分是传输门，并且T-RAM单元的第二部分是门控侧晶闸管存储元件。因此，制造T-RAM单元的工艺步骤与制造n-MOS和p-MOS支持器件的工艺步骤共享。 n-MOS和p-MOS支持器件是指连接到T-RAM阵列的读出放大器，字线驱动器，列和行解码器等。

30. 发明授权

US06563736B2 Flash memory structure having double celled elements and method for fabricating the same 有权
公开(公告)号：US06563736B2
公开(公告)日：2003-05-13
申请号：US09860736
申请日：2001-05-18
申请人： Louis L. Hsu , Rajiv V. Joshi , Carl Radens , Jack A. Mandelman , William R. Tonti
发明人： Louis L. Hsu , Rajiv V. Joshi , Carl Radens , Jack A. Mandelman , William R. Tonti
IPC分类号： G11C1604
CPC分类号： H01L27/11521 , G11C16/0441 , G11C16/0458 , H01L27/115
摘要： A flash memory array having a plurality of bitlines, at least one wordline and a plurality of flash memory flash memory elements, wherein each flash memory element includes two transistors for storing two bits, and wherein each flash memory element is positioned between a pair of adjacent bitlines. A method is also presented for fabricating the flash memory array having the plurality of flash memory elements, wherein each flash memory element is configured for storing two bits.

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