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21. 发明授权

US07683478B2 Hermetic seal and reliable bonding structures for 3D applications 失效
标题翻译：密封密封和3D应用的可靠结合结构
公开(公告)号：US07683478B2
公开(公告)日：2010-03-23
申请号：US12026776
申请日：2008-02-06
申请人： Kuan-Neng Chen , Bruce K. Furman , Edmund J. Sprogis , Anna W. Topol , Cornelia K. Tsang , Matthew R. Wordeman , Albert M. Young
发明人： Kuan-Neng Chen , Bruce K. Furman , Edmund J. Sprogis , Anna W. Topol , Cornelia K. Tsang , Matthew R. Wordeman , Albert M. Young
IPC分类号： H01L23/34
CPC分类号： H01L25/50 , H01L2225/06513 , H01L2225/06593 , H01L2924/0002 , H01L2924/00
摘要： A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.
摘要翻译：一种密封的微电子结构，其提供机械应力耐久性并且包括在多个位置处电连接到半导体结构的至少两个芯片。每个芯片沿着其周边包括连续的接合材料，以及连接到位于每个芯片的周边内的每个芯片的至少一个支撑柱。每个支撑柱向外延伸，使得当至少两个芯片彼此定位时，支撑柱彼此配合。至少两个芯片之间的密封由芯片彼此的重叠关系产生，使得接合材料和支撑柱彼此配合。因此，当至少两个芯片配合在一起时形成密封，并且导致粘合芯片结构。

22. 发明申请

US20090311858A1 PROGRAMMABLE VIA STRUCTURE AND METHOD OF FABRICATING SAME 有权
标题翻译：可编程通过结构和制作方法
公开(公告)号：US20090311858A1
公开(公告)日：2009-12-17
申请号：US12538120
申请日：2009-08-08
申请人： Kuan-Neng Chen , Lia Krusin-Elbaum , Chung H. Lam , Albert M. Young
发明人： Kuan-Neng Chen , Lia Krusin-Elbaum , Chung H. Lam , Albert M. Young
IPC分类号： H01L21/768
CPC分类号： H01L45/122 , H01L45/06 , H01L45/1206 , H01L45/1286 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： A programmable via structure is provided as well as a method of fabricating the same. The inventive programmable via a semiconductor substrate. An oxide layer such as a thermal oxide is located on a surface of the semiconductor substrate. A patterned heating material is located on a surface of the oxide layer. The inventive structure also includes a patterned dielectric material having a least one via filled with a phase change material (PCM). The patterned dielectric material including the PCM filled via is located on a surface of the patterned heating material. A patterned diffusion barrier is located on an exposed surface of said at least one via filled with the phase change material. The inventive structure also includes contact vias that extend through the patterned dielectric material. The contact vias are filled with a conductive material which also extends onto the upper surface of the patterned dielectric material. A conductive material which serves as the input of the device is located atop the patterned diffusion barrier that is located directly above the via that is filled with the phase change material.
摘要翻译：提供了可编程通孔结构以及其制造方法。本发明可编程通过半导体衬底。诸如热氧化物的氧化物层位于半导体衬底的表面上。图案化的加热材料位于氧化物层的表面上。本发明的结构还包括具有填充有相变材料（PCM）的至少一个通孔的图案化电介质材料。包括PCM填充通孔的图案化电介质材料位于图案化加热材料的表面上。图案化扩散阻挡层位于所述至少一个充满相变材料的通孔的暴露表面上。本发明的结构还包括延伸通过图案化电介质材料的接触孔。接触通孔填充有也延伸到图案化电介质材料的上表面上的导电材料。用作器件输入的导电材料位于图案化的扩散阻挡层的顶部，其位于通过相变材料填充的正上方。

23. 发明申请

US20080171423A1 LOW-COST STRAINED SOI SUBSTRATE FOR HIGH-PERFORMANCE CMOS TECHNOLOGY 有权
标题翻译：用于高性能CMOS技术的低成本应变SOI衬底
公开(公告)号：US20080171423A1
公开(公告)日：2008-07-17
申请号：US11622543
申请日：2007-01-12
申请人： Meikei Ieong , Douglas C. La Tulipe , Leathen Shi , Anna W. Topol , James Vichiconti , Albert M. Young
发明人： Meikei Ieong , Douglas C. La Tulipe , Leathen Shi , Anna W. Topol , James Vichiconti , Albert M. Young
IPC分类号： H01L21/20
CPC分类号： H01L21/02658 , H01L21/02667 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/78 , H01L29/7843
摘要： A cost-effective and simple method of fabricating strained semiconductor-on-insulator (SSOI) structures which avoids epitaxial growth and subsequent wafer bonding processing steps is provided. In accordance with the present invention, a strain-memorization technique is used to create strained semiconductor regions on a SOI substrate. The transistors formed on the strained semiconductor regions have higher carrier mobility because the Si regions have been strained. The inventive method includes (i) ion implantation to create a thin amorphization layer, (ii) deposition of a high stress film on the amorphization layer, (iii) a thermal anneal to recrystallize the amorphization layer, and (iv) removal of the stress film. Because the SOI substrate was under stress during the recrystallization process, the final semiconductor layer will be under stress as well. The amount of stress and the polaity (tensile or compressive) of the stress can be controlled by the type and thickness of the stress films.
摘要翻译：提供了一种制造应变绝缘体上半导体（SSOI）结构的成本有效和简单的方法，其避免了外延生长和随后的晶片接合处理步骤。根据本发明，使用应变记忆技术在SOI衬底上产生应变半导体区域。形成在应变半导体区域上的晶体管具有更高的载流子迁移率，因为Si区域已经变形。本发明的方法包括（i）离子注入以产生薄的非晶化层，（ii）在非晶化层上沉积高应力膜，（iii）热退火以使非晶化层重结晶，和（iv）去除应力电影。由于在再结晶过程中SOI衬底处于应力状态，所以最终的半导体层也将受到应力。应力的量和应力的极性（拉伸或压缩）可以通过应力膜的类型和厚度来控制。

24. 发明申请

US20080142775A1 PROGRAMMABLE VIA STRUCTURE AND METHOD OF FABRICATING SAME 有权
标题翻译：可编程通过结构和制作方法
公开(公告)号：US20080142775A1
公开(公告)日：2008-06-19
申请号：US11612631
申请日：2006-12-19
申请人： Kuan-Neng Chen , Lia Krusin-Elbaum , Chung H. Lam , Albert M. Young
发明人： Kuan-Neng Chen , Lia Krusin-Elbaum , Chung H. Lam , Albert M. Young
IPC分类号： H01L45/00
CPC分类号： H01L45/122 , H01L45/06 , H01L45/1206 , H01L45/1286 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： A programmable via structure is provided as well as a method of fabricating the same. The inventive programmable via a semiconductor substrate. An oxide layer such as a thermal oxide is located on a surface of the semiconductor substrate. A patterned heating material is located on a surface of the oxide layer. The inventive structure also includes a patterned dielectric material having a least one via filled with a phase change material (PCM). The patterned dielectric material including the PCM filled via is located on a surface of the patterned heating material. A patterned diffusion barrier is located on an exposed surface of said at least one via filled with the phase change material. The inventive structure also includes contact vias that extend through the patterned dielectric material. The contact vias are filled with a conductive material which also extends onto the upper surface of the patterned dielectric material. A conductive material which serves as the input of the device is located atop the patterned diffusion barrier that is located directly above the via that is filled with the phase change material.
摘要翻译：提供了可编程通孔结构以及其制造方法。本发明可编程通过半导体衬底。诸如热氧化物的氧化物层位于半导体衬底的表面上。图案化的加热材料位于氧化物层的表面上。本发明的结构还包括具有填充有相变材料（PCM）的至少一个通孔的图案化电介质材料。包括PCM填充通孔的图案化电介质材料位于图案化加热材料的表面上。图案化扩散阻挡层位于所述至少一个充满相变材料的通孔的暴露表面上。本发明的结构还包括延伸通过图案化电介质材料的接触孔。接触通孔填充有也延伸到图案化电介质材料的上表面上的导电材料。用作器件输入的导电材料位于图案化的扩散阻挡层的顶部，其位于通过相变材料填充的正上方。

25. 发明申请

US20080124835A1 HERMETIC SEAL AND RELIABLE BONDING STRUCTURES FOR 3D APPLICATIONS 审中-公开
公开(公告)号：US20080124835A1
公开(公告)日：2008-05-29
申请号：US11534366
申请日：2006-11-03
申请人： Kuan-Neng Chen , Bruce K. Furman , Edmund J. Sprogis , Anna W. Topol , Cornelia K. Tsang , Matthew R. Wordeman , Albert M. Young
发明人： Kuan-Neng Chen , Bruce K. Furman , Edmund J. Sprogis , Anna W. Topol , Cornelia K. Tsang , Matthew R. Wordeman , Albert M. Young
IPC分类号： H01L21/50
CPC分类号： H01L25/50 , H01L2224/80895 , H01L2225/06513 , H01L2225/06593 , H01L2924/0002 , H01L2924/00
摘要： A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.

26. 发明申请

US20150024548A1 COMPUTER READABLE MEDIUM ENCODED WITH A PROGRAM FOR FABRICATING 3D INTEGRATED CIRCUIT DEVICE USING INTERFACE WAFER AS PERMANENT CARRIER 有权
标题翻译：使用接口作为永久载体制作3D集成电路设备的程序编写的计算机可读介质
公开(公告)号：US20150024548A1
公开(公告)日：2015-01-22
申请号：US13572004
申请日：2012-08-10
申请人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
发明人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
IPC分类号： H01L25/065 , H01L25/00
CPC分类号： H01L25/0657 , H01L21/6835 , H01L25/18 , H01L25/50 , H01L2221/68377 , H01L2224/0401 , H01L2224/05001 , H01L2224/05008 , H01L2224/05009 , H01L2224/05024 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05558 , H01L2224/05568 , H01L2224/0557 , H01L2224/056 , H01L2224/131 , H01L2224/16227 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/33181 , H01L2224/73153 , H01L2224/73253 , H01L2224/83121 , H01L2224/83895 , H01L2224/92242 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593 , H01L2924/10253 , H01L2924/14 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/15311 , H01L2924/157 , H01L2924/37001 , H01L2224/83 , H01L2224/11 , H01L2924/014 , H01L2924/00014
摘要： A computer readable medium is provided that is encoded with a program comprising instructions for performing a method for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer.
摘要翻译：提供了一种计算机可读介质，其由包含用于执行制造3D集成电路结构的方法的指令的程序编码。提供了包括第一布线层和穿硅通孔的接口晶片，以及包括有源电路的第一有源电路层晶片。第一有源电路层晶片被结合到界面晶片。然后，去除第一有源电路层晶片的第一部分，使得第二部分保持附着到界面晶片。包括接口晶片和第一有源电路层晶片的第二部分的堆叠结构被结合到基底晶片。接下来，将界面晶片减薄以形成界面层，并且在界面层上形成通过界面层中的穿硅通孔耦合到第一布线层的金属化。

27. 发明授权

US08174841B2 Adaptive interconnect structure 失效
标题翻译：自适应互连结构
公开(公告)号：US08174841B2
公开(公告)日：2012-05-08
申请号：US12430416
申请日：2009-04-27
申请人： Leland Chang , Matthew R. Wordeman , Albert M. Young
发明人： Leland Chang , Matthew R. Wordeman , Albert M. Young
IPC分类号： H01R43/00
CPC分类号： H01L25/0657 , H01L23/5252 , H01L23/5256 , H01L24/06 , H01L24/14 , H01L24/16 , H01L25/50 , H01L2224/0401 , H01L2224/05555 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/13099 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/014 , H01L2924/04953 , H01L2924/00014
摘要： An array of contact pads on a semiconductor structure has a pitch less than twice an overlay tolerance of a bonding process employed to vertically stack semiconductor structures. A set of contact pads within the area of overlay variation for a matching contact pin may be electrically connected to an array of programmable contacts such that one programmable contact is connected to each contact pad within the area of overlay variation. One contact pad may be provided with a plurality of programmable contacts. The variability of contacts between contact pins and contact pads is accommodated by connecting or disconnecting programmable contacts after the stacking of semiconductor structures. Since the pitch of the array of contact pins may be less than twice the overlay variation of the bonding process, a high density of interconnections is provided in the vertically stacked structure.
摘要翻译：半导体结构上的接触焊盘阵列的间距小于用于垂直堆叠半导体结构的接合工艺的覆盖公差的两倍。用于匹配接触针的覆盖变化区域内的一组接触焊盘可以电连接到可编程触点阵列，使得一个可编程触点连接到覆盖变化区域内的每个接触焊盘。一个接触垫可以设置有多个可编程触点。在半导体结构堆叠之后，通过连接或断开可编程触点来容纳接触引脚和接触焊盘之间的接触的可变性。由于接触引脚阵列的间距可能小于接合过程的覆盖变化的两倍，所以垂直堆叠结构中提供了高密度的互连。

28. 发明授权

US07999377B2 Method and structure for optimizing yield of 3-D chip manufacture 有权
标题翻译：优化3-D芯片制造产量的方法和结构
公开(公告)号：US07999377B2
公开(公告)日：2011-08-16
申请号：US12029122
申请日：2008-02-11
申请人： Edward M. DeMulder , Sarah H. Knickerbocker , Michael J. Shapiro , Albert M. Young
发明人： Edward M. DeMulder , Sarah H. Knickerbocker , Michael J. Shapiro , Albert M. Young
IPC分类号： H01L23/488
CPC分类号： H01L21/8221 , H01L27/0688 , H01L2224/13
摘要： The process begins with separate device wafers having complimentary chips. Thin metal capture pads, having a preferred thickness of about 10 microns so that substantial pressure may be applied during processing without damaging capture pads, are deposited on both device wafers, which are then tested and mapped for good chip sites. A handle wafer is attached to one device wafer, which can then be thinned to improve via etching and filling. Capture pads are removed and replaced after thinning. The device wafer with handle wafer is diced, and good chips with attached portions of the diced handle wafer are positioned and bonded to the good chip sites of the other device wafer, and the handle wafer portions are removed. The device wafer having known good 3-D chips then undergoes final processing.
摘要翻译：该过程开始于具有互补芯片的单独的器件晶片。薄金属捕获垫具有约10微米的优选厚度，使得在处理过程中可能施加大的压力而不损坏捕获垫，沉积在两个器件晶片上，然后对其进行测试和映射以获得良好的芯片位置。处理晶片连接到一个器件晶片，然后可以通过蚀刻和填充来减薄其改进。捕获垫被去除并在变薄后更换。切割具有处理晶片的器件晶片，并且将具有切割手柄晶片的附接部分的良好芯片定位并结合到另一器件晶片的良好芯片位置，并移除处理晶片部分。具有已知良好3-D芯片的器件晶片然后进行最终处理。

29. 发明授权

US07888164B2 Programmable via structure and method of fabricating same 有权
标题翻译：可编程通孔结构及其制造方法
公开(公告)号：US07888164B2
公开(公告)日：2011-02-15
申请号：US12538120
申请日：2009-08-08
申请人： Kuan-Neng Chen , Lia Krusin-Elbaum , Chung H. Lam , Albert M. Young
发明人： Kuan-Neng Chen , Lia Krusin-Elbaum , Chung H. Lam , Albert M. Young
IPC分类号： H01L21/02
CPC分类号： H01L45/122 , H01L45/06 , H01L45/1206 , H01L45/1286 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： A method of fabricating a programmable via structure is provided. The method includes providing a patterned heating material on a surface of an oxide layer. The oxide layer is located above a semiconductor substrate. A patterned dielectric material is formed having a least one via on a surface of the patterned heating material. The at least one via is filled with a phase change material such that a lower surface of the phase change material is in direct contact with a portion of the patterned heating material. A patterned diffusion barrier is formed on an exposed surface of the at least one via filled with the phase change material. A method of programmable a programmable via structure made by the method is also disclosed.
摘要翻译：提供一种制造可编程通孔结构的方法。该方法包括在氧化物层的表面上提供图案化的加热材料。氧化物层位于半导体衬底之上。在图案化加热材料的表面上形成具有至少一个通孔的图案化电介质材料。至少一个通孔填充有相变材料，使得相变材料的下表面与图案化加热材料的一部分直接接触。图案化的扩散阻挡层形成在填充有相变材料的至少一个通孔的暴露表面上。还公开了一种通过该方法制成的可编程通孔结构的方法。

30. 发明申请

US20100314711A1 3D INTEGRATED CIRCUIT DEVICE HAVING LOWER-COST ACTIVE CIRCUITRY LAYERS STACKED BEFORE HIGHER-COST ACTIVE CIRCUITRY LAYER 有权
标题翻译：具有低成本有源电路层的3D集成电路器件在高成本有源电路层之前堆叠
公开(公告)号：US20100314711A1
公开(公告)日：2010-12-16
申请号：US12194211
申请日：2008-08-19
申请人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
发明人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
IPC分类号： H01L27/12 , H01L21/768
CPC分类号： H01L25/50 , H01L21/6835 , H01L21/76898 , H01L21/8221 , H01L25/0657 , H01L25/18 , H01L27/0688 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L2221/68377 , H01L2224/0401 , H01L2224/05558 , H01L2224/0557 , H01L2224/131 , H01L2224/16 , H01L2224/16227 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/33181 , H01L2224/73153 , H01L2224/73253 , H01L2224/83121 , H01L2224/83895 , H01L2224/92242 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593 , H01L2924/00011 , H01L2924/00014 , H01L2924/10253 , H01L2924/14 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/15311 , H01L2924/157 , H01L2924/37001 , H01L2224/80001 , H01L2924/014 , H01L2224/83 , H01L2224/11
摘要： A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer that includes active circuitry is provided, and a first portion of the first active circuitry layer wafer is removed such that a second portion of the first active circuitry layer wafer remains. Another wafer that includes active circuitry is provided, and the other wafer is bonded to the second portion of the first active circuitry layer wafer. The first active circuitry layer wafer is lower-cost than the other wafer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.
摘要翻译：提供了一种用于制造3D集成电路结构的方法。根据该方法，提供包括有源电路的第一有源电路层晶片，并且去除第一有源电路层晶片的第一部分，使得第一有源电路层晶片的第二部分保留。提供了包括有源电路的另一个晶片，另一个晶片结合到第一有源电路层晶片的第二部分。第一有源电路层晶片比另一个晶片低成本。还提供了用用于制造3D集成电路结构的程序编码的有形计算机可读介质和3D集成电路结构。

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