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21. 发明授权

US07432600B2 System having semiconductor component with multiple stacked dice 有权
标题翻译：具有多个堆叠骰子的半导体元件的系统
公开(公告)号：US07432600B2
公开(公告)日：2008-10-07
申请号：US11473731
申请日：2006-06-23
申请人： Dean A. Klein , Alan G. Wood , Trung Tri Doan
发明人： Dean A. Klein , Alan G. Wood , Trung Tri Doan
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/48 , B33Y80/00 , H01L21/563 , H01L23/3114 , H01L23/49833 , H01L24/10 , H01L24/13 , H01L25/0652 , H01L25/0657 , H01L2224/05568 , H01L2224/05573 , H01L2224/13 , H01L2224/13099 , H01L2224/16145 , H01L2224/73203 , H01L2224/73204 , H01L2225/06513 , H01L2225/06524 , H01L2225/06527 , H01L2225/06586 , H01L2225/06596 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01078 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/18161 , H01L2924/19041 , H01L2924/351 , H01L2924/00 , H01L2224/05599
摘要： A system includes a semiconductor component having a base die and a secondary die flip chip mounted to the base die. The base die includes a set of stacking contacts for flip chip mounting the secondary die to the base die, and a set of interconnect contacts configured as an internal signal transmission system, and a physical structure for supporting a terminal contact system of the package component. The component also includes an encapsulant on the base die encapsulating the interconnect contacts, an underfill layer between the dice, and terminal contacts configured for flip chip mounting the package component to a supporting substrate.
摘要翻译：一种系统包括具有安装在基模上的基模和二次晶片倒装芯片的半导体部件。基座芯片包括用于将二次管芯倒装芯片安装到基底管芯的一组叠置触点，以及一组配置为内部信号传输系统的互连触头，以及用于支撑封装部件的端子接触系统的物理结构。该组件还包括在基底模具上封装了互连触头的密封剂，芯片之间的底部填充层和被配置用于将封装部件倒装芯片安装到支撑衬底的端子触头。

22. 发明授权

US07367871B2 Semiconductor processing methods of removing conductive material 有权
标题翻译：去除导电材料的半导体加工方法
公开(公告)号：US07367871B2
公开(公告)日：2008-05-06
申请号：US11449201
申请日：2006-06-05
申请人： Trung Tri Doan , Scott G. Meikle
发明人： Trung Tri Doan , Scott G. Meikle
IPC分类号： B24B1/00
CPC分类号： B24B37/11 , B23H5/08 , B24B37/042 , B24B37/046 , B24B37/20 , C25F3/30 , H01L21/3212 , H01L21/32125
摘要： The invention includes a semiconductive processing method of electrochemical-mechanical removing at least some of a conductive material from over a surface of a semiconductor substrate. A cathode is provided at a first location of the wafer, and an anode is provided at a second location of the wafer. The conductive material is polished with the polishing pad polishing surface. The polishing occurs at a region of the conductive material and not at another region. The region where the polishing occurs is defined as a polishing operation location. The polishing operation location is displaced across the surface of the substrate from said second location of the substrate toward said first location of the substrate. The polishing operation location is not displaced from said first location toward said second location when the polishing operation location is between the first and second locations. The invention also includes a semiconductor processing method of removing at least some of a conductive material from over a surface of a semiconductive material wafer. A polishing pad is displaced across an upper surface of the wafer from a central region of the wafer toward a periphery of the wafer, and is not displaced from the periphery to the central region.
摘要翻译：本发明包括从半导体衬底的表面上电化学 - 机械去除至少一些导电材料的半导体处理方法。阴极设置在晶片的第一位置处，并且阳极设置在晶片的第二位置处。用抛光垫抛光表面抛光导电材料。抛光发生在导电材料的区域而不是在另一区域。抛光发生的区域被定义为抛光操作位置。抛光操作位置从衬底的所述第二位置横跨衬底的表面移动到衬底的所述第一位置。当抛光操作位置在第一和第二位置之间时，抛光操作位置不会从所述第一位置移动到所述第二位置。本发明还包括从半导体材料晶片的表面上去除至少一些导电材料的半导体加工方法。抛光垫从晶片的中心区域朝着晶片的周边跨越晶片的上表面移位，并且不会从周边移动到中心区域。

23. 发明申请

US20070212854A1 METHOD OF SEPARATING SEMICONDUCTOR DIES 有权
标题翻译：分离半导体器件的方法
公开(公告)号：US20070212854A1
公开(公告)日：2007-09-13
申请号：US11682814
申请日：2007-03-06
申请人： Chen-Fu Chu , Trung Tri Doan , Hao-Chun Cheng , Feng-Hsu Fan , Fu-Hsien Wang
发明人： Chen-Fu Chu , Trung Tri Doan , Hao-Chun Cheng , Feng-Hsu Fan , Fu-Hsien Wang
IPC分类号： H01L21/00
CPC分类号： H01L33/0079 , H01L33/0095
摘要： A method for the separation of multiple dies during semiconductor fabrication is described. On an upper surface of a semiconductor wafer containing multiple dies, metal layers are deposited everywhere except where a block of stop electroplating material exists. The stop electroplating material is obliterated, and a barrier layer is formed above the entire remaining structure. A sacrificial metal element is added above the barrier layer, and then the substrate is removed. After the semiconductor material between the individual dies is eradicated, any desired bonding pads and patterned circuitry are added to the semiconductor surface opposite the sacrificial metal element, a passivation layer is added to this surface, and then the sacrificial metal element is removed. Tape is added to the now exposed barrier layer, the passivation layer is removed, the resulting structure is flipped over, and the tape is expanded to separate the individual dies.
摘要翻译：描述了在半导体制造期间分离多个管芯的方法。在包含多个模具的半导体晶片的上表面上，除了存在一块停止电镀材料之外，金属层被沉积。停止电镀材料被消除，并且在整个剩余结构上方形成阻挡层。在阻挡层上方添加牺牲金属元素，然后去除衬底。在消除各个管芯之间的半导体材料之后，将任何期望的接合焊盘和图案化电路添加到与牺牲金属元件相对的半导体表面，在该表面上添加钝化层，然后去除牺牲金属元件。将胶带添加到现在暴露的阻挡层中，去除钝化层，将所得结构翻转，并且将带扩展以分离各个模具。

24. 发明授权

US07183208B2 Methods for treating pluralities of discrete semiconductor substrates 失效
公开(公告)号：US07183208B2
公开(公告)日：2007-02-27
申请号：US10349808
申请日：2003-01-22
申请人： Trung Tri Doan , Lyle D. Breiner , Er-Xuan Ping , Lingyi A. Zheng
发明人： Trung Tri Doan , Lyle D. Breiner , Er-Xuan Ping , Lingyi A. Zheng
IPC分类号： H01L21/205
CPC分类号： H01L21/0228 , C23C16/0236 , C23C16/0245 , C23C16/45546 , C23C16/54 , C30B25/02 , H01L21/02046 , H01L21/0214 , H01L21/02142 , H01L21/02164 , H01L21/0217 , H01L21/02175 , H01L21/02211 , H01L21/02326 , H01L21/28562 , H01L21/3144 , H01L21/31604 , H01L21/31683 , H01L21/3185 , H01L21/76841 , H01L21/76856 , H01L21/76888
摘要： The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.

25. 发明授权

US07170103B2 Wafer with vertical diode structures 有权
标题翻译：具有垂直二极管结构的晶圆
公开(公告)号：US07170103B2
公开(公告)日：2007-01-30
申请号：US11210357
申请日：2005-08-24
申请人： Fernando Gonzalez , Tyler A. Lowrey , Trung Tri Doan , Raymond A. Turi , Graham R. Wolstenholme
发明人： Fernando Gonzalez , Tyler A. Lowrey , Trung Tri Doan , Raymond A. Turi , Graham R. Wolstenholme
IPC分类号： H01L29/88 , H01L29/861
CPC分类号： H01L21/02667 , H01L21/02532 , H01L21/2022 , H01L27/0814 , H01L27/101 , H01L27/1021 , H01L27/24 , H01L29/6609 , H01L29/66136 , H01L29/861 , H01L45/04 , H01L45/145 , Y10S257/903 , Y10S257/91 , Y10S438/979
摘要： A method of making a vertical diode is provided, the vertical diode having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.
摘要翻译：提供了一种制造垂直二极管的方法，该垂直二极管具有与其相连的二极管开口，其延伸穿过绝缘层并接触硅晶片上的有源区。硅化钛层覆盖二极管开口的内表面并接触有源区。二极管开口最初填充有非晶硅插塞，其在沉积期间被掺杂，随后再结晶以形成大晶粒多晶硅。硅插头具有重掺杂有第一类型掺杂剂的顶部部分和轻掺杂有第二类型掺杂剂的底部部分。顶部由底部界定，以便不与硅化钛层接触。对于垂直二极管的一个实施例，可编程电阻器接触硅插头的顶部并且金属线接触可编程电阻器。

26. 发明授权

US07078266B2 Method for fabricating semiconductor components with thinned substrate, back side contacts and circuit side contacts 失效
标题翻译：用薄化衬底，背面接触和电路侧触点制造半导体器件的方法
公开(公告)号：US07078266B2
公开(公告)日：2006-07-18
申请号：US10933144
申请日：2004-09-02
申请人： Alan G. Wood , Trung Tri Doan
发明人： Alan G. Wood , Trung Tri Doan
IPC分类号： H01L21/48
CPC分类号： H01L23/3114 , H01L21/76831 , H01L21/76898 , H01L23/481 , H01L24/11 , H01L24/13 , H01L25/0657 , H01L25/50 , H01L2224/05001 , H01L2224/05009 , H01L2224/05172 , H01L2224/0557 , H01L2224/05572 , H01L2224/1134 , H01L2224/13099 , H01L2224/131 , H01L2224/16 , H01L2225/06541 , H01L2225/06586 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , Y10S438/977 , H01L2924/00 , H01L2924/00014 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/05681 , H01L2224/05684 , H01L2224/05111 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05184
摘要： A semiconductor component includes back side pin contacts fabricated using a circuit side fabrication method. The component also includes a thinned semiconductor die having a pattern of die contacts, and conductive members formed by filled openings in the die contacts and the die. In addition, the pin contacts are formed by terminal portions of the conductive members. The fabrication method includes the steps of forming the openings and the conductive members, and then thinning and etching the die to form the pin contacts. An alternate embodiment female component includes female conductive members configured to physically and electrically engage pin contacts on a mating component of a stacked assembly.
摘要翻译：半导体部件包括使用电路侧制造方法制造的后侧引脚触点。该部件还包括具有模接触图案的薄化半导体管芯，以及由管芯接触件和管芯中的填充开口形成的导电部件。此外，引脚触点由导电构件的端子部分形成。制造方法包括形成开口和导电构件的步骤，然后使模具变薄和蚀刻以形成引脚触点。替代实施例的阴部件包括阴导电部件，其被配置为物理地和电接合堆叠组件的配合部件上的销触点。

27. 发明授权

US07001845B2 Methods of treating surfaces of substrates 失效
公开(公告)号：US07001845B2
公开(公告)日：2006-02-21
申请号：US10832764
申请日：2004-04-26
申请人： Scott E. Moore , Trung Tri Doan
发明人： Scott E. Moore , Trung Tri Doan
IPC分类号： H01L21/431
CPC分类号： H01L21/6704 , B08B1/00 , B08B7/0092 , B24B37/042 , H01L21/67046 , Y10S134/902 , Y10S438/906 , Y10S438/959 , Y10S438/963 , Y10S438/974
摘要： In one aspect, the invention includes a method of treating a surface of a substrate. A mixture which comprises at least a frozen first material and liquid second material is provided on the surface and moved relative to the substrate. In another aspect, the invention encompasses a method of treating a plurality of substrates. A treating member is provided proximate a first substrate, and an initial layer of frozen material is formed over a surface of the treating member. A surface of the first substrate is treated by moving at least one of the treating member and the first substrate relative to the other of the treating member and the first substrate. After the surface of the first substrate is treated, the initial layer of frozen material is removed from over the surface of the treating member. The treating member is then provided proximate another substrate, and the surface of the other substrate is treated by moving at least one of the treating member and the second substrate relative to the other of the treating member and the second substrate.

28. 发明申请

US20050029650A1 Method for fabricating semiconductor components with thinned substrate, back side contacts and circuit side contacts 失效
标题翻译：用薄化衬底，背面接触和电路侧触点制造半导体器件的方法
公开(公告)号：US20050029650A1
公开(公告)日：2005-02-10
申请号：US10933144
申请日：2004-09-02
申请人： Alan Wood , Trung Tri Doan
发明人： Alan Wood , Trung Tri Doan
IPC分类号： H01L23/48 , H01L25/065 , H01L21/44 , H01L23/02
CPC分类号： H01L23/3114 , H01L21/76831 , H01L21/76898 , H01L23/481 , H01L24/11 , H01L24/13 , H01L25/0657 , H01L25/50 , H01L2224/05001 , H01L2224/05009 , H01L2224/05172 , H01L2224/0557 , H01L2224/05572 , H01L2224/1134 , H01L2224/13099 , H01L2224/131 , H01L2224/16 , H01L2225/06541 , H01L2225/06586 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , Y10S438/977 , H01L2924/00 , H01L2924/00014 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/05681 , H01L2224/05684 , H01L2224/05111 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05184
摘要： A semiconductor component includes back side pin contacts fabricated using a circuit side fabrication method. The component also includes a thinned semiconductor die having a pattern of die contacts, and conductive members formed by filled openings in the die contacts and the die. In addition, the pin contacts are formed by terminal portions of the conductive members. The fabrication method includes the steps of forming the openings and the conductive members, and then thinning and etching the die to form the pin contacts. An alternate embodiment female component includes female conductive members configured to physically and electrically engage pin contacts on a mating component of a stacked assembly.
摘要翻译：半导体部件包括使用电路侧制造方法制造的后侧引脚触点。该部件还包括具有模接触图案的薄化半导体管芯，以及由管芯接触件和管芯中的填充开口形成的导电部件。此外，引脚触点由导电构件的端子部分形成。制造方法包括形成开口和导电构件的步骤，然后使模具变薄和蚀刻以形成引脚触点。替代实施例的阴部件包括阴导电部件，其被配置为物理地和电接合堆叠组件的配合部件上的销触点。

29. 发明授权

US06784046B2 Method of making vertical diode structures 失效
标题翻译：制造垂直二极管结构的方法
公开(公告)号：US06784046B2
公开(公告)日：2004-08-31
申请号：US10104240
申请日：2002-03-22
申请人： Fernando Gonzalez , Tyler A. Lowrey , Trung Tri Doan , Raymond A. Turi , Graham R. Wolstenholme
发明人： Fernando Gonzalez , Tyler A. Lowrey , Trung Tri Doan , Raymond A. Turi , Graham R. Wolstenholme
IPC分类号： H01L218234
CPC分类号： H01L21/02667 , H01L21/02532 , H01L21/2022 , H01L27/0814 , H01L27/101 , H01L27/1021 , H01L27/24 , H01L29/6609 , H01L29/66136 , H01L29/861 , H01L45/04 , H01L45/145 , Y10S257/903 , Y10S257/91 , Y10S438/979
摘要： A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.
摘要翻译：提供了一种制造垂直二极管的方法，所述垂直二氧化物具有与其相连的二极管开口，其延伸穿过绝缘层并接触硅晶片上的有源区。硅化钛层覆盖二极管开口的内表面并接触有源区。二极管开口最初填充有非晶硅插塞，其在沉积期间被掺杂，随后再结晶以形成大晶粒多晶硅。硅插头具有重掺杂有第一类型掺杂剂的顶部部分和轻掺杂有第二类型掺杂剂的底部部分。顶部由底部界定，以便不与硅化钛层接触。对于垂直二极管的一个实施例，可编程电阻器接触硅插头的顶部并且金属线接触可编程电阻器。

30. 发明授权

US06743699B1 Method of fabricating semiconductor components 失效
标题翻译：制造半导体元件的方法
公开(公告)号：US06743699B1
公开(公告)日：2004-06-01
申请号：US10349220
申请日：2003-01-21
申请人： Trung Tri Doan
发明人： Trung Tri Doan
IPC分类号： H01L21301
CPC分类号： H01L24/97 , H01L21/56 , H01L21/78 , H01L23/3121 , H01L2924/01033 , H01L2924/12044 , H01L2924/14
摘要： A plurality of semiconductor dice are provided on a substrate having a first side and a second side, with the semiconductor dice being spaced from one another by scribe line area. A stencil is positioned over at least one of the first side and the second side of the substrate. The stencil has masking sections which cover at least portions of the scribe line area. A polymer is applied through the positioned stencil onto the first or second side of the substrate over which the stencil is received, with the stencil substantially precluding the polymer from being applied on the covered portions of the scribe line area. After the applying, portions of the scribe line area are cut into and the plurality of dice are singulated from the substrate. Other aspects and implementations are contemplated.
摘要翻译：多个半导体管芯设置在具有第一侧和第二侧的基板上，半导体管芯通过划线区域相互间隔开。模板位于衬底的第一侧和第二侧中的至少一个上方。模板具有覆盖划线区域的至少一部分的掩模部分。通过定位的模板将聚合物施加到基材的第一或第二侧上，在其上容纳模版的模板，模版基本上阻止聚合物施加在划线区域的覆盖部分上。在施加之后，切割部分划线区域并将多个骰子从衬底分离。考虑了其他方面和实现。

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