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21. 发明授权

US6055623A Specialized millicode instruction for editing functions 失效
标题翻译：专用的millicode指令用于编辑功能
公开(公告)号：US6055623A
公开(公告)日：2000-04-25
申请号：US56344
申请日：1998-04-07
申请人： Charles Franklin Webb , Judy Shan-Shan Chen Johnson
发明人： Charles Franklin Webb , Judy Shan-Shan Chen Johnson
IPC分类号： G06F9/38 , G06F9/22 , G06F9/28 , G06F9/30 , G06F9/302 , G06F9/305 , G06F9/308 , G06F9/318 , G06F9/32
CPC分类号： G06F9/3822 , G06F9/3001 , G06F9/30018 , G06F9/30029 , G06F9/30094 , G06F9/30145 , G06F9/3017 , G06F9/30181
摘要： A computer system having a pipelined computer processor, which executes a relatively simple instruction set in a hardware controlled execution unit and executes a relatively complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in said hardware controlled execution unit, a millicode operating in a milli-mode state when macro-mode decoding by said processor is suspended to cause the system to subsequently use processor milli-registers and the processor's decoder decodes them and schedules them for execution upon entry into the processor milli-mode. Millicode flags allow specialized update and branch instructions and flags are either cleared or specifically set for a millicode instruction. A millicode instruction for editing functions processes one byte of an input pattern string, generates one byte of an output string, and updates various pointers and state indications to prepare for processing the next byte in a string. Translate Fetch (TRFET) millicode instructions support a Translate and Test TRT instruction and specialized millicode instructions for packed decimal division make use of the hardware control and dataflow logic designed to support simpler packed decimal operations including Add to provide operand access, checking, preparation, and storing functions, and to generate the quotient digits as needed for the DP instruction are implemented as as internal code instructions, rather than implementing the entire DP function in hardware, and control is maintained in internal code allowing simpler handling of unusual and boundary conditions.
摘要翻译：一种具有流水线计算机处理器的计算机系统，其在硬件控制执行单元中执行相对简单的指令集，并且在所述硬件控制的执行单元中以简单指令的毫位序列在毫模式架构状态下执行相对复杂的指令集，当所述处理器的宏模式解码被暂停以使得系统随后使用处理器毫秒寄存器并且处理器的解码器对它们进行解码并在进入处理器毫模式时进行调度以进行执行，则以毫模式状态工作的微代码。 Millicode标志允许专门的更新和分支指令和标志被清除或专门设置为一个millicode指令。用于编辑功能的millicode指令处理输入模式字符串的一个字节，生成输出字符串的一个字节，并更新各种指针和状态指示，以准备处理字符串中的下一个字节。 Translate Fetch（TRFET）millicode指令支持翻译和测试TRT指令和专门的millicode指令，用于打包十进制分割，使用硬件控制和数据流逻辑，用于支持更简单的打包十进制操作，包括添加以提供操作数访问，检查，准备和存储功能，并根据DP指令的需要生成商数字，作为内部代码指令而实现，而不是在硬件中实现整个DP功能，并且内部代码中的控制保持在更简单的处理异常和边界条件中。

22. 发明授权

US5687106A Implementation of binary floating point using hexadecimal floating point unit 失效
标题翻译：使用十六进制浮点单元实现二进制浮点数
公开(公告)号：US5687106A
公开(公告)日：1997-11-11
申请号：US414250
申请日：1995-03-31
申请人： Eric Mark Schwarz , Charles Franklin Webb , Kai-Ann Ho
发明人： Eric Mark Schwarz , Charles Franklin Webb , Kai-Ann Ho
IPC分类号： G06F7/57 , G06F7/38 , G06F7/00
CPC分类号： G06F7/483 , G06F2207/3844 , G06F7/49957
摘要： A computer system supporting multiple floating point architectures. In an embodiment of the invention, a floating point unit (FPU) is optimized for hex format. The FPU uses a hex internal dataflow with a with an exponent and bias sufficient to support a binary floating point architecture. The FPU includes format conversion means, rounding means, sticky bit calculation means, and special number control means to execute binary floating point operations according to the IEEE 754 standard. An embodiment of the invention provides a system for executing floating point operations in either IBM S/390 hexadecimal format or IEEE 754 binary format.
摘要翻译：支持多种浮点架构的计算机系统。在本发明的实施例中，针对十六进制格式优化了浮点单元（FPU）。 FPU使用十六进制内部数据流，其中指数和偏差足以支持二进制浮点架构。 FPU包括格式转换装置，舍入装置，粘点计算装置和专用号码控制装置，以根据IEEE 754标准执行二进制浮点运算。本发明的实施例提供了一种用于以IBM S / 390十六进制格式或IEEE 754二进制格式执行浮点运算的系统。

23. 发明授权

US5802359A Mapping processor state into a millicode addressable processor state register array 失效
标题翻译：将处理器状态映射到一个可编址的处理器状态寄存器阵列中
公开(公告)号：US5802359A
公开(公告)日：1998-09-01
申请号：US892068
申请日：1997-07-14
申请人： Charles Franklin Webb , Mark Steven Farrell
发明人： Charles Franklin Webb , Mark Steven Farrell
IPC分类号： G06F9/318 , G06F9/32 , G06F9/38 , G06F9/06
CPC分类号： G06F9/3017 , G06F9/30094 , G06F9/3861
摘要： A milli-mode system has a processor state unit (R-unit) with register space into which those system operating registers and control latches, which make up the processor architected state, are mapped. This processor state unit, which includes a processor state register array and associated controls, receives all state updates from the processor as data and register addresses.
摘要翻译：毫微模式系统具有具有寄存器空间的处理器状态单元（R单元），构成处理器架构状态的那些系统操作寄存器和控制锁存器被映射到其中。该处理器状态单元包括处理器状态寄存器阵列和相关联的控制，从处理器接收作为数据和寄存器地址的所有状态更新。

24. 发明授权

US5694617A System for prioritizing quiesce requests and recovering from a quiescent state in a multiprocessing system with a milli-mode operation 失效
标题翻译：用于优先处理静默请求的系统，以及在具有毫模式操作的多处理系统中从静止状态恢复的系统
公开(公告)号：US5694617A
公开(公告)日：1997-12-02
申请号：US414975
申请日：1995-03-31
申请人： Charles Franklin Webb , Janet Rhea Easton , Mark Steven Farrell , Ming H. Cheung
发明人： Charles Franklin Webb , Janet Rhea Easton , Mark Steven Farrell , Ming H. Cheung
IPC分类号： G06F11/14 , G06F11/00 , G06F13/00
CPC分类号： G06F11/1405
摘要： A milli-mode routine handles a quiesce interrupt, and causes all the processors in the system to enter a quiesced state. A single bit of a millicode control register indicates a quiesced state and drives an output of the processor to indicate the processor is in a quiesced state. The processor receives a signal indicating all processors in the system are in a quiesced state and latches this value. The output of this latch is sent to the processor instruction unit for use as a millicode branch condition.
摘要翻译：毫秒模式例程处理静默中断，并使系统中的所有处理器进入静态状态。毫秒级控制寄存器的一位指示静止状态，并驱动处理器的输出以指示处理器处于静默状态。处理器接收到指示系统中的所有处理器处于静止状态并锁存该值的信号。该锁存器的输出被发送到处理器指令单元以用作毫分支条件。

25. 发明授权

US08880805B2 Computer system having cache subsystem performing demote requests 有权
标题翻译：具有缓存子系统的计算机系统执行降级请求
公开(公告)号：US08880805B2
公开(公告)日：2014-11-04
申请号：US13105235
申请日：2011-05-11
申请人： Chung-Lung Kevin Shum , Kathryn Marie Jackson , Charles Franklin Webb
发明人： Chung-Lung Kevin Shum , Kathryn Marie Jackson , Charles Franklin Webb
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F3/0614 , G06F3/064 , G06F3/0679 , G06F12/0802 , G06F12/0811 , G06F12/0817 , G06F12/0833 , G06F12/0837 , G06F12/0842 , G06F12/0875 , G06F12/128 , G06F2212/1016 , G06F2212/283 , G06F2212/314 , G06F2212/452 , G06F2212/6042 , G06F2212/621 , G06F2212/69
摘要： Computer system having cache subsystem wherein demote requests are performed by the cache subsystem. Software indicates to hardware of a processing system that its storage modification to a particular cache line is done, and will not be doing any modification for the time being. With this indication, the processor actively releases its exclusive ownership by updating its line ownership from exclusive to read-only (or shared) in its own cache directory and in the storage controller (SC). By actively giving up the exclusive rights, another processor can immediately be given exclusive ownership to that said cache line without waiting on any processor's explicit cross invalidate acknowledgement. This invention also describes the hardware design needed to provide this support.
摘要翻译：具有缓存子系统的计算机系统，其中降级请求由高速缓存子系统执行。软件向处理系统的硬件指示其对特定高速缓存行的存储修改已完成，并且暂时不进行任何修改。有了这个指示，处理器通过将其所有权从排他性更新到其自己的高速缓存目录和存储控制器（SC）中的只读（或共享）来主动释放其独占所有权。通过积极放弃专有权，另一个处理器可以立即被给予所述高速缓存行的独占所有权，而不用等待任何处理器的明确的交叉无效确认。本发明还描述了提供此支持所需的硬件设计。

26. 发明申请

US20120124292A1 Computer System Having Cache Subsystem Performing Demote Requests 有权
标题翻译：具有缓存子系统的计算机系统执行降级请求
公开(公告)号：US20120124292A1
公开(公告)日：2012-05-17
申请号：US13105235
申请日：2011-05-11
申请人： Chung-Lung Kevin Shum , Kathryn Marie Jackson , Charles Franklin Webb
发明人： Chung-Lung Kevin Shum , Kathryn Marie Jackson , Charles Franklin Webb
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F3/0614 , G06F3/064 , G06F3/0679 , G06F12/0802 , G06F12/0811 , G06F12/0817 , G06F12/0833 , G06F12/0837 , G06F12/0842 , G06F12/0875 , G06F12/128 , G06F2212/1016 , G06F2212/283 , G06F2212/314 , G06F2212/452 , G06F2212/6042 , G06F2212/621 , G06F2212/69
摘要： Computer system having cache subsystem wherein demote requests are performed by the cache subsystem. Software indicates to hardware of a processing system that its storage modification to a particular cache line is done, and will not be doing any modification for the time being. With this indication, the processor actively releases its exclusive ownership by updating its line ownership from exclusive to read-only (or shared) in its own cache directory and in the storage controller (SC). By actively giving up the exclusive rights, another processor can immediately be given exclusive ownership to that said cache line without waiting on any processor's explicit cross invalidate acknowledgement. This invention also describes the hardware design needed to provide this support.
摘要翻译：具有缓存子系统的计算机系统，其中降级请求由高速缓存子系统执行。软件向处理系统的硬件指示其对特定高速缓存行的存储修改已完成，并且暂时不进行任何修改。有了这个指示，处理器通过将其所有权从排他性更新到其自己的高速缓存目录和存储控制器（SC）中的只读（或共享）来主动释放其独占所有权。通过积极放弃专有权，另一个处理器可以立即被给予所述高速缓存行的独占所有权，而不用等待任何处理器的明确的交叉无效确认。本发明还描述了提供此支持所需的硬件设计。

27. 发明授权

US06233655B1 Method for Quad-word Storing into 2-way interleaved L1 cache 失效
标题翻译：用于四字存储到双向交错L1缓存的方法
公开(公告)号：US06233655B1
公开(公告)日：2001-05-15
申请号：US09070146
申请日：1998-04-30
申请人： Chung-Lung Kevin Shum , Wen He Li , Charles Franklin Webb
发明人： Chung-Lung Kevin Shum , Wen He Li , Charles Franklin Webb
IPC分类号： G06F1200
CPC分类号： G06F9/30043 , G06F12/0851 , G06F12/0886
摘要： A computer processor has an I-unit (instruction unit) and instruction decoder, an E-unit (execution unit), a Buffer Control Element (BCE) containing a unified two-way interleaved L1 cache and providing write control to said two-way interleaved L1 cache. The processor has Double Word wide execution dataflow. An instruction decoder receiving instruction data from a unified cache before decoding causes, for stores, I-unit logic to initiate a request ahead of execution to tell the buffer control element that stores will be made from the E-unit, and E-unit logic sends a store request to initiate a store after decoding corresponding instruction data which indicates what address in the cache the DoubleWord data is to be stored to. In the process, E-unit logic calculates, from source and destination address information address ranges information in an instruction, whether a corresponding multi-Double Word store with same byte data will result from the data patterns, and, when a multi-Double Word store could result, it enables the E-unit to request the writing of an incoming Double Word on the computer's data bus for both Double Word L1 cache interleaves using the same address for both to effectively write two consecutively addressed DoubleWords for the same cycle to achieve a Quad Word store in a cycle.
摘要翻译：计算机处理器具有I单元（指令单元）和指令解码器，E单元（执行单元），包含统一双向交错L1高速缓存的缓冲器控制元件（BCE），并向所述双向交错L1缓存。处理器具有双字宽执行数据流。在解码之前从统一高速缓存器接收指令数据的指令解码器使存储I单元逻辑在执行之前启动请求以告知缓冲器控制元件将从E单元进行存储，并且E单元逻辑在对相应的指令数据进行解码之后发送存储请求，以指示高速缓存中要存储的DoubleWord数据的哪个地址。在该过程中，E单元逻辑根据指令中的源地址信息和目的地址信息地址范围信息，计算出数据模式是否产生具有相同字节数据的对应多双字存储，以及当多单字存储可能导致，它使E单元能够使用相同的地址在计算机的数据总线上请求输入双字的双字L1高速缓存交错，以便在相同周期内有效地写入两个连续寻址的DoubleWords来实现一个四周商店在一个循环。

28. 发明授权

US06058470A Specialized millicode instruction for translate and test 失效
标题翻译：专业的millicode指令进行翻译和测试
公开(公告)号：US06058470A
公开(公告)日：2000-05-02
申请号：US56484
申请日：1998-04-07
申请人： Charles Franklin Webb , Mark Steven Farrell
发明人： Charles Franklin Webb , Mark Steven Farrell
IPC分类号： G06F9/22 , G06F9/28 , G06F9/30 , G06F9/302 , G06F9/308 , G06F9/318 , G06F9/32
CPC分类号： G06F9/30014 , G06F9/30018 , G06F9/30036 , G06F9/30094 , G06F9/3017
摘要： A computer system having a pipelined computer processor, which executes a relatively simple instruction set in a hardware controlled execution unit and executes a relatively complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in said hardware controlled execution unit, a millicode operating in a milli-mode state when macro-mode decoding by said processor is suspended to cause the system to subsequently use processor milli-registers and the processor's decoder decodes them and schedules them for execution upon entry into the processor milli-mode. Millicode flags allow specialized update and branch instructions and flags are either cleared or specifically set for a millicode instruction. A millicode instruction for editing functions processes one byte of an input pattern string, generates one byte of an output string, and updates various pointers and state indications to prepare for processing the next byte in a string. Translate Fetch (TRFET) millicode instructions support a Translate and Test TRT instruction and specialized millicode instructions for packed decimal division make use of the hardware control and dataflow logic designed to support simpler packed decimal operations including Add to provide operand access, checking, preparation, and storing functions, and to generate the quotient digits as needed for the DP instruction are implemented as as internal code instructions, rather than implementing the entire DP function in hardware, and control is maintained in internal code allowing simpler handling of unusual and boundary conditions.
摘要翻译：一种具有流水线计算机处理器的计算机系统，其在硬件控制执行单元中执行相对简单的指令集，并且在所述硬件控制的执行单元中以简单指令的毫位序列在毫模式架构状态下执行相对复杂的指令集，当所述处理器的宏模式解码被暂停以使得系统随后使用处理器毫秒寄存器并且处理器的解码器对它们进行解码并在进入处理器毫模式时进行调度以进行执行，则以毫模式状态工作的微代码。 Millicode标志允许专门的更新和分支指令和标志被清除或专门设置为一个millicode指令。用于编辑功能的millicode指令处理输入模式字符串的一个字节，生成输出字符串的一个字节，并更新各种指针和状态指示，以准备处理字符串中的下一个字节。 Translate Fetch（TRFET）millicode指令支持翻译和测试TRT指令和专门的millicode指令，用于打包十进制分割，使用硬件控制和数据流逻辑来设计，以支持更简单的打包十进制操作，包括添加以提供操作数访问，检查，准备和存储功能，并根据DP指令的需要生成商数字，作为内部代码指令而实现，而不是在硬件中实现整个DP功能，并且内部代码中的控制保持在更简单的处理异常和边界条件中。

29. 发明授权

US5754810A Specialized millicode instruction for certain decimal operations 失效
标题翻译：专用millicode指令，用于某些小数操作
公开(公告)号：US5754810A
公开(公告)日：1998-05-19
申请号：US614249
申请日：1996-03-12
申请人： Charles Franklin Webb , Mark Steven Farrell , Charles Lewis Cross , Nishit Hemantkumar Gokli , Wen He Li
发明人： Charles Franklin Webb , Mark Steven Farrell , Charles Lewis Cross , Nishit Hemantkumar Gokli , Wen He Li
IPC分类号： G06F5/00 , G06F3/00
CPC分类号： G06F5/00
摘要： A millicode method for packing the hexadecimal digits from a plurality of bytes in each of two millicode registers (R1,R1) into one of the two millicode registers extracts the rightmost hexadecimal digit from each of a plurality of bytes stored in millicode register R1 and the rightmost hexadecimal digit from each of a plurality of bytes stored in millicode register R2 and stores hexadecimal digits from said extracting step in millicode register R1 with each hexadecimal digit extracted from a byte in register R1 and from a byte in register R2 stored in millicode register R1 in register R1 positions occupied by said plurality of bytes stored in register R1 prior to said extraction step.
摘要翻译：用于将两个毫分
率寄存器（R1，R1）中的每一个中的多个字节中的十六进制数十进制数十进制数组合到一个两个毫分
率寄存器中，从存储在毫秒寄存器R1中的多个字节中的每一个提取最右边的十六进制数字，存储在毫秒寄存器R2中的多个字节中的每一个的最右边的十六进制数字，并且存储从存储在寄存器R1中的字节中提取的每个十六进制数字和存储在毫秒寄存器R1中的寄存器R2中的字节的来自所述提取步骤的十六进制数字在所述提取步骤之前，在存储在寄存器R1中的所述多个字节占据的寄存器R1位置。

30. 发明申请

US20090157965A1 Method and Apparatus for Active Software Disown of Cache Line's Exlusive Rights 有权
标题翻译：用于主动软件的方法和设备降低缓存线的隐藏权限
公开(公告)号：US20090157965A1
公开(公告)日：2009-06-18
申请号：US11954374
申请日：2007-12-12
申请人： Chung-Lung Kevin Shum , Kathryn Marie Jackson , Charles Franklin Webb
发明人： Chung-Lung Kevin Shum , Kathryn Marie Jackson , Charles Franklin Webb
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F3/0614 , G06F3/064 , G06F3/0679 , G06F12/0802 , G06F12/0811 , G06F12/0817 , G06F12/0833 , G06F12/0837 , G06F12/0842 , G06F12/0875 , G06F12/128 , G06F2212/1016 , G06F2212/283 , G06F2212/314 , G06F2212/452 , G06F2212/6042 , G06F2212/621 , G06F2212/69
摘要： Software indicates to hardware of a processing system that its storage modification to a particular cache line is done, and will not be doing any modification for the time being. With this indication, the processor actively releases its exclusive ownership by updating its line ownership from exclusive to read-only (or shared) in its own cache directory and in the storage controller (SC). By actively giving up the exclusive rights, another processor can immediately be given exclusive ownership to that said cache line without waiting on any processor's explicit cross invalidate acknowledgement. This invention also describes the hardware design needed to provide this support.
摘要翻译：软件向处理系统的硬件指示其对特定高速缓存行的存储修改已完成，并且暂时不进行任何修改。有了这个指示，处理器通过将其所有权从排他性更新到其自己的高速缓存目录和存储控制器（SC）中的只读（或共享）来主动释放其独占所有权。通过积极放弃专有权，另一个处理器可以立即被给予所述高速缓存行的独占所有权，而不用等待任何处理器的明确的交叉无效确认。本发明还描述了提供此支持所需的硬件设计。

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