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1. 发明授权

US5754810A Specialized millicode instruction for certain decimal operations 失效
标题翻译：专用millicode指令，用于某些小数操作
公开(公告)号：US5754810A
公开(公告)日：1998-05-19
申请号：US614249
申请日：1996-03-12
申请人： Charles Franklin Webb , Mark Steven Farrell , Charles Lewis Cross , Nishit Hemantkumar Gokli , Wen He Li
发明人： Charles Franklin Webb , Mark Steven Farrell , Charles Lewis Cross , Nishit Hemantkumar Gokli , Wen He Li
IPC分类号： G06F5/00 , G06F3/00
CPC分类号： G06F5/00
摘要： A millicode method for packing the hexadecimal digits from a plurality of bytes in each of two millicode registers (R1,R1) into one of the two millicode registers extracts the rightmost hexadecimal digit from each of a plurality of bytes stored in millicode register R1 and the rightmost hexadecimal digit from each of a plurality of bytes stored in millicode register R2 and stores hexadecimal digits from said extracting step in millicode register R1 with each hexadecimal digit extracted from a byte in register R1 and from a byte in register R2 stored in millicode register R1 in register R1 positions occupied by said plurality of bytes stored in register R1 prior to said extraction step.
摘要翻译：用于将两个毫分
率寄存器（R1，R1）中的每一个中的多个字节中的十六进制数十进制数十进制数组合到一个两个毫分
率寄存器中，从存储在毫秒寄存器R1中的多个字节中的每一个提取最右边的十六进制数字，存储在毫秒寄存器R2中的多个字节中的每一个的最右边的十六进制数字，并且存储从存储在寄存器R1中的字节中提取的每个十六进制数字和存储在毫秒寄存器R1中的寄存器R2中的字节的来自所述提取步骤的十六进制数字在所述提取步骤之前，在存储在寄存器R1中的所述多个字节占据的寄存器R1位置。

2. 发明授权

US5819078A Addressing extended memory using millicode by concatenating a small millicode address and address extension data 失效
标题翻译：通过连接小的millicode地址和地址扩展数据来寻址使用millicode的扩展内存
公开(公告)号：US5819078A
公开(公告)日：1998-10-06
申请号：US872048
申请日：1997-06-10
申请人： Mark Steven Farrell , Barry Watson Krumm , Jennifer Serena Almoradie Navarro , Charles Franklin Webb
发明人： Mark Steven Farrell , Barry Watson Krumm , Jennifer Serena Almoradie Navarro , Charles Franklin Webb
IPC分类号： G06F9/318 , G06F9/355 , G06F12/06
CPC分类号： G06F9/342 , G06F9/30036 , G06F9/3017
摘要： A millicode instruction loads a millicode address extension register with extended address bits, and an operand access control register that signals when a logical address is to be extended by the extra bits, and when it should be treated as only a 31 bit address.
摘要翻译：一个millicode指令加载一个扩展地址位的millicode地址扩展寄存器和一个操作数访问控制寄存器，用于在逻辑地址扩展一个额外的位时发出信号，当它被当作只有一个31位的地址时。

3. 发明授权

US5694587A Specialized millicode instructions for test PSW validity, load with access test, and character translation assist 失效
标题翻译：测试PSW有效性的专用millicode指令，访问测试负载和字符翻译辅助
公开(公告)号：US5694587A
公开(公告)日：1997-12-02
申请号：US414154
申请日：1995-03-31
申请人： Charles Franklin Webb , Mark Steven Farrell , Mark Anthony Check , John Stephen Liptay
发明人： Charles Franklin Webb , Mark Steven Farrell , Mark Anthony Check , John Stephen Liptay
IPC分类号： G06F9/30 , G06F9/305 , G06F9/318 , G06F9/38 , G06F11/07
CPC分类号： G06F9/3865 , G06F11/0721 , G06F11/0751 , G06F9/30029 , G06F9/30087 , G06F9/30145 , G06F9/3017 , G06F9/30189
摘要： A pipelined computer processor in a milli-mode architected state tests the validity of a program status word with a mask stored in a millicode general register. The mask indicates bits in the program status word which are to be zeros if the word is valid. A logical AND operation is performed between correspondingly positioned bits in the word and bits in the mask and in addition the status of at least one other bit in the word is checked, a bit other than a correspondingly positioned bit.
摘要翻译：在毫模式架构状态下的流水线计算机处理器使用存储在毫通通用寄存器中的掩码测试程序状态字的有效性。掩码表示程序状态字中的位，如果该字有效，则它们将为零。在字中的相应位置的位和掩码中的位之间执行逻辑“与”运算，另外检查字中的至少一个其他位的状态，除了对应定位的位之外的位。

4. 发明授权

US5790844A Millicode load and test access instruction that blocks interrupts in response to access exceptions 失效
标题翻译： Millicode加载和测试访问指令阻止中断响应访问异常
公开(公告)号：US5790844A
公开(公告)日：1998-08-04
申请号：US829268
申请日：1997-03-31
申请人： Charles Franklin Webb , Mark Steven Farrell , Mark Anthony Check , John Stephen Liptay
发明人： Charles Franklin Webb , Mark Steven Farrell , Mark Anthony Check , John Stephen Liptay
IPC分类号： G06F9/30 , G06F9/305 , G06F9/318 , G06F9/38 , G06F11/07
CPC分类号： G06F9/3865 , G06F11/0721 , G06F11/0751 , G06F9/30029 , G06F9/30087 , G06F9/30145 , G06F9/3017 , G06F9/30189
摘要： A special inillicode instruction "Load With Access Test" explicitly detects access exceptions for storage operands while retaining control in the current millicode routine to insure exceptions are handled correctly and with the right priority. The millicode Load With Access Test instruction operates similarly to the ESA/390 Load instruction except that access exception code is set, interrupts are blocked and the serialization is forced to purge the instruction pipeline and reset the pipeline control without redirection of the instruction stream.
摘要翻译：一个特殊的initicode指令“加载访问测试”显式检测存储操作数的访问异常，同时保留当前millicode例程中的控制，以确保正确处理异常并以正确的优先级。除了访问异常代码被设置，中断被阻止并且串行化被强制清除指令流水线并重新设置流水线控制而不重定向指令流之外，Millicode加载与访问测试指令的操作类似于ESA / 390加载指令。

5. 发明授权

US5673391A Hardware retry trap for millicoded processor 失效
标题翻译：用于毫米处理器的硬件重试陷阱
公开(公告)号：US5673391A
公开(公告)日：1997-09-30
申请号：US414977
申请日：1995-03-31
申请人： Charles Franklin Webb , Mark Steven Farrell , Scott Barnett Swaney
发明人： Charles Franklin Webb , Mark Steven Farrell , Scott Barnett Swaney
IPC分类号： G06F11/14 , G06F11/34
CPC分类号： G06F11/1405
摘要： Retry trap in the processor system detects the occurrence of a hardware retry during a millicode routine. In operation, millicode resets the retry trap to "O" at the start of a millicode sequence that is sensitive to a retry operation being at some stage of the millicode sequence. The millicode routine tests the retry latch state at one or more points in the sequence to determine if a retry has occurred since the start of the sequence, which is sensitive to a retry operation. The action taken in response to a determination that a retry operation has occurred depends upon the type of potential damage to the system state as a result of the occurrence of the retry operation during the millicode sequence.
摘要翻译：处理器系统中的重试陷阱在毫秒代码程序期间检测硬件重试的发生。在操作中，millicode在对于在millicode序列的某个阶段的重试操作敏感的millicode序列开始时将重试陷阱重置为“O”。 millicode例程测试序列中一个或多个点处的重试锁存状态，以确定自从启动重试操作以来是否发生了重试。响应于重试操作已经发生的确定而采取的动作取决于在毫秒序列期间发生重试操作的结果对系统状态的潜在损害的类型。

6. 发明授权

US6125444A Millimode capable computer system providing global branch history table disables and separate millicode disables which enable millicode disable to be turned off for some sections of code execution but not disabled for all 失效
标题翻译：提供全球分支历史表的具有Millimode功能的计算机系统禁用和分离的millicode禁用，这使得可以关闭某些代码段但不对所有的代码执行millicode禁用
公开(公告)号：US6125444A
公开(公告)日：2000-09-26
申请号：US70201
申请日：1998-04-30
申请人： Mark Anthony Check , John Stephen Liptay , Timothy John Slegel , Charles Franklin Webb , Mark Steven Farrell
发明人： Mark Anthony Check , John Stephen Liptay , Timothy John Slegel , Charles Franklin Webb , Mark Steven Farrell
IPC分类号： G06F9/22 , G06F9/26 , G06F9/38
CPC分类号： G06F9/3844
摘要： A millimode capable computer system provides control to millicode to allow the BHT operations to continue except when the these special situations occur that require control of instruction fetch operations must be provided and the BHT can be turned off for some sections of code execution, but not disabled for all. A single free running BHT functions for both a normal mode and a millimode for the central processor which can execute in millimode with a branch history table directing instruction fetch for which both a global BHT disable and millicode disables exist. Hit detection logic receives input from the global BHT disable, as well as from an initialized control register bit and a processor control register bit to select the correct set target information and generate a "branch history table hit detected" control signal.
摘要翻译：具有毫米级功能的计算机系统提供对millicode的控制以允许BHT操作继续，除非出现这些特殊情况需要提供指令提取操作的控制，并且BHT可以在某些代码执行部分被关闭但不被禁用对全部。单个免费运行的BHT功能可用于中央处理器的正常模式和毫模式，可以以毫米模式执行，其中分支历史表指示全局BHT禁用和毫代码禁用两者之间存在禁用指令的指令提取。命中检测逻辑接收来自全局BHT禁用的输入，以及从初始化的控制寄存器位和处理器控制寄存器位选择正确的设置目标信息并生成“检测到分支历史表命中”控制信号。

7. 发明授权

US06079013A Multiprocessor serialization with early release of processors 失效
标题翻译：多处理器串行化与早期版本的处理器
公开(公告)号：US06079013A
公开(公告)日：2000-06-20
申请号：US70429
申请日：1998-04-30
申请人： Charles Franklin Webb , Dean G. Bair , Mark Steven Farrell , Barry Watson Krumm , Pak-kin Mak , Jennifer Almoradie Navarro , Timothy John Slegel
发明人： Charles Franklin Webb , Dean G. Bair , Mark Steven Farrell , Barry Watson Krumm , Pak-kin Mak , Jennifer Almoradie Navarro , Timothy John Slegel
IPC分类号： G06F9/52 , G06F9/318 , G06F12/06
CPC分类号： G06F9/30087 , G06F9/3004 , G06F9/3017
摘要： A pipelined multiprocessor system for ESA/390 operations which executes a simple instruction set in a hardware controlled execution unit and executes a complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in the hardware controlled execution unit, comprising a plurality of CPU processors each of which is part of said multiprocessing system and capable of generating and responding to a quiesce request, and controls for system operations which allow the CPUs in the ESA/390 system to process the local buffer update portion of IPTE and SSKE operations without waiting for all other processors to reach an interruptible point, and then to continue program execution with minor temporary restrictions on operations until the IPTE or SSKE operation is globally completed. In addition, Licensed Internal Code (LIC) sequences are defined which allow these IPTE and SSKE operations to co-exist with other operations which require conventional system quiescing (i.e. all processors must pause together), and to allow for CPU retry actions on any of the CPUs in the system at any point in the operation.
摘要翻译：一种用于ESA / 390操作的流水线多处理器系统，其执行硬件控制执行单元中的简单指令集，并且以硬模式设计状态以硬计算执行单元中的简单指令的毫位序列执行复指令集，包括多个CPU处理器，每个CPU处理器都是所述多处理系统的一部分并且能够产生和响应静默请求，并且控制允许ESA / 390系统中的CPU处理IPTE和SSKE的本地缓冲器更新部分的系统操作操作，而不等待所有其他处理器到达可中断点，然后继续执行程序，对操作进行轻微的临时限制，直到IPTE或SSKE操作全局完成。此外，定义了许可内码（LIC）序列，允许这些IPTE和SSKE操作与需要常规系统静止的其他操作（即，所有处理器必须暂停在一起）并存，并允许对任何 CPU在系统中的任何一点操作。

8. 发明授权

US06058470A Specialized millicode instruction for translate and test 失效
标题翻译：专业的millicode指令进行翻译和测试
公开(公告)号：US06058470A
公开(公告)日：2000-05-02
申请号：US56484
申请日：1998-04-07
申请人： Charles Franklin Webb , Mark Steven Farrell
发明人： Charles Franklin Webb , Mark Steven Farrell
IPC分类号： G06F9/22 , G06F9/28 , G06F9/30 , G06F9/302 , G06F9/308 , G06F9/318 , G06F9/32
CPC分类号： G06F9/30014 , G06F9/30018 , G06F9/30036 , G06F9/30094 , G06F9/3017
摘要： A computer system having a pipelined computer processor, which executes a relatively simple instruction set in a hardware controlled execution unit and executes a relatively complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in said hardware controlled execution unit, a millicode operating in a milli-mode state when macro-mode decoding by said processor is suspended to cause the system to subsequently use processor milli-registers and the processor's decoder decodes them and schedules them for execution upon entry into the processor milli-mode. Millicode flags allow specialized update and branch instructions and flags are either cleared or specifically set for a millicode instruction. A millicode instruction for editing functions processes one byte of an input pattern string, generates one byte of an output string, and updates various pointers and state indications to prepare for processing the next byte in a string. Translate Fetch (TRFET) millicode instructions support a Translate and Test TRT instruction and specialized millicode instructions for packed decimal division make use of the hardware control and dataflow logic designed to support simpler packed decimal operations including Add to provide operand access, checking, preparation, and storing functions, and to generate the quotient digits as needed for the DP instruction are implemented as as internal code instructions, rather than implementing the entire DP function in hardware, and control is maintained in internal code allowing simpler handling of unusual and boundary conditions.
摘要翻译：一种具有流水线计算机处理器的计算机系统，其在硬件控制执行单元中执行相对简单的指令集，并且在所述硬件控制的执行单元中以简单指令的毫位序列在毫模式架构状态下执行相对复杂的指令集，当所述处理器的宏模式解码被暂停以使得系统随后使用处理器毫秒寄存器并且处理器的解码器对它们进行解码并在进入处理器毫模式时进行调度以进行执行，则以毫模式状态工作的微代码。 Millicode标志允许专门的更新和分支指令和标志被清除或专门设置为一个millicode指令。用于编辑功能的millicode指令处理输入模式字符串的一个字节，生成输出字符串的一个字节，并更新各种指针和状态指示，以准备处理字符串中的下一个字节。 Translate Fetch（TRFET）millicode指令支持翻译和测试TRT指令和专门的millicode指令，用于打包十进制分割，使用硬件控制和数据流逻辑来设计，以支持更简单的打包十进制操作，包括添加以提供操作数访问，检查，准备和存储功能，并根据DP指令的需要生成商数字，作为内部代码指令而实现，而不是在硬件中实现整个DP功能，并且内部代码中的控制保持在更简单的处理异常和边界条件中。

9. 发明授权

US6119219A System serialization with early release of individual processor 失效
标题翻译：系统串行化与早期发布的单个处理器
公开(公告)号：US6119219A
公开(公告)日：2000-09-12
申请号：US70595
申请日：1998-04-30
申请人： Charles Franklin Webb , Dean G. Bair , Mark Steven Farrell , Barry Watson Krumm , Pak-kin Mak , Jennifer Almoradie Navarro , Timothy John Slegel
发明人： Charles Franklin Webb , Dean G. Bair , Mark Steven Farrell , Barry Watson Krumm , Pak-kin Mak , Jennifer Almoradie Navarro , Timothy John Slegel
IPC分类号： G06F15/177 , G06F9/30 , G06F9/318 , G06F9/38 , G06F9/52 , G06F9/00
CPC分类号： G06F9/3861 , G06F9/3004 , G06F9/30087 , G06F9/30101 , G06F9/3017 , G06F9/3834
摘要： A pipelined multiprocessor system for ESA/390 operations which executes a simple instruction set in a hardware controlled execution unit and executes a complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in the hardware controlled execution unit, comprising a plurality of CPU processors each of which is part of said multiprocessing system and capable of generating and responding to a quiesce request, and controls for system operations which allow the CPUs in the ESA/390 system to process the local buffer update portion of IPTE and SSKE operations without waiting for all other processors to reach an interruptible point, and then to continue program execution with minor temporary restrictions on operations until the IPTE or SSKE operation is globally completed. In addition, Licensed Internal Code (LIC) sequences are defined which allow these IPTE and SSKE operations to co-exist with other operations which require conventional system quiescing (i.e. all processors must pause together), and to allow for CPU retry actions on any of the CPUs in the system at any point in the operation.
摘要翻译：一种用于ESA / 390操作的流水线多处理器系统，其执行硬件控制执行单元中的简单指令集，并且以硬模式设计状态以硬计算执行单元中的简单指令的毫位序列执行复指令集，包括多个CPU处理器，每个CPU处理器都是所述多处理系统的一部分并且能够产生和响应静默请求，并且控制允许ESA / 390系统中的CPU处理IPTE和SSKE的本地缓冲器更新部分的系统操作操作，而不等待所有其他处理器到达可中断点，然后继续执行程序，对操作进行轻微的临时限制，直到IPTE或SSKE操作全局完成。此外，定义了许可内码（LIC）序列，允许这些IPTE和SSKE操作与需要常规系统静止的其他操作（即，所有处理器必须暂停在一起）并存，并允许对任何 CPU在系统中的任何一点操作。

10. 发明授权

US5802359A Mapping processor state into a millicode addressable processor state register array 失效
标题翻译：将处理器状态映射到一个可编址的处理器状态寄存器阵列中
公开(公告)号：US5802359A
公开(公告)日：1998-09-01
申请号：US892068
申请日：1997-07-14
申请人： Charles Franklin Webb , Mark Steven Farrell
发明人： Charles Franklin Webb , Mark Steven Farrell
IPC分类号： G06F9/318 , G06F9/32 , G06F9/38 , G06F9/06
CPC分类号： G06F9/3017 , G06F9/30094 , G06F9/3861
摘要： A milli-mode system has a processor state unit (R-unit) with register space into which those system operating registers and control latches, which make up the processor architected state, are mapped. This processor state unit, which includes a processor state register array and associated controls, receives all state updates from the processor as data and register addresses.
摘要翻译：毫微模式系统具有具有寄存器空间的处理器状态单元（R单元），构成处理器架构状态的那些系统操作寄存器和控制锁存器被映射到其中。该处理器状态单元包括处理器状态寄存器阵列和相关联的控制，从处理器接收作为数据和寄存器地址的所有状态更新。

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