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1. 发明授权

US6055623A Specialized millicode instruction for editing functions 失效
标题翻译：专用的millicode指令用于编辑功能
公开(公告)号：US6055623A
公开(公告)日：2000-04-25
申请号：US56344
申请日：1998-04-07
申请人： Charles Franklin Webb , Judy Shan-Shan Chen Johnson
发明人： Charles Franklin Webb , Judy Shan-Shan Chen Johnson
IPC分类号： G06F9/38 , G06F9/22 , G06F9/28 , G06F9/30 , G06F9/302 , G06F9/305 , G06F9/308 , G06F9/318 , G06F9/32
CPC分类号： G06F9/3822 , G06F9/3001 , G06F9/30018 , G06F9/30029 , G06F9/30094 , G06F9/30145 , G06F9/3017 , G06F9/30181
摘要： A computer system having a pipelined computer processor, which executes a relatively simple instruction set in a hardware controlled execution unit and executes a relatively complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in said hardware controlled execution unit, a millicode operating in a milli-mode state when macro-mode decoding by said processor is suspended to cause the system to subsequently use processor milli-registers and the processor's decoder decodes them and schedules them for execution upon entry into the processor milli-mode. Millicode flags allow specialized update and branch instructions and flags are either cleared or specifically set for a millicode instruction. A millicode instruction for editing functions processes one byte of an input pattern string, generates one byte of an output string, and updates various pointers and state indications to prepare for processing the next byte in a string. Translate Fetch (TRFET) millicode instructions support a Translate and Test TRT instruction and specialized millicode instructions for packed decimal division make use of the hardware control and dataflow logic designed to support simpler packed decimal operations including Add to provide operand access, checking, preparation, and storing functions, and to generate the quotient digits as needed for the DP instruction are implemented as as internal code instructions, rather than implementing the entire DP function in hardware, and control is maintained in internal code allowing simpler handling of unusual and boundary conditions.
摘要翻译：一种具有流水线计算机处理器的计算机系统，其在硬件控制执行单元中执行相对简单的指令集，并且在所述硬件控制的执行单元中以简单指令的毫位序列在毫模式架构状态下执行相对复杂的指令集，当所述处理器的宏模式解码被暂停以使得系统随后使用处理器毫秒寄存器并且处理器的解码器对它们进行解码并在进入处理器毫模式时进行调度以进行执行，则以毫模式状态工作的微代码。 Millicode标志允许专门的更新和分支指令和标志被清除或专门设置为一个millicode指令。用于编辑功能的millicode指令处理输入模式字符串的一个字节，生成输出字符串的一个字节，并更新各种指针和状态指示，以准备处理字符串中的下一个字节。 Translate Fetch（TRFET）millicode指令支持翻译和测试TRT指令和专门的millicode指令，用于打包十进制分割，使用硬件控制和数据流逻辑，用于支持更简单的打包十进制操作，包括添加以提供操作数访问，检查，准备和存储功能，并根据DP指令的需要生成商数字，作为内部代码指令而实现，而不是在硬件中实现整个DP功能，并且内部代码中的控制保持在更简单的处理异常和边界条件中。

2. 发明授权

US5790844A Millicode load and test access instruction that blocks interrupts in response to access exceptions 失效
标题翻译： Millicode加载和测试访问指令阻止中断响应访问异常
公开(公告)号：US5790844A
公开(公告)日：1998-08-04
申请号：US829268
申请日：1997-03-31
申请人： Charles Franklin Webb , Mark Steven Farrell , Mark Anthony Check , John Stephen Liptay
发明人： Charles Franklin Webb , Mark Steven Farrell , Mark Anthony Check , John Stephen Liptay
IPC分类号： G06F9/30 , G06F9/305 , G06F9/318 , G06F9/38 , G06F11/07
CPC分类号： G06F9/3865 , G06F11/0721 , G06F11/0751 , G06F9/30029 , G06F9/30087 , G06F9/30145 , G06F9/3017 , G06F9/30189
摘要： A special inillicode instruction "Load With Access Test" explicitly detects access exceptions for storage operands while retaining control in the current millicode routine to insure exceptions are handled correctly and with the right priority. The millicode Load With Access Test instruction operates similarly to the ESA/390 Load instruction except that access exception code is set, interrupts are blocked and the serialization is forced to purge the instruction pipeline and reset the pipeline control without redirection of the instruction stream.
摘要翻译：一个特殊的initicode指令“加载访问测试”显式检测存储操作数的访问异常，同时保留当前millicode例程中的控制，以确保正确处理异常并以正确的优先级。除了访问异常代码被设置，中断被阻止并且串行化被强制清除指令流水线并重新设置流水线控制而不重定向指令流之外，Millicode加载与访问测试指令的操作类似于ESA / 390加载指令。

3. 发明授权

US5673391A Hardware retry trap for millicoded processor 失效
标题翻译：用于毫米处理器的硬件重试陷阱
公开(公告)号：US5673391A
公开(公告)日：1997-09-30
申请号：US414977
申请日：1995-03-31
申请人： Charles Franklin Webb , Mark Steven Farrell , Scott Barnett Swaney
发明人： Charles Franklin Webb , Mark Steven Farrell , Scott Barnett Swaney
IPC分类号： G06F11/14 , G06F11/34
CPC分类号： G06F11/1405
摘要： Retry trap in the processor system detects the occurrence of a hardware retry during a millicode routine. In operation, millicode resets the retry trap to "O" at the start of a millicode sequence that is sensitive to a retry operation being at some stage of the millicode sequence. The millicode routine tests the retry latch state at one or more points in the sequence to determine if a retry has occurred since the start of the sequence, which is sensitive to a retry operation. The action taken in response to a determination that a retry operation has occurred depends upon the type of potential damage to the system state as a result of the occurrence of the retry operation during the millicode sequence.
摘要翻译：处理器系统中的重试陷阱在毫秒代码程序期间检测硬件重试的发生。在操作中，millicode在对于在millicode序列的某个阶段的重试操作敏感的millicode序列开始时将重试陷阱重置为“O”。 millicode例程测试序列中一个或多个点处的重试锁存状态，以确定自从启动重试操作以来是否发生了重试。响应于重试操作已经发生的确定而采取的动作取决于在毫秒序列期间发生重试操作的结果对系统状态的潜在损害的类型。

4. 发明授权

US07966453B2 Method and apparatus for active software disown of cache line's exlusive rights 有权
标题翻译：主动软件的方法和装置取消了缓存行的隐藏权限
公开(公告)号：US07966453B2
公开(公告)日：2011-06-21
申请号：US11954374
申请日：2007-12-12
申请人： Chung-Lung Kevin Shum , Kathryn Marie Jackson , Charles Franklin Webb
发明人： Chung-Lung Kevin Shum , Kathryn Marie Jackson , Charles Franklin Webb
IPC分类号： G06F13/00
CPC分类号： G06F12/084 , G06F3/0614 , G06F3/064 , G06F3/0679 , G06F12/0802 , G06F12/0811 , G06F12/0817 , G06F12/0833 , G06F12/0837 , G06F12/0842 , G06F12/0875 , G06F12/128 , G06F2212/1016 , G06F2212/283 , G06F2212/314 , G06F2212/452 , G06F2212/6042 , G06F2212/621 , G06F2212/69
摘要： Software indicates to hardware of a processing system that its storage modification to a particular cache line is done, and will not be doing any modification for the time being. With this indication, the processor actively releases its exclusive ownership by updating its line ownership from exclusive to read-only (or shared) in its own cache directory and in the storage controller (SC). By actively giving up the exclusive rights, another processor can immediately be given exclusive ownership to that said cache line without waiting on any processor's explicit cross invalidate acknowledgement. This invention also describes the hardware design needed to provide this support.
摘要翻译：软件向处理系统的硬件指示其对特定高速缓存行的存储修改已完成，并且暂时不进行任何修改。有了这个指示，处理器通过将其所有权从排他性更新到其自己的高速缓存目录和存储控制器（SC）中的只读（或共享）来主动释放其独占所有权。通过积极放弃专有权，另一个处理器可以立即被给予所述高速缓存行的独占所有权，而不用等待任何处理器的明确的交叉无效确认。本发明还描述了提供此支持所需的硬件设计。

5. 发明授权

US6105126A Address bit decoding for same adder circuitry for RXE instruction format with same XBD location as RX format and dis-jointed extended operation code 失效
标题翻译：地址比特解码用于RXE指令格式的相同加法器电路，具有与RX格式相同的XBD位置和解码的扩展操作码
公开(公告)号：US6105126A
公开(公告)日：2000-08-15
申请号：US70359
申请日：1998-04-30
申请人： Mark Anthony Check , Ronald M. Smith, Sr. , John Stephen Liptay , Eric Mark Schwarz , Timothy John Slegel , Charles Franklin Webb
发明人： Mark Anthony Check , Ronald M. Smith, Sr. , John Stephen Liptay , Eric Mark Schwarz , Timothy John Slegel , Charles Franklin Webb
IPC分类号： G06F9/355 , G06F9/30 , G06F9/318 , G06F9/38 , G06F9/34
CPC分类号： G06F9/355 , G06F9/30185
摘要： A computer processor floating point processor six cycle pipeline system where instruction text is fetched prior to the first cycle and decoded during the first cycle for the fetched particular instruction and the base (B) and index (X) register values are read for use in address generation. RXE Instructions are of the RX-type but extended by placing the extension of the operation code beyond the first four bytes of the instruction format and to assign the operation codes in such a way that the machine may determine the exact format from the first 8 bits of the operation code alone. ESA/390 instructions SS, RR; RX; S; RRE; RI; and the new RXE instructions have a format which can be used for fixed point processing as well as floating point processing where instructions of the RXE format have their R1, X2, B2, and D2 fields in the identical positions in said instruction register as in the RX format to enable the processor to determine from the first 8 bits of the operation code alone that an instruction being decoded is an RXE format instruction and the register indexed extensions of the RXE format instruction, after which it gates the correct information to said X-B-D adder. During the second cycle the address add of B+X+Displacement is performed and sent to the cache processor's, and during the third and fourth cycles the cache is respectively accessed and data is returned, and during a fifth cycle execution of the fetched instruction occurs with the result putaway in a sixth cycle.
摘要翻译：计算机处理器浮点处理器六循环流水线系统，其中指令文本在第一周期之前获取并且在第一周期期间被解码用于所提取的特定指令，并且基准（B）和索引（X）寄存器值被读取用于地址代。 RXE指令是RX型，但通过将操作码的扩展置于指令格式的前四个字节之外进行扩展，并以这样的方式分配操作码，使得机器可以从前8位确定确切的格式的操作代码。 ESA / 390指令SS，RR; RX; S; RRE; RI; 并且新的RXE指令具有可用于固定点处理以及浮点处理的格式，其中RXE格式的指令在所述指令寄存器中的相同位置具有其R1，X2，B2和D2字段，如 RX格式，使处理器能够从操作代码的前8位确定正在解码的指令是RXE格式指令和RXE格式指令的寄存器索引扩展，之后它将正确信息锁定到所述XBD加法器。在第二周期期间，执行B + X +位移的地址添加并发送到高速缓存处理器，并且在第三和第四周期期间，分别访问高速缓存并返回数据，并且在第五周期期间执行所取出的指令结果放在第六个周期。

6. 发明授权

US5819078A Addressing extended memory using millicode by concatenating a small millicode address and address extension data 失效
标题翻译：通过连接小的millicode地址和地址扩展数据来寻址使用millicode的扩展内存
公开(公告)号：US5819078A
公开(公告)日：1998-10-06
申请号：US872048
申请日：1997-06-10
申请人： Mark Steven Farrell , Barry Watson Krumm , Jennifer Serena Almoradie Navarro , Charles Franklin Webb
发明人： Mark Steven Farrell , Barry Watson Krumm , Jennifer Serena Almoradie Navarro , Charles Franklin Webb
IPC分类号： G06F9/318 , G06F9/355 , G06F12/06
CPC分类号： G06F9/342 , G06F9/30036 , G06F9/3017
摘要： A millicode instruction loads a millicode address extension register with extended address bits, and an operand access control register that signals when a logical address is to be extended by the extra bits, and when it should be treated as only a 31 bit address.
摘要翻译：一个millicode指令加载一个扩展地址位的millicode地址扩展寄存器和一个操作数访问控制寄存器，用于在逻辑地址扩展一个额外的位时发出信号，当它被当作只有一个31位的地址时。

7. 发明授权

US5694587A Specialized millicode instructions for test PSW validity, load with access test, and character translation assist 失效
标题翻译：测试PSW有效性的专用millicode指令，访问测试负载和字符翻译辅助
公开(公告)号：US5694587A
公开(公告)日：1997-12-02
申请号：US414154
申请日：1995-03-31
申请人： Charles Franklin Webb , Mark Steven Farrell , Mark Anthony Check , John Stephen Liptay
发明人： Charles Franklin Webb , Mark Steven Farrell , Mark Anthony Check , John Stephen Liptay
IPC分类号： G06F9/30 , G06F9/305 , G06F9/318 , G06F9/38 , G06F11/07
CPC分类号： G06F9/3865 , G06F11/0721 , G06F11/0751 , G06F9/30029 , G06F9/30087 , G06F9/30145 , G06F9/3017 , G06F9/30189
摘要： A pipelined computer processor in a milli-mode architected state tests the validity of a program status word with a mask stored in a millicode general register. The mask indicates bits in the program status word which are to be zeros if the word is valid. A logical AND operation is performed between correspondingly positioned bits in the word and bits in the mask and in addition the status of at least one other bit in the word is checked, a bit other than a correspondingly positioned bit.
摘要翻译：在毫模式架构状态下的流水线计算机处理器使用存储在毫通通用寄存器中的掩码测试程序状态字的有效性。掩码表示程序状态字中的位，如果该字有效，则它们将为零。在字中的相应位置的位和掩码中的位之间执行逻辑“与”运算，另外检查字中的至少一个其他位的状态，除了对应定位的位之外的位。

8. 发明授权

US5687106A Implementation of binary floating point using hexadecimal floating point unit 失效
标题翻译：使用十六进制浮点单元实现二进制浮点数
公开(公告)号：US5687106A
公开(公告)日：1997-11-11
申请号：US414250
申请日：1995-03-31
申请人： Eric Mark Schwarz , Charles Franklin Webb , Kai-Ann Ho
发明人： Eric Mark Schwarz , Charles Franklin Webb , Kai-Ann Ho
IPC分类号： G06F7/57 , G06F7/38 , G06F7/00
CPC分类号： G06F7/483 , G06F2207/3844 , G06F7/49957
摘要： A computer system supporting multiple floating point architectures. In an embodiment of the invention, a floating point unit (FPU) is optimized for hex format. The FPU uses a hex internal dataflow with a with an exponent and bias sufficient to support a binary floating point architecture. The FPU includes format conversion means, rounding means, sticky bit calculation means, and special number control means to execute binary floating point operations according to the IEEE 754 standard. An embodiment of the invention provides a system for executing floating point operations in either IBM S/390 hexadecimal format or IEEE 754 binary format.
摘要翻译：支持多种浮点架构的计算机系统。在本发明的实施例中，针对十六进制格式优化了浮点单元（FPU）。 FPU使用十六进制内部数据流，其中指数和偏差足以支持二进制浮点架构。 FPU包括格式转换装置，舍入装置，粘点计算装置和专用号码控制装置，以根据IEEE 754标准执行二进制浮点运算。本发明的实施例提供了一种用于以IBM S / 390十六进制格式或IEEE 754二进制格式执行浮点运算的系统。

9. 发明授权

US6119219A System serialization with early release of individual processor 失效
标题翻译：系统串行化与早期发布的单个处理器
公开(公告)号：US6119219A
公开(公告)日：2000-09-12
申请号：US70595
申请日：1998-04-30
申请人： Charles Franklin Webb , Dean G. Bair , Mark Steven Farrell , Barry Watson Krumm , Pak-kin Mak , Jennifer Almoradie Navarro , Timothy John Slegel
发明人： Charles Franklin Webb , Dean G. Bair , Mark Steven Farrell , Barry Watson Krumm , Pak-kin Mak , Jennifer Almoradie Navarro , Timothy John Slegel
IPC分类号： G06F15/177 , G06F9/30 , G06F9/318 , G06F9/38 , G06F9/52 , G06F9/00
CPC分类号： G06F9/3861 , G06F9/3004 , G06F9/30087 , G06F9/30101 , G06F9/3017 , G06F9/3834
摘要： A pipelined multiprocessor system for ESA/390 operations which executes a simple instruction set in a hardware controlled execution unit and executes a complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in the hardware controlled execution unit, comprising a plurality of CPU processors each of which is part of said multiprocessing system and capable of generating and responding to a quiesce request, and controls for system operations which allow the CPUs in the ESA/390 system to process the local buffer update portion of IPTE and SSKE operations without waiting for all other processors to reach an interruptible point, and then to continue program execution with minor temporary restrictions on operations until the IPTE or SSKE operation is globally completed. In addition, Licensed Internal Code (LIC) sequences are defined which allow these IPTE and SSKE operations to co-exist with other operations which require conventional system quiescing (i.e. all processors must pause together), and to allow for CPU retry actions on any of the CPUs in the system at any point in the operation.
摘要翻译：一种用于ESA / 390操作的流水线多处理器系统，其执行硬件控制执行单元中的简单指令集，并且以硬模式设计状态以硬计算执行单元中的简单指令的毫位序列执行复指令集，包括多个CPU处理器，每个CPU处理器都是所述多处理系统的一部分并且能够产生和响应静默请求，并且控制允许ESA / 390系统中的CPU处理IPTE和SSKE的本地缓冲器更新部分的系统操作操作，而不等待所有其他处理器到达可中断点，然后继续执行程序，对操作进行轻微的临时限制，直到IPTE或SSKE操作全局完成。此外，定义了许可内码（LIC）序列，允许这些IPTE和SSKE操作与需要常规系统静止的其他操作（即，所有处理器必须暂停在一起）并存，并允许对任何 CPU在系统中的任何一点操作。

10. 发明授权

US6085313A Computer processor system for executing RXE format floating point instructions 失效
标题翻译：用于执行RXE格式浮点指令的计算机处理器系统
公开(公告)号：US6085313A
公开(公告)日：2000-07-04
申请号：US070198
申请日：1998-04-30
申请人： Mark Anthony Check , Ronald M. Smith, Sr. , John Stephen Liptay , Eric Mark Schwarz , Timothy John Slegel , Charles Franklin Webb
发明人： Mark Anthony Check , Ronald M. Smith, Sr. , John Stephen Liptay , Eric Mark Schwarz , Timothy John Slegel , Charles Franklin Webb
IPC分类号： G06F9/355 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30145
摘要： A computer processor system having a floating point processor for instructions which are processed in a six cycle pipeline, in which prior to the first cycle of the pipeline an instruction text is fetched, and during the first cycle for the fetched particular instruction it is decoded and the base (B) and index (X) register values are read for use in address generation. Instructions of the RX-type are extended by placing the extension of the operation code beyond the first four bytes of the instruction format and to assign the operation codes in such a way that the machine may determine from the first 8 bits of the operation code alone, the exact format of the instruction. Instructions formats include the ESA/390 instructions SS, RR; RX; S; RRE; RI: and the new RXE instructions. where instructions of the RXE format have their R.sub.1, X.sub.2, B.sub.2, and D.sub.2 fields in the identical positions in said instruction register as in the RX format to enable the processor to determine from the first 8 bits of the operation code alone that an instruction being decoded is an RXE format instruction and the register indexed extensions of the RXE format instruction, after which it gates the correct information to said X-B-D adder. During the second cycle the address add of B+X+Displacement is performed and sent to the cache processor's, and during the third and fourth cycles the cache is respectively accessed and data is returned, and during a fifth cycle execution of the fetched instruction occurs with the result putaway in a sixth cycle.RXE instructions can be used for floating point processing and fixed point processing.
摘要翻译：一种计算机处理器系统，具有用于指令的浮点处理器，其在六个周期流水线中被处理，其中在流水线的第一周期之前取出指令文本，并且在所读取的特定指令的第一周期期间对其进行解码，读取基地址（B）和索引（X）寄存器值以用于地址生成。通过将操作代码的扩展置于指令格式的前四个字节之外来扩展RX类型的指令，并且以这样的方式分配操作代码，使得机器可以仅从操作代码的前8位确定，指令的确切格式。指令格式包括ESA / 390指令SS，RR; RX; S; RRE; RI：和新的RXE指令。其中RXE格式的指令在RX格式中在所述指令寄存器中的相同位置具有它们的R1，X2，B2和D2字段，以使处理器仅从操作代码的前8位确定指令为解码的是RXE格式指令和RXE格式指令的寄存器索引扩展，然后将正确的信息写入所述XBD加法器。在第二周期期间，执行B + X +位移的地址添加并发送到高速缓存处理器，并且在第三和第四周期期间，分别访问高速缓存并返回数据，并且在第五周期期间执行所提取的指令结果放在第六个循环中.RXE指令可用于浮点处理和定点处理。

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