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1. 发明授权

US07966453B2 Method and apparatus for active software disown of cache line's exlusive rights 有权
标题翻译：主动软件的方法和装置取消了缓存行的隐藏权限
公开(公告)号：US07966453B2
公开(公告)日：2011-06-21
申请号：US11954374
申请日：2007-12-12
申请人： Chung-Lung Kevin Shum , Kathryn Marie Jackson , Charles Franklin Webb
发明人： Chung-Lung Kevin Shum , Kathryn Marie Jackson , Charles Franklin Webb
IPC分类号： G06F13/00
CPC分类号： G06F12/084 , G06F3/0614 , G06F3/064 , G06F3/0679 , G06F12/0802 , G06F12/0811 , G06F12/0817 , G06F12/0833 , G06F12/0837 , G06F12/0842 , G06F12/0875 , G06F12/128 , G06F2212/1016 , G06F2212/283 , G06F2212/314 , G06F2212/452 , G06F2212/6042 , G06F2212/621 , G06F2212/69
摘要： Software indicates to hardware of a processing system that its storage modification to a particular cache line is done, and will not be doing any modification for the time being. With this indication, the processor actively releases its exclusive ownership by updating its line ownership from exclusive to read-only (or shared) in its own cache directory and in the storage controller (SC). By actively giving up the exclusive rights, another processor can immediately be given exclusive ownership to that said cache line without waiting on any processor's explicit cross invalidate acknowledgement. This invention also describes the hardware design needed to provide this support.
摘要翻译：软件向处理系统的硬件指示其对特定高速缓存行的存储修改已完成，并且暂时不进行任何修改。有了这个指示，处理器通过将其所有权从排他性更新到其自己的高速缓存目录和存储控制器（SC）中的只读（或共享）来主动释放其独占所有权。通过积极放弃专有权，另一个处理器可以立即被给予所述高速缓存行的独占所有权，而不用等待任何处理器的明确的交叉无效确认。本发明还描述了提供此支持所需的硬件设计。

2. 发明授权

US08880805B2 Computer system having cache subsystem performing demote requests 有权
标题翻译：具有缓存子系统的计算机系统执行降级请求
公开(公告)号：US08880805B2
公开(公告)日：2014-11-04
申请号：US13105235
申请日：2011-05-11
申请人： Chung-Lung Kevin Shum , Kathryn Marie Jackson , Charles Franklin Webb
发明人： Chung-Lung Kevin Shum , Kathryn Marie Jackson , Charles Franklin Webb
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F3/0614 , G06F3/064 , G06F3/0679 , G06F12/0802 , G06F12/0811 , G06F12/0817 , G06F12/0833 , G06F12/0837 , G06F12/0842 , G06F12/0875 , G06F12/128 , G06F2212/1016 , G06F2212/283 , G06F2212/314 , G06F2212/452 , G06F2212/6042 , G06F2212/621 , G06F2212/69
摘要： Computer system having cache subsystem wherein demote requests are performed by the cache subsystem. Software indicates to hardware of a processing system that its storage modification to a particular cache line is done, and will not be doing any modification for the time being. With this indication, the processor actively releases its exclusive ownership by updating its line ownership from exclusive to read-only (or shared) in its own cache directory and in the storage controller (SC). By actively giving up the exclusive rights, another processor can immediately be given exclusive ownership to that said cache line without waiting on any processor's explicit cross invalidate acknowledgement. This invention also describes the hardware design needed to provide this support.
摘要翻译：具有缓存子系统的计算机系统，其中降级请求由高速缓存子系统执行。软件向处理系统的硬件指示其对特定高速缓存行的存储修改已完成，并且暂时不进行任何修改。有了这个指示，处理器通过将其所有权从排他性更新到其自己的高速缓存目录和存储控制器（SC）中的只读（或共享）来主动释放其独占所有权。通过积极放弃专有权，另一个处理器可以立即被给予所述高速缓存行的独占所有权，而不用等待任何处理器的明确的交叉无效确认。本发明还描述了提供此支持所需的硬件设计。

3. 发明申请

US20120124292A1 Computer System Having Cache Subsystem Performing Demote Requests 有权
标题翻译：具有缓存子系统的计算机系统执行降级请求
公开(公告)号：US20120124292A1
公开(公告)日：2012-05-17
申请号：US13105235
申请日：2011-05-11
申请人： Chung-Lung Kevin Shum , Kathryn Marie Jackson , Charles Franklin Webb
发明人： Chung-Lung Kevin Shum , Kathryn Marie Jackson , Charles Franklin Webb
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F3/0614 , G06F3/064 , G06F3/0679 , G06F12/0802 , G06F12/0811 , G06F12/0817 , G06F12/0833 , G06F12/0837 , G06F12/0842 , G06F12/0875 , G06F12/128 , G06F2212/1016 , G06F2212/283 , G06F2212/314 , G06F2212/452 , G06F2212/6042 , G06F2212/621 , G06F2212/69
摘要： Computer system having cache subsystem wherein demote requests are performed by the cache subsystem. Software indicates to hardware of a processing system that its storage modification to a particular cache line is done, and will not be doing any modification for the time being. With this indication, the processor actively releases its exclusive ownership by updating its line ownership from exclusive to read-only (or shared) in its own cache directory and in the storage controller (SC). By actively giving up the exclusive rights, another processor can immediately be given exclusive ownership to that said cache line without waiting on any processor's explicit cross invalidate acknowledgement. This invention also describes the hardware design needed to provide this support.
摘要翻译：具有缓存子系统的计算机系统，其中降级请求由高速缓存子系统执行。软件向处理系统的硬件指示其对特定高速缓存行的存储修改已完成，并且暂时不进行任何修改。有了这个指示，处理器通过将其所有权从排他性更新到其自己的高速缓存目录和存储控制器（SC）中的只读（或共享）来主动释放其独占所有权。通过积极放弃专有权，另一个处理器可以立即被给予所述高速缓存行的独占所有权，而不用等待任何处理器的明确的交叉无效确认。本发明还描述了提供此支持所需的硬件设计。

4. 发明申请

US20090157965A1 Method and Apparatus for Active Software Disown of Cache Line's Exlusive Rights 有权
标题翻译：用于主动软件的方法和设备降低缓存线的隐藏权限
公开(公告)号：US20090157965A1
公开(公告)日：2009-06-18
申请号：US11954374
申请日：2007-12-12
申请人： Chung-Lung Kevin Shum , Kathryn Marie Jackson , Charles Franklin Webb
发明人： Chung-Lung Kevin Shum , Kathryn Marie Jackson , Charles Franklin Webb
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F3/0614 , G06F3/064 , G06F3/0679 , G06F12/0802 , G06F12/0811 , G06F12/0817 , G06F12/0833 , G06F12/0837 , G06F12/0842 , G06F12/0875 , G06F12/128 , G06F2212/1016 , G06F2212/283 , G06F2212/314 , G06F2212/452 , G06F2212/6042 , G06F2212/621 , G06F2212/69
摘要： Software indicates to hardware of a processing system that its storage modification to a particular cache line is done, and will not be doing any modification for the time being. With this indication, the processor actively releases its exclusive ownership by updating its line ownership from exclusive to read-only (or shared) in its own cache directory and in the storage controller (SC). By actively giving up the exclusive rights, another processor can immediately be given exclusive ownership to that said cache line without waiting on any processor's explicit cross invalidate acknowledgement. This invention also describes the hardware design needed to provide this support.
摘要翻译：软件向处理系统的硬件指示其对特定高速缓存行的存储修改已完成，并且暂时不进行任何修改。有了这个指示，处理器通过将其所有权从排他性更新到其自己的高速缓存目录和存储控制器（SC）中的只读（或共享）来主动释放其独占所有权。通过积极放弃专有权，另一个处理器可以立即被给予所述高速缓存行的独占所有权，而不用等待任何处理器的明确的交叉无效确认。本发明还描述了提供此支持所需的硬件设计。

5. 发明授权

US06233655B1 Method for Quad-word Storing into 2-way interleaved L1 cache 失效
标题翻译：用于四字存储到双向交错L1缓存的方法
公开(公告)号：US06233655B1
公开(公告)日：2001-05-15
申请号：US09070146
申请日：1998-04-30
申请人： Chung-Lung Kevin Shum , Wen He Li , Charles Franklin Webb
发明人： Chung-Lung Kevin Shum , Wen He Li , Charles Franklin Webb
IPC分类号： G06F1200
CPC分类号： G06F9/30043 , G06F12/0851 , G06F12/0886
摘要： A computer processor has an I-unit (instruction unit) and instruction decoder, an E-unit (execution unit), a Buffer Control Element (BCE) containing a unified two-way interleaved L1 cache and providing write control to said two-way interleaved L1 cache. The processor has Double Word wide execution dataflow. An instruction decoder receiving instruction data from a unified cache before decoding causes, for stores, I-unit logic to initiate a request ahead of execution to tell the buffer control element that stores will be made from the E-unit, and E-unit logic sends a store request to initiate a store after decoding corresponding instruction data which indicates what address in the cache the DoubleWord data is to be stored to. In the process, E-unit logic calculates, from source and destination address information address ranges information in an instruction, whether a corresponding multi-Double Word store with same byte data will result from the data patterns, and, when a multi-Double Word store could result, it enables the E-unit to request the writing of an incoming Double Word on the computer's data bus for both Double Word L1 cache interleaves using the same address for both to effectively write two consecutively addressed DoubleWords for the same cycle to achieve a Quad Word store in a cycle.
摘要翻译：计算机处理器具有I单元（指令单元）和指令解码器，E单元（执行单元），包含统一双向交错L1高速缓存的缓冲器控制元件（BCE），并向所述双向交错L1缓存。处理器具有双字宽执行数据流。在解码之前从统一高速缓存器接收指令数据的指令解码器使存储I单元逻辑在执行之前启动请求以告知缓冲器控制元件将从E单元进行存储，并且E单元逻辑在对相应的指令数据进行解码之后发送存储请求，以指示高速缓存中要存储的DoubleWord数据的哪个地址。在该过程中，E单元逻辑根据指令中的源地址信息和目的地址信息地址范围信息，计算出数据模式是否产生具有相同字节数据的对应多双字存储，以及当多单字存储可能导致，它使E单元能够使用相同的地址在计算机的数据总线上请求输入双字的双字L1高速缓存交错，以便在相同周期内有效地写入两个连续寻址的DoubleWords来实现一个四周商店在一个循环。

6. 发明授权

US08015362B2 Method and system for handling cache coherency for self-modifying code 有权
标题翻译：用于处理缓存一致性的自修改代码的方法和系统
公开(公告)号：US08015362B2
公开(公告)日：2011-09-06
申请号：US12031923
申请日：2008-02-15
申请人： Gregory W. Alexander , Christian Jacobi , Barry W. Krumm , Chung-Lung Kevin Shum , Aaron Tsai
发明人： Gregory W. Alexander , Christian Jacobi , Barry W. Krumm , Chung-Lung Kevin Shum , Aaron Tsai
IPC分类号： G06F12/00
CPC分类号： G06F12/0848 , G06F9/3812
摘要： A method for handling cache coherency includes allocating a tag when a cache line is not exclusive in a data cache for a store operation, and sending the tag and an exclusive fetch for the line to coherency logic. An invalidation request is sent within a minimum amount of time to an I-cache, preferably only if it has fetched to the line and has not been invalidated since, which request includes an address to be invalidated, the tag, and an indicator specifying the line is for a PSC operation. The method further includes comparing the request address against stored addresses of prefetched instructions, and in response to a match, sending a match indicator and the tag to an LSU, within a maximum amount of time. The match indicator is timed, relative to exclusive data return, such that the LSU can discard prefetched instructions following execution of the store operation that stores to a line subject to an exclusive data return, and for which the match is indicated.
摘要翻译：一种用于处理高速缓存一致性的方法包括当高速缓存行在存储操作的数据高速缓存中不排斥时分配标签，以及将该标签和该行的独占提取发送到一致性逻辑。无效请求在最小时间内被发送到I缓存，优选地只有当它已经被取出到该行并且没有被无效时，因为哪个请求包括要被无效的地址，该标签和一个指示线路用于PSC操作。该方法还包括将请求地址与预取指令的存储地址进行比较，并且响应于匹配，在最大时间量内向LSU发送匹配指示符和标签。匹配指示符相对于独占数据返回是定时的，使得LSU可以执行存储操作之后丢弃预取指令，存储到受独占数据返回的行，并且指示匹配。

7. 发明授权

US07890700B2 Method, system, and computer program product for cross-invalidation handling in a multi-level private cache 失效
标题翻译：用于多级私有缓存中的交叉无效处理的方法，系统和计算机程序产品
公开(公告)号：US07890700B2
公开(公告)日：2011-02-15
申请号：US12051736
申请日：2008-03-19
申请人： Ka Shan Choy , Jennifer A. Navarro , Chung-Lung Kevin Shum , Aaron Tsai
发明人： Ka Shan Choy , Jennifer A. Navarro , Chung-Lung Kevin Shum , Aaron Tsai
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0815
摘要： A method, system, and computer program product for cross-invalidation handling in a multi-level private cache are provided. The system includes a processor. The processor includes a fetch address register logic in communication with a level 1 data cache, a level 1 instruction cache, a level 2 cache, and a higher level cache. The processor also includes a set of cross-invalidate snapshot counter implemented in the fetch address register. Each cross-invalidate snapshot counter tracks an amount of pending higher level cross-invalidations received before new data for the corresponding cache miss is returned from the higher-level cache. The processor also includes logic executing on the fetch address register for handling level 1 data cache misses and interfacing with the level 2 cache. In response to the new data, and upon determining that older cross-invalidations are pending, the new data is prevented from being used by the processor.
摘要翻译：提供了一种用于在多级私有缓存中进行交叉无效处理的方法，系统和计算机程序产品。该系统包括一个处理器。处理器包括与1级数据高速缓存，1级指令高速缓存，2级高速缓存和更高级高速缓存通信的取指地址寄存器逻辑。该处理器还包括一组在获取地址寄存器中实现的交叉无效快照计数器。每个交叉无效快照计数器跟踪在从较高级别的缓存返回相应的高速缓存未命中的新数据之前接收到的未决更高级别的交叉无效的量。该处理器还包括在取出地址寄存器上执行的逻辑，用于处理1级数据高速缓存未命中并与2级缓存进行接口。响应于新数据，并且在确定旧的交叉无效正在等待时，防止新数据被处理器使用。

8. 发明申请

US20100241899A1 Debugging for multiple errors in a microprocessor environment 有权
标题翻译：在微处理器环境中调试多个错误
公开(公告)号：US20100241899A1
公开(公告)日：2010-09-23
申请号：US12405418
申请日：2009-03-17
申请人： Ulrich Mayer , Timothy John Slegel , Chung-Lung Kevin Shum , Frank Lehnert , Guenter Gerwig
发明人： Ulrich Mayer , Timothy John Slegel , Chung-Lung Kevin Shum , Frank Lehnert , Guenter Gerwig
IPC分类号： G06F11/20 , G06F9/30
CPC分类号： G06F11/1407 , G06F9/3863 , G06F9/3865 , G06F11/0721 , G06F11/076 , G06F11/0772
摘要： A new method and apparatus have been taught for storing error information used for debugging as generated by the initial and subsequent error occurrences. In this invention, a register with several bit ranges is used to store error information. The first bit-range is allocated to the initial error information. If the total number of the errors exceeds the capacity of the register, the last error is kept in a last bit-range. This way, precious initial error information (as well as the last error information) will be available for debugging.
摘要翻译：已经教导了一种新的方法和装置，用于存储由初始和随后的错误发生产生的用于调试的错误信息。在本发明中，使用具有多个位范围的寄存器来存储错误信息。第一个比特范围被分配给初始的错误信息。如果错误总数超过寄存器的容量，则最后一个错误将保留在最后一个位范围内。这样，宝贵的初始错误信息（以及最后一个错误信息）将可用于调试。

9. 发明申请

US20090240922A1 METHOD, SYSTEM, COMPUTER PROGRAM PRODUCT, AND HARDWARE PRODUCT FOR IMPLEMENTING RESULT FORWARDING BETWEEN DIFFERENTLY SIZED OPERANDS IN A SUPERSCALAR PROCESSOR 失效
标题翻译：方法，系统，计算机程序产品和用于在超级处理器中执行不同尺寸操作之前的结果的硬件产品
公开(公告)号：US20090240922A1
公开(公告)日：2009-09-24
申请号：US12051792
申请日：2008-03-19
申请人： David S. Hutton , Fadi Y. Busaba , Bruce C. Giamei , Christopher A. Krygowski , Edward T. Malley , Jeffrey S. Plate , John G. Rell, JR. , Chung-Lung Kevin Shum , Timothy J. Slegel
发明人： David S. Hutton , Fadi Y. Busaba , Bruce C. Giamei , Christopher A. Krygowski , Edward T. Malley , Jeffrey S. Plate , John G. Rell, JR. , Chung-Lung Kevin Shum , Timothy J. Slegel
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30036 , G06F9/3828
摘要： Result and operand forwarding is provided between differently sized operands in a superscalar processor by grouping a first set of instructions for operand forwarding, and grouping a second set of instructions for result forwarding, the first set of instructions comprising a first source instruction having a first operand and a first dependent instruction having a second operand, the first dependent instruction depending from the first source instruction; the second set of instructions comprising a second source instruction having a third operand and a second dependent instruction having a fourth operand, the second dependent instruction depending from the second source instruction, performing operand forwarding by forwarding the first operand, either whole or in part, as it is being read to the first dependent instruction prior to execution; performing result forwarding by forwarding a result of the second source instruction, either whole or in part, to the second dependent instruction, after execution; wherein the operand forwarding is performed by executing the first source instruction together with the first dependent instruction; and wherein the result forwarding is performed by executing the second source instruction together with the second dependent instruction.
摘要翻译：通过对用于操作数转发的第一组指令进行分组，以及对用于结果转发的第二组指令进行分组，在超标量处理器中的不同大小的操作数之间提供结果和操作数转发，所述第一组指令包括具有第一操作数的第一源指令以及具有第二操作数的第一依赖指令，所述第一依赖指令取决于所述第一源指令; 所述第二组指令包括具有第三操作数和第二从属指令的第二源指令，所述第三操作数和第二从属指令具有第四操作数，所述第二依赖指令取决于所述第二源指令，通过转发所述第一操作数全部或部分地执行操作数转发，因为它在执行之前被读取到第一个依赖指令; 执行结果转发，将第二源指令的结果全部或部分转发到第二依赖指令; 其中通过与第一依赖指令一起执行第一源指令来执行操作数转发; 并且其中通过与第二从属指令一起执行第二源指令来执行结果转发。

10. 发明申请

US20090217002A1 SYSTEM AND METHOD FOR PROVIDING ASYNCHRONOUS DYNAMIC MILLICODE ENTRY PREDICTION 失效
标题翻译：用于提供异步动态MILLICODE入侵预测的系统和方法
公开(公告)号：US20090217002A1
公开(公告)日：2009-08-27
申请号：US12035109
申请日：2008-02-21
申请人： James J. Bonanno , Brian R. Prasky , John G. Rell, JR. , Anthony Saporito , Chung-Lung Kevin Shum
发明人： James J. Bonanno , Brian R. Prasky , John G. Rell, JR. , Anthony Saporito , Chung-Lung Kevin Shum
IPC分类号： G06F9/312
CPC分类号： G06F9/3017 , G06F9/30145 , G06F9/30174 , G06F9/3806
摘要： A system and method for asynchronous dynamic millicode entry prediction in a processor are provided. The system includes a branch target buffer (BTB) to hold branch information. The branch information includes: a branch type indicating that the branch represents a millicode entry (mcentry) instruction targeting a millicode subroutine, and an instruction length code (ILC) associated with the mcentry instruction. The system also includes search logic to perform a method. The method includes locating a branch address in the BTB for the mcentry instruction targeting the millicode subroutine, and determining a return address to return from the millicode subroutine as a function of the an instruction address of the mcentry instruction and the ILC. The system further includes instruction fetch controls to fetch instructions of the millicode subroutine asynchronous to the search logic. The search logic may also operate asynchronous with respect to an instruction decode unit.
摘要翻译：提供了一种用于在处理器中进行异步动态毫代码入口预测的系统和方法。该系统包括用于保存分支信息的分支目标缓冲器（BTB）。分支信息包括：分支类型，指示分支表示针对毫微米子例程的毫米条目（中心）指令，以及与中心指令相关联的指令长度代码（ILC）。该系统还包括执行方法的搜索逻辑。该方法包括将BTB中的分支地址定位到针对毫秒子程序的中心指令，以及根据中心指令和ILC的指令地址确定返回地址，以从millicode子程序返回。该系统还包括指令获取控制以获取与搜索逻辑异步的毫微数子程序的指令。搜索逻辑也可以相对于指令解码单元进行异步操作。

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