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21. 发明申请

US20110320851A1 PORT ENABLE SIGNAL GENERATION FOR GATING A MEMORY ARRAY DEVICE OUTPUT 有权
标题翻译：端口使能信号生成用于获取存储器阵列设备输出
公开(公告)号：US20110320851A1
公开(公告)日：2011-12-29
申请号：US12822021
申请日：2010-06-23
申请人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar Vora
发明人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar Vora
IPC分类号： G06F1/12 , G06F1/04
CPC分类号： G06F1/10 , G11C11/419
摘要： A method of generating a dynamic port enable signal for gating memory array data to an output node includes generating a programmable leading edge clock signal derivation of an input dynamic clock signal; generating a programmable trailing edge clock signal derivation of the input dynamic clock signal, wherein the leading edge clock signal derivation and the trailing edge clock signal derivation are independently programmable with respect to one another; and gating the generated programmable leading and trailing edge clock signal derivations with a static input enable signal so as to generate the port enable signal such that, when inactive, the port enable signal prevents early memory array data from being coupled to the output node.
摘要翻译：产生用于将存储器阵列数据门控到输出节点的动态端口使能信号的方法包括产生输入动态时钟信号的可编程前沿时钟信号导出; 产生所述输入动态时钟信号的可编程后沿时钟信号导出，其中所述前沿时钟信号导出和所述后沿时钟信号导出可相对于彼此独立地可编程; 以及利用静态输入使能信号选通产生的可编程前导和后沿时钟信号导出，以便产生端口使能信号，使得当非活动时，端口使能信号防止早期存储器阵列数据耦合到输出节点。

22. 发明申请

US20110317496A1 JAM LATCH FOR LATCHING MEMORY ARRAY OUTPUT DATA 失效
标题翻译：用于锁定内存阵列输出数据的JAM LATCH
公开(公告)号：US20110317496A1
公开(公告)日：2011-12-29
申请号：US12822038
申请日：2010-06-23
申请人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar Vora
发明人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar Vora
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/106 , G11C11/413
摘要： A jam latch device for a data node includes a feed forward inverter having an input coupled to the data node; a feedback inverter having an input connected to an output of the feed forward inverter with an output of the feedback inverter connected to the data node; an isolation device that selectively decouples the feedback inverter from a power supply rail, the isolation device controlled by a clock signal of a reset device that resets the data node to a first logic state such that decoupling of the feedback inverter from the power supply rail coincides with resetting the data node to the first logic state; and a margin test device that selectively increases pull down strength of the feedback inverter.
摘要翻译：用于数据节点的卡锁装置包括：前馈反相器，其具有耦合到数据节点的输入; 反馈逆变器，其具有连接到所述前馈逆变器的输出的输入端，所述反馈反相器的输出连接到所述数据节点; 隔离装置，其将反馈反相器与电源轨选择性地分离，该隔离装置由复位装置的时钟信号控制，该复位装置将数据节点复位到第一逻辑状态，使得反馈反相器与电源轨的解耦一致将数据节点重置为第一逻辑状态; 以及选择性地增加反馈逆变器的下拉强度的余量测试装置。

23. 发明授权

US08299833B2 Programmable control clock circuit including scan mode 失效
标题翻译：可编程控制时钟电路包括扫描模式
公开(公告)号：US08299833B2
公开(公告)日：2012-10-30
申请号：US12796970
申请日：2010-06-09
申请人： Paul A. Bunce , Yuen H. Chan , John D. Davis , Richard E. Serton
发明人： Paul A. Bunce , Yuen H. Chan , John D. Davis , Richard E. Serton
IPC分类号： H03K3/017
CPC分类号： H03K5/156
摘要： A programmable clock control circuit includes a base block configured to control operation of the programmable clock control circuit and a chop block configured to control the width of an output clock signal of the programmable clock control circuit. The circuit also includes a pulse width variation block providing a pulse width variation output to the base block, the base block output being variable to provide at least three different output pulse widths. The circuit also includes a launch clock delay block coupled to delay the output of the base block and a scan clock delay block to delay the output pulse and a selector that causes either the scan clock delay block or the launch clock delay block to be active based on a value of a scan gate signal.
摘要翻译：可编程时钟控制电路包括被配置为控制可编程时钟控制电路的操作的基本块和被配置为控制可编程时钟控制电路的输出时钟信号的宽度的斩波块。电路还包括提供脉冲宽度变化输出到基本块的脉冲宽度变化块，基本块输出是可变的以提供至少三个不同的输出脉冲宽度。电路还包括发射时钟延迟块，其耦合以延迟基本块的输出和延迟输出脉冲的扫描时钟延迟块和使得扫描时钟延迟块或启动时钟延迟块基于有源的选择器对扫描门信号的值。

24. 发明申请

US20110317505A1 INTERNAL BYPASSING OF MEMORY ARRAY DEVICES 有权
标题翻译：内存阵列设备的内部旁路
公开(公告)号：US20110317505A1
公开(公告)日：2011-12-29
申请号：US12822058
申请日：2010-06-23
申请人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar Vora
发明人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar Vora
IPC分类号： G11C7/00
CPC分类号： G11C16/02 , G11C7/1048 , G11C11/413 , G11C2207/002
摘要： An output control circuit for a memory array includes a latched output node precharged to a first logic state prior to both a read and write operation; first logic that couples memory cell data from a memory read path to the output node during the read operation, the first logic controlled by a timing signal; second logic that internally bypasses the memory read path during a write operation by decoupling it from the output node, such that a logical derivative of write data written to the memory array is also coupled to the output node, the second logic also controlled by the timing signal; and wherein a transition of the output node from the first logic state to a second logic state during the write operation occurs within a time range as that of the same transition during the read operation.
摘要翻译：用于存储器阵列的输出控制电路包括在读取和写入操作之前预先充电到第一逻辑状态的锁存输出节点; 在读取操作期间将存储器单元数据从存储器读取路径耦合到输出节点的第一逻辑，由定时信号控制的第一逻辑; 第二逻辑，其在写入操作期间通过将其与输出节点分离而在内部旁路存储器读取路径，使得写入存储器阵列的写入数据的逻辑导数也耦合到输出节点，第二逻辑也由定时控制信号; 并且其中，所述输出节点在所述写入操作期间从所述第一逻辑状态到第二逻辑状态的转变在与所述读取操作期间相同转换的时间范围内发生。

25. 发明授权

US08345490B2 Split voltage level restore and evaluate clock signals for memory address decoding 有权
标题翻译：分离电压电平恢复和评估用于存储器地址解码的时钟信号
公开(公告)号：US08345490B2
公开(公告)日：2013-01-01
申请号：US12821824
申请日：2010-06-23
申请人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar J. Vora
发明人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar J. Vora
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/222 , G11C8/10
摘要： A method of implementing voltage level shifting for a memory device includes coupling one or more evaluation clock signals to a memory address decode circuit, the one or more evaluation clock signals operating at a first voltage supply level; and coupling a restore clock signal to the memory address decode circuit, the restore clock signal operating at a second voltage supply level that is higher than the first voltage supply level; wherein one or more outputs of the memory address decode circuit operate at the second voltage supply level.
摘要翻译：实现存储器件的电压电平移位的方法包括将一个或多个评估时钟信号耦合到存储器地址解码电路，所述一个或多个评估时钟信号以第一电压供应电平工作; 以及将恢复时钟信号耦合到存储器地址解码电路，所述还原时钟信号在高于所述第一电压供应电平的第二电压供应电平下工作; 其中存储器地址解码电路的一个或多个输出在第二电压供应电平下工作。

26. 发明申请

US20110317499A1 SPLIT VOLTAGE LEVEL RESTORE AND EVALUATE CLOCK SIGNALS FOR MEMORY ADDRESS DECODING 有权
标题翻译：分离电压电平恢复和评估用于存储器地址解码的时钟信号
公开(公告)号：US20110317499A1
公开(公告)日：2011-12-29
申请号：US12821824
申请日：2010-06-23
申请人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar Vora
发明人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar Vora
IPC分类号： G11C7/00 , G11C8/10
CPC分类号： G11C7/22 , G11C7/222 , G11C8/10
摘要： A method of implementing voltage level shifting for a memory device includes coupling one or more evaluation clock signals to a memory address decode circuit, the one or more evaluation clock signals operating at a first voltage supply level; and coupling a restore clock signal to the memory address decode circuit, the restore clock signal operating at a second voltage supply level that is higher than the first voltage supply level; wherein one or more outputs of the memory address decode circuit operate at the second voltage supply level.
摘要翻译：实现存储器件的电压电平移位的方法包括将一个或多个评估时钟信号耦合到存储器地址解码电路，所述一个或多个评估时钟信号以第一电压供应电平工作; 以及将恢复时钟信号耦合到存储器地址解码电路，所述还原时钟信号在高于所述第一电压供应电平的第二电压供应电平下工作; 其中存储器地址解码电路的一个或多个输出在第二电压供应电平下工作。

27. 发明申请

US20110304370A1 PROGRAMMABLE CONTROL CLOCK CIRCUIT INCLUDING SCAN MODE 失效
标题翻译：可编程控制时钟电路，包括扫描模式
公开(公告)号：US20110304370A1
公开(公告)日：2011-12-15
申请号：US12796970
申请日：2010-06-09
申请人： Paul A. Bunce , Yuen H. Chan , John D. Davis , Richard E. Serton
发明人： Paul A. Bunce , Yuen H. Chan , John D. Davis , Richard E. Serton
IPC分类号： H03K5/04
CPC分类号： H03K5/156
摘要： A programmable clock control circuit includes a base block configured to control operation of the programmable clock control circuit and a chop block configured to control the width of an output clock signal of the programmable clock control circuit. The circuit also includes a pulse width variation block providing a pulse width variation output to the base block, the base block output being variable to provide at least three different output pulse widths. The circuit also includes a launch clock delay block coupled to delay the output of the base block and a scan clock delay block to delay the output pulse and a selector that causes either the scan clock delay block or the launch clock delay block to be active based on a value of a scan gate signal.
摘要翻译：可编程时钟控制电路包括被配置为控制可编程时钟控制电路的操作的基本块和被配置为控制可编程时钟控制电路的输出时钟信号的宽度的斩波块。电路还包括提供脉冲宽度变化输出到基本块的脉冲宽度变化块，基本块输出是可变的以提供至少三个不同的输出脉冲宽度。电路还包括发射时钟延迟块，其耦合以延迟基本块的输出和延迟输出脉冲的扫描时钟延迟块和使得扫描时钟延迟块或启动时钟延迟块基于有源的选择器对扫描门信号的值。

28. 外观设计

USD851145S1 Modular flywheel holesaw 有权
公开(公告)号：USD851145S1
公开(公告)日：2019-06-11
申请号：US29672090
申请日：2018-12-03
申请人： John D. Davis
设计人： John D. Davis
摘要： FIG. 1 is a frontal perspective view of the invention.
FIG. 2 is a back perspective view of the invention.
FIG. 3 is a front view of the invention.
FIG. 4 is a back view of the invention; and,
FIG. 5 is a side view of the invention.

29. 发明申请

US20140348611A1 Dual Actuated Nut And/Or Bolt Head With Reversed Thinned Jackscrews And Washer/Nut Castle Interlock 审中-公开
标题翻译：双驱动螺母和/或螺栓头与反转变薄的千斤顶和洗衣机/坚果城堡联锁
公开(公告)号：US20140348611A1
公开(公告)日：2014-11-27
申请号：US14283198
申请日：2014-05-20
申请人： John D. Davis
发明人： John D. Davis
IPC分类号： F16B39/12
CPC分类号： F16B43/02 , F16B39/10
摘要： A jackscrew nut and/or bolt head assembly includes a bottom washer that is interlocked via circumferentially arrayed castle extensions and recesses. Spherical faces at the washer top are thereby held in alignment with corresponding spherical jackscrew bottoms, which assures evenly distributed contact pressures during out of angle elastic jackscrew displacement during jackscrew loading. The bottom washer interlock may provide further for a transfer of a primary pre tightening torque exerted onto the main body of the nut and/or bolt head via a tool that concurrently accesses all jackscrew heads extending above the main body. The assembly may be initially tightened via the primary torque whereby secondary jackscrew actuation and displacement is greatly reduced. The jackscrews are thinned in reverse for maximum contact area at their spherical bottoms.
摘要翻译：螺旋螺母和/或螺栓头组件包括底部垫圈，其通过周向排列的城堡延伸部和凹部互锁。因此，垫圈顶部的球形面保持与对应的球形顶螺旋底座对准，这保证了在起重螺旋桨装载期间的角度之前的弹性起重螺丝刀位移期间的均匀分布的接触压力。底部垫圈联锁装置可以进一步提供通过同时访问在主体上方延伸的所有顶螺旋头的工具传递施加到螺母和/或螺栓头主体上的初级预紧力矩。组件可以首先通过主扭矩紧固，从而大大减少次级起重螺丝起子和排量。在其球形底部的最大接触面积处，顶针螺纹相反地变薄。

30. 发明申请

US20130054936A1 REMAPPING INOPERABLE MEMORY BLOCKS USING POINTERS 有权
标题翻译：使用指示灯重新取代无法使用的记忆块
公开(公告)号：US20130054936A1
公开(公告)日：2013-02-28
申请号：US13218480
申请日：2011-08-26
申请人： John D. Davis
发明人： John D. Davis
IPC分类号： G06F12/12 , G06F12/10
CPC分类号： G11C29/76 , G11C13/0004
摘要： Inoperable bits are determined in a memory block. Rather than abandon the block as inoperable, a data structure is generated that includes at least one memory page pointer that identifies the location of the inoperable bits in the memory block. The data structure is stored in one of a group of memory blocks that are reserved for the data structures. A pointer to the data structure is stored in metadata associated with the memory block with the inoperable bits. When a later memory operation is received for the memory block, the pointer is retrieved from the metadata and the memory page pointers are used to avoid the inoperable bits.
摘要翻译：不可操作的位在存储器块中确定。不是将块放弃为不可操作，而是生成包括至少一个存储器页指针的数据结构，该存储器页指针标识存储器块中的不可操作位的位置。数据结构存储在为数据结构保留的一组存储块中。指向数据结构的指针存储在与不可操作的位相关联的与存储器块相关联的元数据中。当对于存储器块接收到较后的存储器操作时，从元数据中检索指针，并且使用存储器页指针来避免不可操作的位。

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